JP2004319316A - Electrode panel for pdp and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrode panel for a PDP aiming at fine patterning and reduction of electric resistance, and prevented from defective adhesion between respective layers. <P>SOLUTION: The electrode panel for PDP (front panel) 10 comprises a transparent electrode layer 12 formed on a transparent base plate 11, resistance lowering layers 13, 14 for lowering wiring resistance of the transparent electrode layer 12 formed thereon, a palladium-plated layer 15 formed on the resistance lowering layers 13, 14, for lowering the wiring resistance of the transparent electrode layer 12 in cooperation with the resistance lowering layers 13, 14, and a dielectric layer 16 covering the resistance lowering layers 13, 14 and the palladium-plated layer 15. An electrode panel for a PDP (back panel) comprises a resistance lowering layer formed on a base plate, a palladium-plated layer formed on the resistance lowering layer, separation walls arranged on the base plate, and a phosphor layer arranged between the separation walls so as to cover the resistance lowering layer and the palladium-plated layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
[Industrial applications]
The present invention relates to an electrode substrate for a PDP (Plasma Display Panel) and a manufacturing method.
[0002]
[Prior art]
2. Description of the Related Art In recent years, flat displays such as plasma displays, liquid crystal displays, and EL (Electro Luminescent) displays have been remarkably developed due to demands for thinner wall displays.
[0003]
Among these flat displays, the plasma display has a DC type plasma display in which electrodes are exposed to a discharge space and discharges only when a voltage is applied, and a DC type display in which electrodes are covered with a dielectric layer and are not exposed to the discharge space. There is an AC type plasma display which has a memory function by its action.
[0004]
Meanwhile, in a conventional plasma display, a silver paste and a copper paste are printed on a glass substrate to form a wiring pattern (for example, see Patent Document 1).
[0005]
[Patent Document 1]
JP 2000-204304 A
[0006]
[Problems to be solved by the invention]
However, the conventional method for forming a wiring pattern has a problem that a fine pattern cannot be formed due to printing. For example, the accuracy of electrode formation by silver paste printing was limited to about 100 μm.
[0007]
Further, an electrode formed by silver paste printing has a large electric resistance value, and has a problem that silver migration occurs and reliability is low.
[0008]
Further, in the electrodes of the AC plasma display, when the electrodes are formed of copper, they are oxidized by oxygen in the dielectric layer, and there is a problem that poor adhesion occurs between copper and the dielectric layer.
[0009]
Therefore, an object of the present invention is to provide a PDP electrode substrate and a manufacturing method capable of forming a fine pattern and reducing an electric resistance value and preventing poor adhesion between layers.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, an electrode substrate for a PDP provided on the front side of a PDP includes a transparent substrate, an electrode pattern layer formed on the transparent substrate, and an electrode pattern layer formed on the electrode pattern layer. A low-resistance layer for lowering the wiring resistance value, a palladium plating layer formed on the low-resistance layer, and a dielectric layer covering the low-resistance layer and the palladium plating layer. It is characterized by.
[0011]
In this case, the low-resistance layer includes an electroless nickel-substituted gold plating layer formed on the electrode pattern layer, and a copper plating layer formed on the electroless nickel-substituted gold plating layer. Is also good.
[0012]
Further, the electrode pattern layer may be formed of ITO.
[0013]
The PDP electrode substrate provided on the back side of the PDP includes a substrate, a low-resistance layer formed on the substrate, a palladium plating layer formed on the low-resistance layer, and a It is characterized by comprising: a provided partition; and a phosphor layer formed between the partition to cover the low resistance layer and the palladium plating layer.
[0014]
In this case, the low-resistance layer includes an electroless nickel-substituted gold plating layer formed on the electrode pattern layer, and a copper plating layer formed on the electroless nickel-substituted gold plating layer. Is also good.
[0015]
Also, a method for manufacturing a PDP electrode substrate provided on the front side of a PDP includes an electrode pattern forming step of forming an electrode pattern on a transparent substrate, and forming a first low resistance layer on the transparent substrate and the electrode pattern layer. Forming a first low-resistance layer, forming a resist layer having a predetermined pattern on the first low-resistance layer, and not forming the resist layer on the first low-resistance layer. Forming a second low-resistance layer at a position, forming a palladium plating layer on the second low-resistance layer, and stripping the resist layer The method is characterized by comprising a resist stripping step and an etching step of etching the first low-resistance layer.
[0016]
In this case, a dielectric layer forming step of forming a dielectric layer to cover the electrode pattern layer, the first low resistance layer, the second low resistance layer, and the palladium plating layer; A black stripe forming step of forming a black stripe.
[0017]
Further, in the first resistance lowering layer forming step, an electroless nickel-substituted gold plating layer may be formed on the electrode pattern by electroless plating.
[0018]
Further, in the step of forming the second low resistance layer, an electrolytic copper plating layer may be formed on the first low resistance layer by electrolytic plating.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a preferred embodiment of the present invention will be described.
[1] Configuration of PDP electrode substrate (front panel)
FIG. 1 is a schematic cross-sectional view of a PDP electrode substrate (front plate) of the embodiment.
[0020]
The PDP electrode substrate (front plate) 10 is roughly divided into a transparent substrate 11, a transparent electrode layer 12 formed on the transparent substrate 11 in a predetermined pattern, and selectively formed on the transparent electrode layer 12. An electroless nickel-substituted gold plating layer 13, an electro-copper plating layer 14 formed on the electroless nickel-substituted gold plating layer 13, a palladium plating layer 15 formed on the electro-copper plating layer 14, a transparent electrode layer 12, It has a dielectric layer 16 formed so as to cover the electrolytic nickel-substituted gold plating layer 13, the electrolytic copper plating layer 14, and the palladium plating layer 15, and a black stripe layer 17 formed on the dielectric layer 16.
[0021]
As the transparent substrate 11, a non-flexible inflexible transparent material such as quartz glass, Pyrex glass (registered trademark), or a synthetic quartz plate, or a flexible transparent material such as a transparent resin film or an optical resin plate is used. be able to. In the following description, a material suitable for a black matrix substrate for a color liquid crystal display device using an active matrix method has a low coefficient of thermal expansion, excellent dimensional stability and workability in high-temperature heat treatment, and an alkali component in glass. And non-alkali glass containing no.
[0022]
The transparent electrode layer 12 is made of indium tin oxide (ITO: Indium Tin Oxide), zinc oxide (ZnO), tin oxide (SnO), an alloy thereof, or the like, using a sputtering method, a vacuum evaporation method, a CVD method, or the like. It can be formed by a general film forming method. The thickness of the transparent electrode layer 12 is about 0.01 to 1 μm, preferably about 0.03 to 0.5 μm. In the following description, it is assumed that indium tin oxide (ITO) is used for the transparent electrode layer 12.
[0023]
The electroless nickel-substituted gold plating layer 13 functions as a first resistance-lowering layer for lowering the resistance of the transparent electrode layer 12. The thickness of the electroless nickel-substituted gold plating layer 13 is 0.01 to 5.0 μm, and preferably about 0.1 to 1.0 μm.
[0024]
The electrolytic copper plating layer 14 functions as a second resistance reducing layer for reducing the resistance of the transparent electrode layer 12. The thickness of the electrolytic copper plating layer 14 is about 0.1 to 20 μm, and preferably about 1.0 to 10 μm.
[0025]
The palladium plating layer 15 is a layer for reducing the resistance of the transparent electrode layer 12, reducing the influence of oxygen contained in the dielectric layer 16, and improving the adhesion with the dielectric layer 16. The thickness of the palladium plating layer 15 is about 0.1 to 10 μm, preferably about 0.5 to 2.0 μm.
[0026]
The dielectric layer 16 protects the transparent electrode layer 12, the electroless nickel-substituted gold plating layer 13, the electrolytic copper plating layer 14, and the palladium plating layer 15, suppresses deterioration, and extends the life. The thickness of the dielectric layer 16 is about 0.5 to 20 μm, preferably about 1.0 to 5.0 μm.
[0027]
The black stripe layer 17 forms a black matrix pattern. The thickness of the black stripe layer 17 is about 0.05 to 10 μm, preferably about 0.1 to 1.0 μm.
[2] Method of manufacturing electrode plate (front plate) for PDP
Next, a method for manufacturing a PDP electrode plate (front plate) of the embodiment will be described with reference to FIGS.
[2.1] ITO sputtering process (step S1)
First, after cleaning the transparent substrate 11 according to a standard method, as shown in FIG. 2, an ITO layer which is the transparent electrode layer 12 is formed on one entire surface of the transparent substrate 11 by a sputtering method.
[2.2] Transparent electrode forming step (step S2)
Next, a photosensitive resist is applied on the ITO layer serving as the transparent electrode layer 12 to form a photosensitive resist layer (not shown). The photosensitive resist layer is exposed and developed through a photomask corresponding to a predetermined pattern. Then, the ITO layer serving as the transparent electrode layer 12 is etched and the photosensitive resist layer is removed to form the transparent electrode layer 12 having a predetermined pattern (Step S2).
[2.3] Electroless nickel-substituted gold plating layer forming step (step S3)
Subsequently, the transparent substrate 11 on which the transparent electrode layer 12 is formed is immersed in an electroless nickel-substituted gold plating solution, and the electroless nickel-substituted gold plating layer 13 is laminated on the transparent electrode layer 12 (step S3).
[0028]
This step of forming an electroless nickel-substituted gold plating layer is divided into two steps, and includes an electroless nickel-plated layer forming step and a substituted gold-plated layer forming step.
[0029]
First, the transparent substrate on which the transparent electrode layer 12 has been formed is immersed in an electroless nickel plating solution, an electroless nickel plating layer is laminated on the transparent electrode layer 12, and then immersed in a replacement gold plating solution. The substitutional gold plating layer 13 is made of nickel.
[0030]
The electroless plating solution used in the first electroless nickel plating layer forming step contains a reducing agent, a reducible heavy metal salt, a basic compound, and a buffer.
[0031]
Examples of the reducing agent include hypophosphorous acid, sodium hypophosphite, sodium borohydride, N-dimethylamine borane, borazine derivatives, hydrazine, formalin, and the like.
[0032]
Examples of the reducible heavy metal salts include water-soluble nickel reducible heavy metal salts.
[0033]
Examples of the basic compound include caustic soda, ammonium hydroxide, and the like that improve the plating rate, reduction efficiency, and the like.
[0034]
Examples of the buffer include pH adjusting agents such as inorganic acids and organic acids, oxycarboxylic acids such as sodium citrate and sodium acetate, boric acid, carbonic acid, organic acids, and alkali salts of inorganic acids.
[0035]
Further, the electroless plating solution contains, in addition to the reducing agent, the reducible heavy metal salt, the basic compound and the buffer, a complexing agent for stabilizing heavy metal ions, an accelerator, a stabilizer, and a surfactant. An electroless plating solution having the following is used. Further, two or more electroless plating solutions may be used in combination. For example, first, an electroless plating solution containing a boron-based reducing agent such as sodium borohydride, which easily forms a nucleus (for example, when palladium is used as a metal compound serving as a catalyst for electroless plating), is used. Next, an electroless plating solution containing a hypophosphorous acid-based reducing agent having a high metal deposition rate can be used.
[0036]
On the other hand, the replacement gold plating solution used in the replacement gold plating formation step contains, for example, gold potassium cyanide, gold sulfite, and sodium as metal salts to be reduced, and contains an organic acid such as citric acid, malic acid, and lactic acid as a chelating agent. .
[2.4] Plating resist forming step (Step S4)
Next, a photosensitive resist is applied on the electroless nickel-substituted gold plating layer 13 to form a photosensitive resist layer 21, and the photosensitive resist layer 21 is applied through a photomask having a predetermined pattern corresponding to the electrolytic copper plating layer 14. After exposure and development, the photosensitive resist layer 21 is removed from the portion where the electroplated copper layer 14 is formed on the electroless nickel-substituted gold plated layer 13 (step S4).
[2.5] Electrolytic copper plating layer forming step (step S5)
Subsequently, as shown in FIG. 3, the transparent substrate 11 on which the photosensitive resist layer which has been partially removed is formed is immersed in an electrolytic copper plating solution so that the transparent substrate 11 is placed at a predetermined position on the electroless nickel-substituted gold plating layer 13. The copper plating layer 14 is laminated (Step S5).
[2.6] Palladium plating layer forming step (step S6)
Next, the transparent substrate 11 on which the electrolytic copper plating layer 14 is formed is immersed in a palladium plating solution, and the palladium plating layer 15 is laminated on the electrolytic copper plating layer 14 (Step S6).
[0037]
The palladium plating solution used in this palladium plating layer forming step contains, for example, palladium chloride, palladium sulfate, palladium ammonium sulfate, palladium methanesulfonate as the metal salt to be reduced, and sodium sulfate, sodium phosphate, etc. as the conductive salt. Further, it contains citric acid, lactic acid, EDTA, ethylenediamine and the like as a chelating agent.
[2.7] Stripping of resist (Step S7)
Subsequently, the photosensitive resist layer 21 formed in step S4 is peeled off (step S7).
[2.8] Etching Step (Step S8)
Next, the electroless nickel-substituted gold plating layer 13 other than the portion corresponding to the portion where the palladium plating layer 15 is formed is removed by etching (step S8).
[2.9] Dielectric layer forming step (step S9)
Next, a dielectric layer 16 is formed by printing so as to cover the electroless nickel-substituted gold plating layer 13, the electrolytic copper plating layer 14, and the palladium plating layer 15 (step S9).
[0038]
Here, examples of the dielectric material used include a mixture of lead oxide and silicon dioxide.
[2.10] Black Stripe Layer Forming Step (Step S10)
Subsequently, a black stripe layer 17 is formed by printing at a position on the dielectric layer 16 corresponding to the formation position of the palladium plating layer 15 (therefore, the electrolytic copper plating layer 14 and the electroless nickel-substituted gold plating layer 13) (Step S10). .
[0039]
Through the above steps, the PDP electrode substrate (front plate) 10 is manufactured.
[0040]
As described above, according to the method of manufacturing the PDP electrode substrate (front plate) 10 of the present embodiment, since the wiring pattern is formed using a so-called photolithography process, it is easy to form a fine pattern. is there. Further, since the outermost surface of the wiring pattern is a palladium plating layer, the electric resistance can be reduced, and the adhesion can be improved without reaction with the dielectric layer. Further, the manufacturing cost can be reduced because of the wet method.
[3] Structure of PDP electrode substrate (back plate)
FIG. 4 shows a schematic sectional view of the PDP electrode substrate (back plate) of the embodiment.
[0041]
The PDP electrode substrate (back plate) 30 is roughly classified into a substrate 31, an electroless nickel-substituted gold plating layer 32 formed on the substrate 31, and an electrolytic copper plating formed on the electroless nickel-substituted gold plating layer 32. A layer 33, a palladium plating layer 34 formed on the electrolytic copper plating layer 33, and an address electrode formed by the electroless nickel-substituted gold plating layer 32, the electrolytic copper plating layer 33, and the palladium plating layer 34. A phosphor layer formed so as to cover an address electrode formed by a partition wall 35 (standing) and an electroless nickel-substituted gold plating layer 32, an electrolytic copper plating layer 33, and a palladium plating layer 34 between the pair of partition walls 35. 36.
[0042]
As the substrate 31, a non-flexible inflexible transparent material (transparent substrate) such as quartz glass, Pyrex glass (registered trademark), a synthetic quartz plate, or a flexible transparent material such as a resin film or an optical resin plate is used. (A transparent substrate or an opaque substrate) can be used. In the following description, a material suitable for a black matrix substrate for a color liquid crystal display device using an active matrix method has a low coefficient of thermal expansion, excellent dimensional stability and workability in high-temperature heat treatment, and an alkali component in glass. And non-alkali glass containing no.
[0043]
The electroless nickel-substituted gold plating layer 32 functions as a first low-resistance layer for reducing the resistance of the address electrode. The thickness of the electroless nickel-substituted gold plating layer 32 is 0.01 to 5.0 μm, and preferably about 0.1 to 1.0 μm.
[0044]
The electrolytic copper plating layer 33 functions as a second resistance-lowering layer for lowering the resistance of the address electrode. The thickness of the electrolytic copper plating layer 33 is 0.1 to 20.0 μm, preferably about 1.0 to 10 μm.
[0045]
The palladium plating layer 34 is a layer for reducing the resistance of the address electrode. The thickness of the palladium plating layer 34 is 0.1 to 10 μm, preferably about 0.5 to 2.0 μm.
[0046]
The partition wall 35 is erected along an address electrode formed by the electroless nickel-substituted gold plating layer 32, the electrolytic copper plating layer 33, and the palladium plating layer 34, and is formed by a thick film printing method to form a discharge cell. Things. The height of the partition wall 35 is about 0.2 mm.
[0047]
The phosphor layer 36 is formed by applying phosphors 36R, 36G, and 36B of R, G, and B colors by a printing method. The thickness of the phosphor layer 36 is about 0.1 to 20 μm, preferably about 0.5 to 5.0 μm.
[4] Method of manufacturing electrode plate (back plate) for PDP
Next, a method for manufacturing an electrode plate (back plate) for a PDP according to the embodiment will be described with reference to FIGS.
[4.1] Electroless nickel-substituted gold plating layer forming step (step S11)
First, after cleaning the substrate 31 according to a standard method, the entire surface of one side of the substrate 31 is immersed in an electroless nickel-substituted gold plating solution, and the electroless nickel-substituted gold plating layer 32 is laminated on the substrate 31 (step S11).
[0048]
The electroless nickel-substituted gold plating layer forming step is divided into two steps as described above, and includes an electroless nickel-plated layer forming step and a substituted gold plating layer-forming step. The details are as described above, and a description thereof will be omitted.
[4.2] Plating Resist Forming Step (Step S12)
Next, a photosensitive resist is applied on the electroless nickel-substituted gold plating layer 32 to form a photosensitive resist layer 41, and the photosensitive resist layer is applied through a photomask of a predetermined pattern corresponding to the electrolytic copper plating layer 33. After the exposure and development, the photosensitive resist layer 41 is removed from the portion where the electrolytic copper plating layer 33 is formed on the electroless nickel-substituted gold plating layer 32 (Step S12).
[4.3] Electric Copper Plating Layer Forming Step (Step S13)
Subsequently, the substrate 31 on which the partially removed photosensitive resist layer 41 is formed is immersed in an electrolytic copper plating solution to laminate an electrolytic copper plating layer 33 at a predetermined position on the electroless nickel-substituted gold plating layer 32. (Step S13).
[4.4] Palladium plating layer forming step (Step S14)
Next, the substrate 31 on which the electrolytic copper plating layer 33 is formed is immersed in a palladium plating solution, and the palladium plating layer 34 is laminated on the electrolytic copper plating layer 33 (Step S14).
[0049]
The palladium plating solution used in the palladium plating layer forming step includes, for example, palladium chloride, palladium sulfate, palladium ammonium sulfate, and palladium methanesulfonate as metal salts, sodium sulfate and sodium phosphate as conductive salts, and a chelating agent. Contains citric acid, lactic acid, EDTA, ethylenediamine and the like.
[4.5] Stripping of resist (Step S15)
Subsequently, the photosensitive resist layer 41 formed in step S12 is peeled off (step S15).
[4.6] Etching Step (Step S16)
Next, the electroless nickel-substituted gold plating layer 32 other than the portion corresponding to the portion where the palladium plating layer 34 is formed is removed by etching (step S16).
[4.7] Partition Wall Forming Step (Step S17)
Next, the partition wall 35 is formed by the thick film printing method so as to stand in parallel with the address electrode constituted by the electroless nickel-substituted gold plating layer 32, the electrolytic copper plating layer 33, and the palladium plating layer 15 (Step S17). .
[4.8] Phosphor Layer Forming Step (Step S18)
Subsequently, the corresponding phosphors 36R, 36G, and 36B are applied by printing between the pair of partition walls 35 to form the phosphor layer 36 (step S18).
[0050]
As described above, according to the method of manufacturing the PDP electrode substrate (back plate) 30 of the present embodiment, since a wiring pattern is formed using a so-called photolithography process, it is easy to form a fine pattern. is there. Further, since the outermost surface of the wiring pattern is a palladium plating layer, the electric resistance can be reduced, and the adhesion can be improved without reaction with the dielectric layer. Further, the manufacturing cost can be reduced because of the wet method.
[5] Effects of the embodiment
As described above, according to the PDP electrode substrate and the method of manufacturing the same according to the present embodiment, a fine wiring pattern is formed by a photolithography process instead of a printing process using a paste such as a copper paste. Since the resistance is reduced in the plating step of performing substitutional gold plating, electrolytic copper plating, and palladium plating, formation of a fine pattern and reduction in resistance can be realized at the same time.
[0051]
Further, in the front plate of the PDP electrode substrate, the palladium plating layer is not affected by oxygen in the dielectric layer and can withstand the baking temperature (for example, 540 [゜]) of the dielectric layer. The occurrence of defects can be reduced.
[0052]
Further, since a wet process is used, manufacturing costs can be reduced.
[0053]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[1] PDP electrode substrate (front panel)
A glass substrate (PD-200 glass manufactured by Asahi Glass Co., Ltd.) having a size of 300 [mm] × 300 [mm] and a thickness of 3 [mm] was prepared as a transparent substrate for forming a PDP electrode substrate (front plate). After washing the substrate according to a conventional method, an ITO layer (sheet resistance value: 20 Ω / □, thickness: 580 [Å]) was formed on one entire surface of the substrate by a sputtering method. Specifically, a request was made to Geomatic Co., Ltd., using a DC magnetron sputtering apparatus, using argon and oxygen as a discharge gas, and using indium tin oxide (ITO) as a target.
[0054]
Next, a photosensitive resist having the following composition was applied to form a photosensitive resist layer having a predetermined thickness.
Composition of photosensitive resist
10% aqueous solution of polyvinyl alcohol 20 parts by weight
(Gosenal T-330 manufactured by Nippon Synthetic Chemical Co., Ltd.)
20% aqueous solution of diazo resin… 0.8 parts by weight
(D-011 manufactured by Shinko Giken Co., Ltd.)
・ Pure water: 15 parts by weight
Next, with a proximity exposure machine using an ultra-high pressure mercury lamp as an exposure light source, a photosensitive exposure is performed at a predetermined exposure amount through a photomask provided with an opening (line width: 180 [μm]) corresponding to a transparent electrode formation pattern. The resist layer was exposed. Then, the transparent electrode layer 12 (transparent electrode pattern) was formed by developing using pure water.
[0055]
Next, the transparent substrate 11 on which the transparent electrode layer 12 is formed is immersed in an electroless plating solution of 83 [° C.] (FPD / NI manufactured by Technic Japan Co., Ltd.) for 5 minutes, and then washed with water and dried. The transparent substrate 11 on which the electrolytic nickel plating layer 14 is formed is immersed in an electroless plating solution (FPD / AU manufactured by Technic Japan Co., Ltd.) for 5 minutes, and then washed with water and dried to form the electroless nickel-substituted gold plating layer 13. Formed.
[0056]
Next, the above-mentioned photosensitive resist (OFPR-800, manufactured by Tokyo Ohka) is applied on the electroless nickel-substituted gold plating layer 13, and the pattern is equivalent to a transparent electrode formation pattern by a proximity exposure machine using an ultra-high pressure mercury lamp as an exposure light source. The photosensitive resist layer 21 was exposed at a predetermined exposure amount through a photomask provided with openings (line width 120 [μm], line interval 30 [μm]). Thereafter, by developing using pure water, the photosensitive resist layer 21 from which the formation pattern portion of the electrolytic copper plating layer 14 has been removed is formed.
[0057]
Subsequently, the transparent substrate 11 on which the photosensitive resist layer 14 which has been partially removed is formed is immersed in an electrolytic copper plating solution (Cover Glyme CLX manufactured by Shipley Co., Ltd.) so as to be in a predetermined position on the electroless nickel-substituted gold plating layer 13. Then, an electrolytic copper plating layer 14 is laminated.
[0058]
Further, the transparent substrate 11 on which the electrolytic copper plating layer 14 is formed is immersed in a palladium plating solution (Palladur 200 manufactured by Shipley), and the palladium plating layer 15 is laminated on the electrolytic copper plating layer 14.
[0059]
Subsequently, the photosensitive resist layer 21 is peeled off.
[0060]
Next, the electroless nickel-substituted gold plating layer 13 other than the portion corresponding to the portion where the palladium plating layer 15 is formed is etched with an etching solution (a gold stripping solution manufactured by Technic Japan Co., Ltd. and a nickel stripping solution which is a mixed acid of nitric acid: phosphoric acid = 4: 6). Immersion at 40 ° C. for 5 minutes).
[0061]
Next, a dielectric layer 16 is formed by printing so as to cover the electroless nickel-substituted gold plating layer 13, the electrolytic copper plating layer 14, and the palladium plating layer 15.
[0062]
Further, after requesting a microtechnology laboratory to form a resist in accordance with the formation position of the palladium plating layer 15 (and, consequently, the electrolytic copper plating layer 14 and the electroless nickel-substituted gold plating layer 13), the resist is formed on the dielectric layer 16. After plating at 90 ° C. for 6 minutes with a black stripe forming solution (FPD BK manufactured by Technic Japan Co., Ltd.) at the position, the plate is peeled off with a 50% nitric acid solution to form a black stripe layer 17.
[2] PDP electrode substrate (back plate)
A glass substrate (PD-200 glass manufactured by Asahi Glass Co., Ltd.) having a size of 300 [mm] × 300 [mm] and a thickness of 3 [mm] was prepared as a substrate 31 for forming a PDP electrode substrate (back plate). After the substrate 31 was washed according to a conventional method, the transparent electrode layer 12 was formed on the entire surface of one side of the substrate by sputtering using ITO.
[0063]
Next, the substrate 31 on which the transparent electrode layer 12 is formed is immersed in an electroless plating solution (FPD / NI manufactured by Technic Japan Co., Ltd.) for 5 minutes, and then washed with water and dried. The formed transparent substrate 11 is immersed in an electroless plating solution (FPD AU manufactured by Technic Japan Co., Ltd.) at 80 [° C.] for 5 minutes, then washed with water and dried to form an electroless nickel-substituted gold plating layer 32. did.
[0064]
Next, a photosensitive resist having the following composition was applied to form a photosensitive resist layer having a predetermined thickness.
[0065]
Composition of photosensitive resist
-10% aqueous solution of polyvinyl alcohol: 20 parts by weight (Gosenal T-330 manufactured by Nippon Synthetic Chemical Co., Ltd.)
・ 20% aqueous solution of diazo resin… 0.8 parts by weight (D-011 manufactured by Shinko Giken Co., Ltd.)
・ Pure water: 15 parts by weight
Next, with a proximity exposure machine using an ultra-high pressure mercury lamp as an exposure light source, exposure of the photosensitive resist layer is performed at a predetermined exposure amount through a photomask having an opening corresponding to a formation pattern of the electrolytic copper plating layer 14. went. Thereafter, by developing using pure water, the photosensitive resist layer 41 from which the pattern portion of the electroconductive copper plating layer 33 is removed is formed.
[0066]
Subsequently, the transparent substrate 11 on which the partially removed photosensitive resist layer 41 is formed is immersed in an electrolytic copper plating solution (Cover Glyme CLX manufactured by Shipley Co., Ltd.), so that the transparent substrate 11 has a predetermined position on the electroless nickel-substituted gold plating layer 13. Then, an electrolytic copper plating layer 33 is laminated.
[0067]
Further, the substrate 31 on which the electrolytic copper plating layer 33 is formed is immersed in a palladium plating solution (Palladur 200 manufactured by Shipley), and the palladium plating layer 34 is laminated on the electrolytic copper plating layer 33.
[0068]
Subsequently, the photosensitive resist layer 41 is peeled off.
[0069]
Next, the electroless nickel-substituted gold plating layer 13 other than the portion corresponding to the portion where the palladium plating layer 34 is formed is etched with an etching solution (a gold stripping solution manufactured by Technic Japan Co., Ltd. and a nickel stripping solution which is a mixed acid of nitric acid: phosphoric acid = 4: 6). Immersion at 40 ° C. for 5 minutes).
[0070]
Next, the partition wall 35 is formed by the thick-film printing method so as to stand in parallel with the address electrode constituted by the electroless nickel-substituted gold plating layer 32, the electrolytic copper plating layer 33, and the palladium plating layer 15.
[3] Effects of the embodiment
FIG. 7 is an explanatory diagram of the effect of the embodiment.
In FIG. 7, the evaluation of adhesion is as follows.
：: Good adhesion
Δ: Slightly low adhesion
×: poor adhesion
That is, when palladium was used as the metal for plating (Example) and when silver was used (Comparative Example 2), good adhesion was obtained. On the other hand, when the metal was pressed and gold was used (Comparative Example 1), the adhesion was slightly low. When tin, copper or nickel was used as the metal (Comparative Examples 3 to 5), an oxide film was generated, and peeling was observed between the dielectric layer and the metal, resulting in poor adhesion. It became a state.
[0071]
In the discoloration state, no discoloration was observed when palladium was used as the metal (Example) and when silver was used (Comparative Example 2). On the other hand, when gold was used as the metal (Comparative Example 1), when the film thickness of gold was 2 μm or less, the surface of the film became slightly dark. When tin, copper or nickel was used as the metal (Comparative Examples 3 to 5), the surface of the coating was blackened and the metal surface was in an oxidized state.
[0072]
The change in the electric resistance value is a result of measurement using a line having a line width of 100 μm and a line length of 10 cm after the dielectric layer was peeled off by polishing. When palladium was used as the metal (Example), no change in the resistance value was observed. On the other hand, when silver was used as the metal (Comparative Example 2), the electric resistance decreased slightly, and when gold was used as the metal (Comparative Example 1), the electric resistance decreased. When tin, copper or nickel was used as the metal (Comparative Examples 3 to 5), the electric resistance value was significantly reduced.
[0073]
No migration was observed when palladium was used as the metal (Example) or when gold was used (Comparative Example 1). In contrast, when silver was used as the metal (Comparative Example 2), migration was observed. Further, when tin, copper or nickel was used as the metal (Comparative Examples 3 to 5), migration was not able to be evaluated in a state where the entire coating was oxidized in the depth direction.
[0074]
As described above, according to the present example, even when compared with any of Comparative Examples 1 to 5, excellent characteristics were obtained in any of adhesion, discoloration, change in electric resistance, and migration. It turned out to be obtained.
[0075]
【The invention's effect】
According to the present invention, a fine wiring pattern is formed by a so-called photolithography process, and the resistance is reduced by a plating process of applying electroless nickel-substituted gold plating, electrolytic copper plating, and palladium plating. Can be achieved at the same time.
[0076]
Further, in the front plate of the PDP electrode substrate, the palladium plating layer is not affected by oxygen in the dielectric layer and can withstand the baking temperature (for example, 540 [゜]) of the dielectric layer. The occurrence of defects can be reduced.
[0077]
Further, since a wet process is used, manufacturing costs can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a PDP electrode substrate (front plate) of an embodiment.
FIG. 2 is a schematic manufacturing process diagram (part 1) of a PDP electrode substrate (front plate) of the embodiment.
FIG. 3 is a schematic manufacturing process diagram (part 2) of the PDP electrode substrate (front plate) of the embodiment.
FIG. 4 is a schematic cross-sectional view of a PDP electrode substrate (back plate) of the embodiment.
FIG. 5 is a schematic manufacturing process diagram (part 1) of the PDP electrode substrate (back plate) of the embodiment.
FIG. 6 is a schematic manufacturing process diagram (part 2) of the PDP electrode substrate (back plate) of the embodiment.
FIG. 7 is an explanatory diagram of an effect of the embodiment.
[Explanation of symbols]
10 PDP electrode substrate (front panel)
11 Transparent substrate
12 Transparent electrode layer (transparent electrode pattern layer)
13. Electroless nickel-substituted gold plating layer (low-resistance layer)
14 Copper electroplated layer (low resistance layer)
15 Palladium plating layer
16 Dielectric layer
17 Black Stripe Layer
30 PDP electrode substrate (back plate)
31 substrate
32 Electroless nickel-substituted gold plating layer (low-resistance layer)
33 Electric copper plating layer (low resistance layer)
34 Palladium plating layer
35 partition
36 phosphor layer
36R phosphor (red)
36G phosphor (green)
36B phosphor (blue)

Claims (9)

An electrode substrate for PDP provided on the front side of PDP,
A transparent substrate,
An electrode pattern layer formed on the transparent substrate,
A low-resistance layer formed on the electrode pattern layer, for reducing a wiring resistance value of the electrode pattern layer,
A palladium plating layer formed on the low resistance layer,
A dielectric layer covering the low resistance layer and the palladium plating layer;
An electrode substrate for a PDP, comprising: The PDP electrode substrate according to claim 1,
The low resistance layer, an electroless nickel-substituted gold plating layer formed on the electrode pattern layer,
A copper plating layer formed on the electroless nickel-substituted gold plating layer,
An electrode substrate for a PDP, comprising: The electrode substrate for a PDP according to claim 1 or 2,
The electrode substrate for a PDP, wherein the electrode pattern layer is formed of ITO. An electrode substrate for PDP provided on the back side of PDP,
Board and
A low resistance layer formed on the substrate,
A palladium plating layer formed on the low resistance layer,
A partition wall provided on the substrate,
A phosphor layer formed between the partition walls so as to cover the low resistance layer and the palladium plating layer;
An electrode substrate for a PDP, comprising: The PDP electrode substrate according to claim 4,
The low resistance layer, an electroless nickel-substituted gold plating layer formed on the electrode pattern layer,
A copper plating layer formed on the electroless nickel-substituted gold plating layer,
An electrode substrate for a PDP, comprising: A method for manufacturing a PDP electrode substrate provided on the front side of a PDP,
An electrode pattern forming step of forming an electrode pattern on a transparent substrate,
Forming a first low-resistance layer on the transparent substrate and the electrode pattern layer;
Forming a resist pattern having a predetermined pattern on the first resistance-lowering layer;
Forming a second low-resistance layer at a position where the resist layer is not formed on the first low-resistance layer;
A palladium plating layer forming step of forming a palladium plating layer on the second resistance reducing layer;
A resist stripping step of stripping the resist layer,
An etching step of etching the first low-resistance layer;
A method for manufacturing a PDP electrode substrate, comprising: The method for manufacturing a PDP electrode substrate according to claim 6,
A dielectric layer forming step of forming a dielectric layer to cover the electrode pattern layer, the first low resistance layer, the second low resistance layer, and the palladium plating layer;
A black stripe forming step of forming a black stripe on the dielectric layer,
A method for manufacturing a PDP electrode substrate, comprising: The method for manufacturing a PDP electrode substrate according to claim 6 or 7,
The method of manufacturing an electrode substrate for a PDP, wherein the first low-resistance layer forming step comprises forming an electroless nickel-substituted gold plating layer on the electrode pattern by electroless plating. The method for manufacturing an electrode substrate for a PDP according to any one of claims 6 to 8,
The method for manufacturing an electrode substrate for a PDP, wherein the forming the second low-resistance layer comprises forming an electrolytic copper plating layer on the first low-resistance layer by electrolytic plating.

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