JP2004309848A - Method for manufacturing substrate, method for manufacturing substrate for electro-optic device and method for manufacturing liquid crystal device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent occurrence of an element defect by obstructing peeling of an ITO film on the outer peripheral part of a wafer substrate. <P>SOLUTION: The manufacturing method comprises a process of forming interlayer insulation films to be arranged between a plurality of deposition layers laminated on the substrate, a process (steps S3 to S5) of forming the deposition layers by an electrically conducting material on the interlayer insulation films, and a process (step S7) of coating at least the interlayer insulation films with a resist at the end surfaces of the substrate in wet etching performed after patterning of the deposition layer by the electrically conducting material. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a substrate, a method for manufacturing a substrate for an electro-optical device, and a method for manufacturing a liquid crystal device, in which a transparent electrode at an edge of a wafer substrate is hardly peeled to prevent element failure.
[0002]
[Prior art]
In general, an electro-optical device, for example, a liquid crystal device that performs a predetermined display using liquid crystal as an electro-optical material has a configuration in which liquid crystal is sandwiched between a pair of substrates. Among them, in an electro-optical device such as a liquid crystal device of an active matrix drive system using a TFT drive, a TFD drive or the like, each intersection of a number of scanning lines (gate lines) and data lines (source lines) arranged vertically and horizontally is provided. Correspondingly, a pixel electrode and a switching element are provided on a substrate (active matrix substrate).
[0003]
A switching element such as a TFT element is turned on by an ON signal supplied to a gate line, and writes an image signal supplied via a source line to a pixel electrode (transparent electrode (ITO film)). Thus, a voltage based on the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode, thereby changing the arrangement of the liquid crystal molecules. Thus, the image display is performed by changing the transmittance of the pixel and changing the light passing through the pixel electrode and the liquid crystal layer according to the image signal.
[0004]
An element substrate that constitutes such a switching element is formed by stacking a semiconductor thin film, an insulating thin film, or a conductive thin film having a predetermined pattern on a wafer substrate such as a glass or quartz substrate. That is, the TFT substrate and the like are formed by repeating the film formation process of various films and the photolithography process.
[0005]
In the resist coating step in the photolithography step, in the course of transporting the wafer substrate to the exposure device after the resist is applied, in order to prevent the resist from peeling off at the outer peripheral portion of the substrate and causing particle contamination, the resist is applied near the outer peripheral portion of the substrate. Generally, so-called edge rinsing without applying a resist using a rinsing liquid is performed. The edge rinse is disclosed in Patent Document 1.
[0006]
[Patent Document 1]
JP-A-6-124887
[0007]
[Problems to be solved by the invention]
Incidentally, the ITO film formed on the entire surface of the wafer substrate is patterned by dry etching after the photolithography process. However, in the dry etching of the liquid crystal substrate, an electrostatic chuck cannot be used to fix the wafer substrate, and the wafer substrate is fixed by a clamp attached to the outer peripheral portion due to the characteristics of the device. That is, at the time of dry etching, the ITO film on the outer peripheral portion of the substrate cannot be removed by the clamp attached to the outer peripheral portion, and the ITO film that is originally unnecessary remains on the outer peripheral portion. In addition, the sputtering apparatus for forming the ITO film on the entire surface cannot control the composition ratio at the outer peripheral portion of the substrate correctly due to a limitation in performance, and a defective ITO film which is easily peeled is formed at the outer peripheral portion of the substrate. ing.
[0008]
After the patterning of the ITO film, a terminal (PAD) for electrically connecting the liquid crystal device to an external circuit is formed. A wiring layer is formed below the ITO film with an interlayer insulating film interposed therebetween. By opening a hole in the interlayer insulating film, conduction between the wiring layer and the PAD is achieved.
[0009]
In such a PAD forming step, a resist is applied to form a mask pattern, and a part of the interlayer insulating film is removed by wet etching to form an opening. However, also in the PAD forming step, edge rinsing is performed when applying the resist. Therefore, the interlayer insulating film is exposed at the outer peripheral portion of the substrate, and the interlayer insulating film below the ITO film is partially removed.
[0010]
FIG. 11 is an explanatory diagram showing this state. In FIG. 11, a wiring layer 112 is formed on a substrate 111, and ITO films 115 and 116 are formed on the wiring layer 112 via an interlayer insulating film 113. A resist is formed on the ITO film 115 to form an opening for PAD formation. However, at the edge of the substrate, the interlayer insulating film 113 is removed by the wet etching solution, and the ITO film 116 is in a floating state.
[0011]
Then, the defective ITO film 116 formed in the vicinity of the outer peripheral portion of the wafer substrate 111 which is relatively easily peeled off is removed from the vicinity of the outer peripheral portion of the substrate in the cleaning step and adheres to the surface of the substrate 111 again. There is a problem that such a foreign substance of the ITO film 116 enters a gap between the ITO films 115 of the adjacent pixels and causes an element failure such as a short circuit.
[0012]
The present invention has been made in view of such a problem, and adopts edge rinsing and forms a resist so as to cover an interlayer insulating film on an outer peripheral portion of a wafer substrate, thereby preventing peeling of an ITO film. It is an object of the present invention to provide a method of manufacturing a substrate, a method of manufacturing a substrate for an electro-optical device, and a method of manufacturing a liquid crystal device that can prevent the occurrence of element failure.
[0013]
[Means for Solving the Problems]
In the method for manufacturing a substrate according to the present invention, a step of forming an interlayer insulating film disposed between a plurality of film layers stacked on a substrate and a step of forming a film layer of a conductive material on the interlayer insulating film And a step of coating at least the interlayer insulating film with a resist on an end face of the substrate during wet etching performed after patterning the film-forming layer with the conductive material.
[0014]
According to such a configuration, an interlayer insulating film is formed between the deposition layers stacked on the substrate. A film formation layer of a conductive material is formed on the interlayer insulating film, and the film formation layer of the conductive material is patterned. When wet etching is performed after this patterning, a resist serving as a mask for wet etching is formed so as to cover at least the interlayer insulating film on the end face of the substrate. As a result, the interlayer insulating film is not removed at the end face of the substrate during the wet etching, so that the film formed of the conductive material near the end face of the substrate does not remain in a floating state with the lower interlayer insulating film remaining reliably. Accordingly, it is possible to prevent the deposition layer of the conductive material near the substrate end face from peeling off, and it is possible to prevent an element failure due to the film peeling of the conductive material.
[0015]
In addition, the resist is extended toward the outside of the substrate by a predetermined distance from the end surface of the film formation layer made of the conductive material in the vicinity of the end surface of the substrate, so that the interlayer insulating film is formed on the end surface of the substrate. Is characterized by being coated.
[0016]
According to such a configuration, since the resist is extended toward the outside of the substrate by a predetermined distance from the end surface of the film formation layer made of the conductive material in the vicinity of the substrate end surface, the interlayer insulating film is formed on the substrate end surface. Coating can be reliably performed.
[0017]
Further, the resist is subjected to edge rinsing in the vicinity of the end face of the substrate, and has a smaller thickness than other portions.
[0018]
According to such a configuration, the resist is formed thin in the vicinity of the end face of the substrate, so that peeling of the resist can be suppressed and particle contamination can be prevented.
[0019]
Further, before the step of forming the interlayer insulating film, a step of forming a wiring layer below the interlayer insulating film, and a step of exposing the wiring layer by wet etching after the step of covering with the resist. Forming a part.
[0020]
According to such a configuration, in order to expose the wiring layer formed below the interlayer insulating film, wet etching is performed after patterning the film-forming layer with the conductive material. Even in this case, since the resist covers the interlayer insulating film on the end face of the substrate, the interlayer insulating film on the end face of the substrate is not removed, so that peeling of the film formation layer due to the conductive material can be suppressed.
[0021]
Further, the method of manufacturing a substrate for an electro-optical device according to the present invention includes: a step of forming an interlayer insulating film on a film formation layer laminated on the substrate; a step of forming a transparent electrode on the interlayer insulating film; At the time of wet etching performed after patterning of the transparent electrode, a step of coating at least the interlayer insulating film with a resist on the end face of the substrate is provided.
[0022]
According to such a configuration, the interlayer insulating film is formed on the film formation layer on the substrate, and the transparent electrode is formed on the interlayer insulating film. The transparent electrode is patterned. At the time of this patterning, the transparent electrode may remain on the edge of the substrate that is not originally needed. However, when wet etching is performed after patterning, a resist serving as a mask for wet etching is formed so as to cover at least the interlayer insulating film on the end face of the substrate. Accordingly, the interlayer insulating film is not removed from the end face of the substrate during the wet etching, so that the transparent electrode near the end face of the substrate does not float, and peeling of the transparent electrode is prevented. Accordingly, it is possible to prevent foreign substances from being attached to the substrate as foreign matter of the transparent electrode, and to prevent element failure.
[0023]
Further, the method for manufacturing an electro-optical device substrate according to the present invention includes a step of forming a wiring layer on the substrate, a step of forming an interlayer insulating film on the wiring layer, and forming a transparent electrode on the interlayer insulating film. Forming, and after patterning the transparent electrode, forming a resist so as to cover at least the interlayer insulating film at the end face of the substrate, and performing wet etching using the resist as a mask pattern to form the wiring. Forming an opening for exposing the layer.
[0024]
According to such a configuration, the wiring layer is formed on the substrate, and the transparent electrode is formed on the wiring layer via the interlayer insulating film. After patterning the transparent electrode, a resist is formed on the end face of the substrate so as to cover at least the interlayer insulating film. Next, wet etching is performed using the resist as a mask pattern to form an opening exposing the wiring layer. In this wet etching, the interlayer insulating film is not removed, and peeling of the transparent electrode is prevented.
[0025]
A method for manufacturing a liquid crystal device according to the present invention is characterized in that a liquid crystal device is manufactured using a substrate for a liquid crystal device manufactured by the method for manufacturing a substrate or the method for manufacturing a substrate for an electro-optical device.
[0026]
According to such a configuration, occurrence of element failure in the liquid crystal device substrate is prevented, and a high-quality liquid crystal device can be manufactured.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a flowchart showing a method for manufacturing a substrate according to the first embodiment of the present invention. This embodiment is applied to the manufacture of a substrate for a liquid crystal device, which is a substrate for an electro-optical device. FIG. 2 is a plan view of the liquid crystal device formed using the electro-optical device substrate manufactured in the present embodiment, together with the components formed thereon, as viewed from the counter substrate side. FIG. 3 is a cross-sectional view showing the liquid crystal device after the assembly step of bonding the liquid crystal by bonding the element substrate and the counter substrate together and cutting the liquid crystal device along the line HH ′ in FIG. FIG. 4 is an equivalent circuit diagram of various elements, wiring, and the like in a plurality of pixels constituting a pixel region of the liquid crystal device shown in FIGS. FIG. 5 is a sectional view showing the pixel structure of the liquid crystal device shown in FIGS. 2 and 3 in detail. FIG. 6 is a process chart showing a method of forming the ITO film and the PAD in a sectional view in the order of steps. FIG. 7 is an explanatory view showing a wafer substrate at the time of manufacturing an array, and FIG. 8 is an explanatory view for explaining an ITO film forming step and an etching step. FIG. 9 is a flowchart showing a method of manufacturing a substrate for a liquid crystal device, and FIG. 10 is a table showing an effective resist formation range. In each of the above drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.
[0028]
In the present embodiment, the resist at the time of forming the PAD is formed so as to cover the interlayer insulating film on the outer peripheral portion of the wafer substrate while performing a certain degree of edge rinsing, thereby preventing the contamination of the resist with particles and the ITO. The interlayer insulating film immediately below the film is prevented from being removed, and peeling of the ITO film near the outer peripheral portion of the wafer substrate is prevented.
[0029]
First, an overall configuration of a liquid crystal device formed using a liquid crystal device substrate which is a substrate for an electro-optical device manufactured in the present embodiment will be described with reference to FIGS.
As shown in FIGS. 2 and 3, the liquid crystal device includes, for example, a TFT substrate 10 made of a quartz substrate, a glass substrate, and a silicon substrate, and an opposing substrate 20 made of, for example, a glass substrate or a quartz substrate. A liquid crystal 50 is sealed between the two. On the TFT substrate 10, pixel electrodes (ITO films) 9a and the like constituting pixels are arranged in a matrix. A counter electrode (ITO film) 21 is provided on the entire surface of the counter substrate 20. FIG. 4 shows an equivalent circuit of an element on the TFT substrate 10 constituting a pixel.
[0030]
As shown in FIG. 4, in the pixel region, a plurality of scanning lines 11a and a plurality of data lines 6a are wired so as to intersect with each other, and a pixel electrode is formed in a region defined by the scanning lines 11a and the data lines 6a. (ITO films) 9a are arranged in a matrix. Then, a TFT 30 is provided at each intersection of the scanning line 11a and the data line 6a, and the pixel electrode 9a is connected to the TFT 30.
[0031]
The TFT 30 is turned on by the ON signal of the scanning line 11a, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50. In addition, a storage capacitor 70 is provided in parallel with the pixel electrode 9a, and the storage capacitor 70 allows the voltage of the pixel electrode 9a to be held for a time that is, for example, three digits longer than the time during which the source voltage is applied. The storage capacitor 70 improves voltage holding characteristics and enables image display with a high contrast ratio.
[0032]
FIG. 5 is a schematic sectional view of a liquid crystal device focusing on one pixel.
[0033]
A plurality of pixel electrodes 9a are provided in a matrix on the TFT substrate 10, and data lines 6a and scanning lines 11a are provided along respective vertical and horizontal boundaries of the pixel electrodes 9a. The data line 6a has a laminated structure including an aluminum film and the like as described later, and the scanning line 11a is formed of, for example, a conductive polysilicon film. The scanning line 11a is electrically connected to the gate electrode 3a of the semiconductor layer 1a facing the channel region 1a '. That is, the gate electrode 3a connected to the scanning line 11a and the channel region 1a 'are opposed to each other where the scanning line 11a intersects with the data line 6a, thereby forming a pixel switching TFT 30.
[0034]
On the TFT substrate 10, in addition to the TFT 30 and the pixel electrode 9a, various configurations including these are provided in a laminated structure. As shown in FIG. 5, this laminated structure includes, in order from the bottom, a first layer (film formation layer) including the scanning line 11a, a second layer including the TFT 30 including the gate electrode 3a, and a third layer including the storage capacitor 70. A fourth layer including the data line 6a, a fifth layer including the shield layer 400, and a sixth layer (uppermost layer) including the pixel electrode 9a and the alignment film 16 and the like. A base insulating film 12 is provided between the first and second layers, a first interlayer insulating film 41 is provided between the second and third layers, and a second interlayer insulating film 42 is provided between the third and fourth layers. , A third interlayer insulating film 43 is provided between the fourth and fifth layers, and a fourth interlayer insulating film 44 is provided between the fifth and sixth layers, respectively. Has been prevented. In addition, the various insulating films 12, 41, 42, 43, and 44 are also provided with, for example, contact holes for electrically connecting the high-concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. Has been. Hereinafter, each of these elements will be described in order from the bottom.
[0035]
The first layer includes, for example, a simple metal or an alloy including at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). A scanning line 11a made of metal silicide, polysilicide, a laminate thereof, or conductive polysilicon is provided. The scanning lines 11a are patterned in a stripe shape when viewed in plan. More specifically, the stripe-shaped scanning line 11a includes a main line extending in the horizontal direction and a protrusion extending in the vertical direction in which the data line 6a or the shield layer 400 extends. The protruding portions extending from the adjacent scanning lines 11a are not connected to each other, and therefore, the scanning lines 11a are separated one by one.
[0036]
Thus, the scanning line 11a has a function of simultaneously controlling ON / OFF of the TFTs 30 existing in the same row. Further, since the scanning line 11a is formed so as to substantially fill a region where the pixel electrode 9a is not formed, the scanning line 11a also has a function of blocking light from entering the TFT 30 from below. This suppresses the occurrence of light leakage current in the semiconductor layer 1a of the TFT 30, and enables high-quality image display without flicker or the like.
[0037]
The TFT 30 including the gate electrode 3a is provided in the second layer. As shown in FIG. 5, the TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a gate electrode 3a as described above, for example, a polysilicon film, and a channel formed by an electric field from the gate electrode 3a. A channel region 1a ′ of the semiconductor layer 1a to be formed, an insulating film 2 including a gate insulating film for insulating the gate electrode 3a from the semiconductor layer 1a, a low-concentration source region 1b and a low-concentration drain region 1c in the semiconductor layer 1a, and a high-concentration region A source region 1d and a high-concentration drain region 1e are provided.
[0038]
Then, a relay electrode 719 is formed on the second layer as the same film as the gate electrode 3a. The relay electrode 719 is formed in an island shape so as to be located substantially at the center of one side of each pixel electrode 9a when viewed in plan. Since the relay electrode 719 and the gate electrode 3a are formed as the same film, when the latter is made of, for example, a conductive polysilicon film, the former is also made of a conductive polysilicon film.
[0039]
The above-described TFT 30 preferably has an LDD structure as shown in FIG. 5, but may have an offset structure in which impurities are not implanted in the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT in which impurities are implanted at a high concentration as a mask to form a high-concentration source region and a high-concentration drain region in a self-aligned manner may be used. Further, in the present embodiment, a single gate structure in which only one gate electrode of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e has been described. Electrodes may be arranged. When a TFT is formed with a dual gate or triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced. Further, the semiconductor layer 1a constituting the TFT 30 may be a non-single-crystal layer or a single-crystal layer. For forming the single crystal layer, a known method such as a bonding method can be used. By using the semiconductor layer 1a as a single crystal layer, the performance of peripheral circuits in particular can be improved.
[0040]
Above the scanning line 11a and below the TFT 30, the underlying insulating film 12 made of, for example, a silicon oxide film is provided. The base insulating film 12 has a function of interlayer insulating the TFT 30 from the scanning line 11a, and is formed on the entire surface of the TFT substrate 10 so that pixel switching due to roughness at the time of polishing the surface of the TFT substrate 10 and dirt remaining after washing is performed. A function of preventing a change in characteristics of the TFT 30 for use.
[0041]
In the base insulating film 12, grooves (contact holes) 12cv having the same width as the channel length of the semiconductor layer 1a extending along the data lines 6a to be described later are dug on both sides of the semiconductor layer 1a in plan view. Corresponding to the groove 12cv, the gate electrode 3a stacked thereabove includes a portion formed in a concave shape on the lower side. Further, since the gate electrode 3a is formed so as to fill the entire groove 12cv, a side wall 3b integrally formed with the gate electrode 3a is extended. I have. Thus, the semiconductor layer 1a of the TFT 30 is covered from the side as viewed in plan, and at least the incidence of light from this portion is suppressed.
[0042]
The side wall 3b is formed so as to fill the groove 12cv, and the lower end thereof is in contact with the scanning line 11a. Here, since the scanning line 11a is formed in a stripe shape as described above, the gate electrode 3a and the scanning line 11a existing in a certain row always have the same potential as long as the row is focused.
[0043]
Note that a structure in which another scanning line including the gate electrode 3a is formed so as to be parallel to the scanning line 11a may be employed. In this case, the scanning line 11a and the another scanning line have a redundant wiring structure. Thereby, for example, even when a part of the scanning line 11a has some defect and normal energization becomes impossible, another scanning line existing in the same row as the scanning line 11a is not used. As long as it is sound, the operation control of the TFT 30 can still be performed normally through it.
[0044]
The storage capacitor 70 is provided in the third layer. The storage capacitor 70 includes a lower electrode 71 serving as a pixel potential-side capacitor electrode connected to the high-concentration drain region 1 e and the pixel electrode 9 a of the TFT 30, and a capacitor electrode 300 serving as a fixed-potential-side capacitor electrode. It is formed by being arranged to face through. According to the storage capacitor 70, the potential holding characteristic of the pixel electrode 9a can be significantly improved. In addition, since the storage capacitor 70 is formed so as not to reach the light transmission region substantially corresponding to the formation region of the pixel electrode 9a (in other words, it is formed so as to fit within the light shielding region). The pixel aperture ratio of the entire electro-optical device is maintained relatively large, so that a brighter image can be displayed.
[0045]
More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitance electrode. However, the lower electrode 71 may be formed of a single-layer film or a multilayer film containing a metal or an alloy. The lower electrode 71 has a function of relay connection between the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30, in addition to a function as a pixel potential side capacitor electrode. This relay connection is performed via the relay electrode 719 as described later.
[0046]
The capacitance electrode 300 functions as a fixed potential side capacitance electrode of the storage capacitor 70. In order to set the capacitor electrode 300 to a fixed potential, the capacitor electrode 300 is electrically connected to the shield layer 400 set to the fixed potential.
[0047]
The capacitor electrode 300 is formed in an island shape on the TFT substrate 10 so as to correspond to each pixel, and the lower electrode 71 is formed to have substantially the same shape as the capacitor electrode 300. . As a result, the storage capacitor 70 does not have a wasteful spread in a plan view, that is, does not lower the pixel aperture ratio, and can realize the maximum capacitance value under the circumstances. That is, the storage capacitor 70 has a smaller area and a larger capacitance value.
[0048]
As shown in FIG. 5, the dielectric film 75 is, for example, a silicon oxide film such as a relatively thin HTO (High-Teleperture oxide) film having a film thickness of about 5 to 200 nm, an LTO (Low Telerature oxide) film, or a silicon nitride film. Consists of From the viewpoint of increasing the storage capacitance 70, the thinner the dielectric film 75 is, the better the reliability of the film can be obtained. The dielectric film 75 has a two-layer structure including a silicon oxide film 75a as a lower layer and a silicon nitride film 75b as an upper layer, as shown in FIG. The presence of the silicon nitride film 75b having a relatively large dielectric constant allows the capacitance value of the storage capacitor 70 to be increased, and the presence of the silicon oxide film 75a lowers the withstand voltage of the storage capacitor 70. I won't let you go. Thus, by forming the dielectric film 75 in a two-layer structure, it is possible to enjoy two opposing effects.
[0049]
Further, the presence of the silicon nitride film 75b makes it possible to prevent water from entering the TFT 30 before it occurs. Accordingly, the operation of the device can be performed for a relatively long time without causing a situation in which the threshold voltage of the TFT 30 increases. In this embodiment, the dielectric film 75 has a two-layer structure. However, the dielectric film 75 has a three-layer structure such as a silicon oxide film, a silicon nitride film, and a silicon oxide film, or more. May be configured to have a laminated structure.
[0050]
Above the TFT 30 or the gate electrode 3a and the relay electrode 719 described above and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG ( A silicate glass film such as boron phosphorus silicate glass, a silicon nitride film, a silicon oxide film, or the like, or a first interlayer insulating film 41 preferably made of NSG is formed. In the first interlayer insulating film 41, a contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and a data line 6a described later is opened while penetrating a second interlayer insulating film 42 described later. There is a hole. In the first interlayer insulating film 41, a contact hole 83 for electrically connecting the high-concentration drain region 1e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70 is formed.
[0051]
Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . In addition, in the first interlayer insulating film 41, a contact hole 882 for electrically connecting the relay electrode 719 and a second relay electrode 6a2 described later is opened while penetrating the second interlayer insulating film described later. ing.
[0052]
As shown in FIG. 5, the contact hole 882 is formed in a region other than the storage capacitor 70, and the lower electrode 71 is drawn out to the upper layer via the contact hole 882 by bypassing the lower layer relay electrode 719 once. Therefore, even when the lower electrode 71 is connected to the upper pixel electrode 9a, it is not necessary to form the lower electrode 71 wider than the dielectric film 75 and the capacitor electrode 300. Therefore, the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be simultaneously patterned in one etching process. This facilitates control of the etching rate of each of the lower electrode 71, the dielectric film 75, and the capacitor electrode 300, and can increase the degree of freedom in designing the thickness and the like.
[0053]
Further, since the dielectric film 75 is formed in the same shape as the lower electrode 71 and the capacitor electrode 300 and has no spread, when the semiconductor layer 1a of the TFT 30 is subjected to hydrogenation processing, hydrogen used for the processing is used. Can easily reach the semiconductor layer 1a through the opening around the storage capacitor 70.
[0054]
The first interlayer insulating film 41 may be baked at about 1000 ° C. to activate the ions implanted in the polysilicon film forming the semiconductor layer 1a and the gate electrode 3a.
[0055]
The fourth layer is provided with a data line 6a. The data line 6a is formed in a stripe shape in the vertical direction so as to coincide with the direction in which the semiconductor layer 1a of the TFT 30 extends. As shown in FIG. 5, the data lines 6a are, in order from the lower layer, a layer made of aluminum (reference numeral 41A in FIG. 5), a layer made of titanium nitride (see reference numeral 41TN in FIG. 5), and a layer made of silicon nitride film (see FIG. 5). It is formed as a film having a three-layer structure denoted by reference numeral 401) in FIG. The silicon nitride film is patterned to have a slightly larger size so as to cover the underlying aluminum layer and titanium nitride layer. Since the data line 6a contains aluminum, which is a relatively low-resistance material, supply of image signals to the TFT 30 and the pixel electrode 9a can be realized without interruption. On the other hand, by forming a silicon nitride film having a relatively excellent effect of damping intrusion of moisture on the data line 6a, the moisture resistance of the TFT 30 can be improved, and the life of the TFT 30 can be prolonged. The silicon nitride film is preferably a plasma silicon nitride film.
[0056]
In the fourth layer, a relay layer 6a1 for a shield layer and a second relay electrode 6a2 are formed as the same film as the data line 6a. These are not formed so as to have a planar shape continuous with the data line 6a when viewed in a plan view, but are formed so as to be separated from each other in patterning. In other words, when focusing on the data line 6a, the relay layer 6a1 has a substantially quadrangular shape immediately to the right of the data line 6a, and has a substantially quadrilateral shape slightly larger than the relay layer 6a1 to the right of the shield layer. The second relay electrode 6a2 is formed. The shield layer relay layer 6a1 and the second relay electrode 6a2 are formed in the same process as the data line 6a, and have a three-layer structure of a layer made of aluminum, a layer made of titanium nitride, and a layer made of a plasma nitride film in order from the lower layer. It is formed as. The plasma nitride film is patterned to have a slightly larger size so as to cover the underlying aluminum layer and titanium nitride layer. The titanium nitride layer functions as a barrier metal for preventing penetration of etching of the contact holes 803 and 804 formed with respect to the shield layer relay layer 6a1 and the second relay electrode 6a2. In addition, by forming a plasma nitride film having a relatively excellent effect of blocking the intrusion of moisture on the relay layer 6a1 for the shield layer and the second relay electrode 6a2, it is possible to improve the moisture resistance of the TFT 30. A longer life can be achieved. Incidentally, a plasma silicon nitride film is desirable as the plasma nitride film.
[0057]
Above the storage capacitor 70 and below the data line 6a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably, a plasma CVD method using TEOS gas The second interlayer insulating film 42 is formed. In the second interlayer insulating film 42, a contact hole 81 for electrically connecting the high concentration source region 1d of the TFT 30 and the data line 6a is opened, and the shield layer relay layer 6a1 and the storage capacitor 70 are formed. A contact hole 801 for electrically connecting the capacitor electrode 300 serving as the upper electrode is formed. Further, a contact hole 882 for electrically connecting the second relay electrode 6a2 and the relay electrode 719 is formed in the second interlayer insulating film.
[0058]
The shield layer 400 is formed on the fifth layer. The shield layer 400 is formed in a lattice shape so as to extend in the horizontal and vertical directions when viewed in plan. Particularly, a portion of the shield layer 400 extending in the vertical direction is formed so as to cover the data line 6a and to be wider than the data line 6a. In addition, a portion extending in the horizontal direction has a cutout near the center of one side of each pixel electrode 9a in order to secure a region for forming a third relay electrode 402 described later.
[0059]
Further, at the corners of the intersections of the shield layers 400 extending in the horizontal and vertical directions, substantially triangular portions are provided so as to fill the corners. By providing the substantially triangular portion in the shield layer 400, light can be effectively shielded from the semiconductor layer 1a of the TFT 30. That is, light that is about to enter the semiconductor layer 1a obliquely from above is reflected or absorbed by this triangular portion, and does not reach the semiconductor layer 1a. Therefore, it is possible to suppress the occurrence of light leakage current and display a high-quality image without flicker or the like.
[0060]
The shield layer 400 extends from the image display area 10a in which the pixel electrode 9a is arranged to the periphery thereof, and is electrically connected to a constant potential source to have a fixed potential. Note that the constant potential source may be a constant potential source of a positive power supply or a negative power supply supplied to the data line driving circuit 101 described later, or a constant potential source supplied to the counter electrode 21 of the counter substrate 20.
[0061]
As described above, the presence of the shield layer 400 which is formed so as to cover the entire data line 6a and has a fixed potential reduces the influence of capacitive coupling generated between the data line 6a and the pixel electrode 9a. It can be eliminated. That is, it is possible to avoid a situation in which the potential of the pixel electrode 9a fluctuates in accordance with the energization of the data line 6a, which may cause display unevenness or the like along the data line 6a on an image. Can be reduced. Since the shield layer 400 is formed in a lattice shape, it is possible to suppress unnecessary capacitive coupling even at a portion where the scanning line 11a extends, without causing unnecessary capacitive coupling.
[0062]
In the fourth layer, a third relay electrode 402 as a relay layer is formed as the same film as the shield layer 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a via a contact hole 89 described later. The shield layer 400 and the third relay electrode 402 are not formed continuously in a planar shape, but are formed so as to be separated on patterning.
[0063]
On the other hand, the above-mentioned shield layer 400 and third relay electrode 402 have a two-layer structure of a lower layer made of aluminum and an upper layer made of titanium nitride. In the third relay electrode 402, the lower layer made of aluminum is connected to the second relay electrode 6a2, and the upper layer made of titanium nitride is connected to the pixel electrode 9a made of an ITO film or the like. ing. When aluminum and the ITO film are directly connected, electric corrosion occurs between the two, and a favorable electrical connection cannot be realized due to disconnection of aluminum or insulation due to formation of alumina. On the other hand, since the titanium nitride and the ITO film are connected, the contact resistance is low and good connectivity is obtained.
[0064]
As described above, since the electrical connection between the third relay electrode 402 and the pixel electrode 9a can be satisfactorily realized, the voltage application to the pixel electrode 9a or the potential holding characteristic of the pixel electrode 9a is maintained satisfactorily. It becomes possible.
[0065]
Further, since the shield layer 400 and the third relay electrode 402 include aluminum having relatively excellent light reflection performance and titanium nitride having relatively excellent light absorption performance, they can function as a light shielding layer. That is, according to these, it is possible to block the progress of the incident light (see FIG. 5) on the semiconductor layer 1a of the TFT 30 on the upper side. Note that such a light shielding function can be similarly applied to the above-described capacitance electrode 300 and data line 6a. The shield layer 400, the third relay electrode 402, the capacitor electrode 300, and the data line 6a form a part of a laminated structure built on the TFT substrate 10 and serve as an upper light-shielding film that blocks light from entering the TFT 30 from above. Function.
[0066]
Above the data line 6a and below the shield layer 400, a silicate glass film such as NSG, PSG, BSG, BPSG, etc., a silicon nitride film, a silicon oxide film, or the like, or preferably, a plasma CVD method using TEOS gas The third interlayer insulating film 43 is formed. In the third interlayer insulating film 43, a contact hole 803 for electrically connecting the shield layer 400 and the relay layer 6a1 for the shield layer, and a third relay electrode 402 and the second relay electrode 6a2 are electrically connected. The contact holes 804 for connecting to each other are opened.
[0067]
The second interlayer insulating film 42 may not be subjected to the above-described baking with respect to the first interlayer insulating film 41, so that the stress generated near the interface of the capacitor electrode 300 may be reduced.
[0068]
As described above, the pixel electrodes 9a are formed in a matrix on the sixth layer, and the alignment film 16 is formed on the pixel electrodes 9a. Under the pixel electrode 9a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably, a plasma film formed by a plasma CVD method using a TEOS gas. A fourth interlayer insulating film 44 made of TEOS is formed. A contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is formed in the fourth interlayer insulating film 44.
[0069]
The surfaces of the third and fourth interlayer insulating films 43 and 44 are flattened by a CMP (Chemical Mechanical Polishing) process or the like. Poor alignment of the liquid crystal layer 50 due to steps due to various wirings, elements, etc. existing below the planarized interlayer insulating films 43, 44 is reduced. However, instead of or in addition to performing the planarization process on the third and fourth interlayer insulating films 43 and 44 in this manner, the TFT substrate 10, the base insulating film 12, the first interlayer insulating film 41, and the second interlayer insulating film 41 A flattening process may be performed by digging a groove in at least one of the insulating film 42 and the third interlayer insulating film 43 and burying the wiring such as the data line 6a or the TFT 30 or the like.
[0070]
Further, the storage capacitor 70 has a three-layer structure of a pixel potential side capacitance electrode, a dielectric film, and a fixed potential side capacitance electrode in order from the bottom, but may have a structure opposite thereto. .
[0071]
As shown in FIGS. 2 and 3, the opposing substrate 20 is provided with a light-shielding film 53 as a frame for dividing a display area. A transparent conductive film such as an ITO film is formed on the entire surface of the counter substrate 20 as the counter electrode 21, and a polyimide alignment film 22 is formed on the entire surface of the counter electrode 21. The alignment film 22 is rubbed in a predetermined direction so as to give a predetermined pretilt angle to the liquid crystal molecules.
[0072]
In a region outside the light-shielding film 53, a sealing material 52 for enclosing liquid crystal is formed between the TFT substrate 10 and the counter substrate 20. The sealing material 52 is disposed so as to substantially match the contour shape of the counter substrate 20, and fixes the TFT substrate 10 and the counter substrate 20 to each other. The sealing material 52 is missing at a part of one side of the TFT substrate 10, and a liquid crystal injection port 108 for injecting the liquid crystal 50 is formed in a gap between the bonded TFT substrate 10 and the counter substrate 20. You. After the liquid crystal is injected from the liquid crystal injection port 108, the liquid crystal injection port 108 is sealed with a sealing material 109.
[0073]
A data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external connection terminal 102 for connection to an external circuit are provided in a region outside the sealing material 52. Are provided along one side of the TFT substrate 10. Along the two sides adjacent to the one side, a scanning line driving circuit 104 for driving the gate electrode 3a by supplying a scanning signal to the scanning line 11a and the gate electrode 3a at a predetermined timing is provided. The scanning line driving circuit 104 is formed on the TFT substrate 10 at a position facing the light shielding film 53 inside the sealing material 52. Further, on the TFT substrate 10, a wiring 105 for connecting the data line driving circuit 101, the scanning line driving circuit 104, the external connection terminal 102, and the upper / lower conduction terminal 107 is provided facing three sides of the light shielding film 53. I have.
[0074]
The upper and lower conductive terminals 107 are formed on the four TFT substrates 10 at the corners of the sealing material 52. A vertical conductive material 106 is provided between the TFT substrate 10 and the counter substrate 20, the lower end of which contacts the upper and lower conductive terminals 107 and the upper end of which contacts the counter electrode 21. Electrical continuity is established between 10 and counter substrate 20.
[0075]
The present invention is not limited to the three-dimensional and two-dimensional layout of each component, but may be various other forms.
[0076]
Next, a method for manufacturing an electro-optical device substrate according to the present embodiment will be described with reference to the explanatory diagrams of FIGS. 6 to 8 and the flowchart of FIG. In this embodiment, an example will be described in which an array manufacturing method is adopted and a plurality of TFT substrates (active matrix substrates) are cut out from one mother glass substrate. That is, a plurality of TFT substrates 10 shown in FIGS. 2 and 3 are simultaneously formed on the mother glass substrate by repeating the film formation and the photolithography process while keeping the size of the mother glass substrate.
[0077]
First, in step S31 of FIG. 9, a wafer substrate 131 (TFT substrate 10) (see FIG. 7) such as a quartz substrate, glass, or silicon substrate is prepared. Here, annealing is preferably performed at a high temperature of about 900 to 1300 ° C. in an inert gas atmosphere such as N (nitrogen), and pre-processing is performed so that distortion generated in the wafer substrate 131 in a high-temperature process performed later is reduced. Keep it.
[0078]
Next, a metal alloy film such as a metal such as Ti, Cr, W, Ta, or Mo, or a metal silicide is formed on the entire surface of the wafer substrate 131 thus processed by sputtering to a thickness of about 100 to 500 nm, preferably. Is deposited to a thickness of 200 nm. Hereinafter, such a film before patterning is referred to as a precursor film. Then, the precursor film of the metal alloy film is patterned by photolithography and etching to form a scanning line 11a having a planar shape of a stripe (step S32).
[0079]
Next, a TEOS (tetra-ethyl-ortho-silicate) gas, a TEB (tetra-ethyl-borate) gas, and a TMOP (tetra-methyl-oxy) gas are formed on the scanning line 11a by, for example, normal pressure or reduced pressure CVD. A silicate glass film such as NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorous silicate glass), a silicon nitride film or a silicon oxide film using a foslate) gas or the like. The underlying insulating film 12 made of the above is formed (Step S33). The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.
[0080]
In the next step S34, semiconductor layer 1a is formed. The precursor film of the semiconductor layer 1a is formed on the base insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C., under reduced pressure using monosilane gas, disilane gas, or the like at a flow rate of about 400 to 600 cc / min. An amorphous silicon film formed by CVD (for example, CVD at a pressure of about 20 to 40 Pa). Next, a p-Si (polysilicon) film having a thickness of about 50 to 200 nm is formed by performing a heat treatment in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably for 4 to 6 hours. , Preferably solid phase growth to a thickness of about 100 nm. As a method for solid phase growth, annealing using RTA or laser annealing using an excimer laser or the like may be used. At this time, depending on whether the pixel switching TFT 30 is an n-channel type or a p-channel type, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like. Then, a semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.
[0081]
Next, in step S35, the semiconductor layer 1a forming the TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C. to form a lower gate insulating film. Subsequently, an upper gate insulating film is formed by a low-pressure CVD method or the like, thereby forming an insulating film 2 (including a gate insulating film) made of a single or multilayer high-temperature silicon oxide film (HTO film) or a silicon nitride film. . As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30 to 100 nm. It will be thick.
[0082]
Next, in order to control the threshold voltage Vth of the pixel switching TFT 30, a predetermined amount of a dopant such as boron is doped into the n-channel region or the p-channel region of the semiconductor layer 1a by ion implantation or the like. I do.
[0083]
Next, a groove 12cv communicating with the scanning line 11a is formed in the base insulating film 12. The groove 12cv is formed by dry etching such as reactive ion etching and reactive ion beam etching.
[0084]
Next, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to make the polysilicon film conductive. Instead of the thermal diffusion, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of the polysilicon film is about 100 to 500 nm, preferably about 350 nm. Then, a gate electrode 3a having a predetermined pattern including the gate electrode portion of the TFT 30 is formed by photolithography and etching (step S36). When the gate electrode 3a is formed, the side wall 3b extending therefrom is also formed at the same time. The side wall 3b is formed by depositing the above-described polysilicon film also on the inside of the trench 12cv. At this time, since the bottom of the groove 12cv is in contact with the scanning line 11a, the side wall 3b and the scanning line 11a are electrically connected. Further, when patterning the gate electrode 3a, a relay electrode 719 is also formed at the same time.
[0085]
Next, a low-concentration source region 1b and a low-concentration drain region 1c, and a high-concentration source region 1d and a high-concentration drain region 1e are formed on the semiconductor layer 1a.
[0086]
Here, a case where the TFT 30 is an n-channel TFT having an LDD structure will be described. Specifically, first, in order to form the low-concentration source region 1b and the low-concentration drain region 1c, the gate electrode 3a is used as a mask. Dopan of a group V element such as P at a low concentration (for example, P ions ^Thirteen cm ₂ Doping). Thus, the semiconductor layer 1a below the gate electrode 3a becomes a channel region 1a '. At this time, the low concentration source region 1b and the low concentration drain region 1c are formed in a self-aligned manner by the gate electrode 3a serving as a mask. Next, a resist layer having a plane pattern wider than the gate electrode 3a is formed on the gate electrode 3a in order to form the high-concentration source region 1d and the high-concentration drain region 1e. Thereafter, a dopant of a group V element such as P is doped at a high concentration (for example, P ions ^Fifteen / Cm ₂ Doping).
[0087]
Note that doping may not be performed in two stages of low concentration and high concentration. For example, a TFT having an offset structure may be used without performing low-concentration doping, and a self-aligned TFT may be formed using a gate electrode 3a (gate electrode) as a mask and an ion implantation technique using P ions, B ions, or the like. Good. The resistance of the gate electrode 3a is further reduced by the doping of the impurity.
[0088]
Next, a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, or an oxide is formed on the gate electrode 3a by, for example, normal pressure or reduced pressure CVD using TEOS gas, TEB gas, TMOP gas, or the like. A first interlayer insulating film 41 made of a silicon film is formed (Step S37). The thickness of the first interlayer insulating film 41 is, for example, about 500 to 2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the first interlayer insulating film 41.
[0089]
Next, in step S38, the contact holes 83 and 881 are formed by dry etching such as reactive ion etching and reactive ion beam etching on the first interlayer insulating film 41. At this time, the former is formed so as to communicate with the high-concentration drain region 1e of the semiconductor layer 1a, and the latter is formed so as to communicate with the relay electrode 719.
[0090]
Next, in step S39, a metal film such as Pt or a polysilicon film is formed to a thickness of about 100 to 500 nm on the first interlayer insulating film 41 by low pressure CVD or sputtering, and a predetermined pattern is formed. A precursor film for the lower electrode 71 is formed. In this case, the formation of the metal film is performed so that both the contact hole 83 and the contact hole 881 are buried, so that the high-concentration drain region 1e, the relay electrode 719, and the lower electrode 71 are electrically connected. Can be
[0091]
Next, a precursor film of the dielectric film 75 is formed on the lower electrode 71. This dielectric film 75 can be formed by various known techniques generally used for forming a TFT gate insulating film, similarly to the case of the insulating film 2. The silicon oxide film 75a is formed by the above-described thermal oxidation or the CVD method, and thereafter, the silicon nitride film 75b is formed by the low pressure CVD method or the like. As the dielectric film 75 becomes thinner, the storage capacitance 70 becomes larger. Therefore, it is advantageous to form the dielectric film 75 into a very thin insulating film having a thickness of 50 nm or less on condition that defects such as film breakage do not occur. It is. Next, a metal film such as a polysilicon film or AL (aluminum) is formed on the dielectric film 75 to a thickness of about 100 to 500 nm by low-pressure CVD or sputtering to form a precursor film for the capacitor electrode 300. To form
[0092]
Next, the lower electrode 71, the dielectric film 75, and the precursor film of the capacitor electrode 300 are patterned at a time to form the lower electrode 71, the dielectric film 75, and the capacitor electrode 300, thereby completing the storage capacitor.
[0093]
Next, for example, a silicate glass film of NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, a silicon oxide film, or the like is formed by normal pressure or reduced pressure CVD using TEOS gas or the like, preferably by plasma CVD. The two-layer insulating film 42 is formed (Step S40). When aluminum is used for the capacitor electrode 300, it is necessary to form a film at a low temperature by plasma CVD. The thickness of the second interlayer insulating film 42 is, for example, about 500 to 1500 nm. Next, in step S41, contact holes 81, 801 and 882 are formed by dry etching such as reactive ion etching and reactive ion beam etching on the second interlayer insulating film. At this time, the contact hole 81 is formed so as to communicate with the high-concentration source region 1d of the semiconductor layer 1a, the contact hole 801 is formed so as to communicate with the capacitor electrode 300, and the contact hole 882 is formed so as to communicate with the relay electrode 719. You.
[0094]
Next, in step S42, a low-resistance metal such as aluminum or a metal silicide having a light-shielding property or a metal silicide is used as a metal film over the entire surface of the second interlayer insulating film 42 by sputtering or the like, preferably in a thickness of about 100 to 500 nm. Deposits at about 300 nm. Then, a data line 6a having a predetermined pattern is formed by photolithography and etching. At this time, at the time of the patterning, the shield layer relay layer 6a1 and the second relay layer 6a2 are also formed at the same time. The relay layer 6a1 for the shield layer is formed so as to cover the contact hole 801 and the second relay layer 6a2 is formed so as to cover the contact hole 882.
[0095]
Next, after a film made of titanium nitride is formed on the entire upper layer by a plasma CVD method or the like, a patterning process is performed so that this film remains only on the data line 6a. However, the layer made of titanium nitride may be formed so as to remain also on the relay layer 6a1 for the shield layer and the second relay layer 6a2, or may be formed so as to remain on the entire surface of the wafer substrate 131 in some cases. Is also good. Alternatively, a film may be formed at the same time as the aluminum film is formed, and may be etched at a time.
[0096]
Next, a silicate such as NSG, PSG, BSG, BPSG, or the like is formed so as to cover the data line 6a or the like by a normal pressure or reduced pressure CVD method using TEOS gas or the like, preferably by a plasma CVD method capable of forming a film at a low temperature. A third interlayer insulating film 43 made of a glass film, a silicon nitride film, a silicon oxide film, or the like is formed (Step S43). The thickness of the third interlayer insulating film 43 is, for example, about 500 to 3500 nm.
[0097]
Next, in step S44, as shown in FIG. 5, the third interlayer insulating film 43 is planarized using, for example, CMP.
[0098]
Next, in step S45, contact holes 803 and 804 are formed by dry etching such as reactive ion etching and reactive ion beam etching on the third interlayer insulating film 43. At this time, the contact hole 803 is formed so as to communicate with the relay layer 6a1 for the shield layer, and the contact hole 804 is formed so as to communicate with the second relay layer 6a2.
[0099]
Next, in step S46, the shield layer 400 is formed on the third interlayer insulating film 43 by a sputtering method, a plasma CVD method, or the like. Here, first, a lower layer film is formed from a low-resistance material such as aluminum directly above the third interlayer insulating film 43, and then a pixel electrode 9a described later such as titanium nitride is formed on the lower layer film. An upper layer film is formed from an ITO film to be formed and a material that does not cause electrolytic corrosion, and finally, the lower layer film and the upper layer film are both patterned to form a shield layer 400 having a two-layer structure. At this time, the third relay electrode 402 is also formed together with the shield layer 400.
[0100]
In addition, as described later, in the same film formation process as that for the shield layer 400, the wiring layer 132 is also formed on the end of the wafer substrate 131.
[0101]
Next, a fourth interlayer insulating film 44 made of a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, a silicon oxide film, or the like is formed by, for example, normal pressure or reduced pressure CVD using TEOS gas or the like. (Step S47). The thickness of the fourth interlayer insulating film 44 is, for example, about 500 to 1500 nm.
[0102]
Next, in step S48, as shown in FIG. 5, the fourth interlayer insulating film 44 is planarized using, for example, CMP. Next, a contact hole 89 is formed by dry etching such as reactive ion etching or reactive ion beam etching on the fourth interlayer insulating film 44 (step S49). At this time, the contact hole 89 is formed so as to communicate with the third relay electrode 402.
[0103]
Next, a transparent conductive film such as an ITO film is deposited on the fourth interlayer insulating film 44 by sputtering or the like to a thickness of about 50 to 200 nm. Then, the pixel electrode 9a is formed by photolithography and etching (Step S50), and finally a PAD is formed (Step S51).
[0104]
FIG. 1 is a flowchart specifically showing a process of forming an ITO film to be a pixel electrode 9a and a process of forming a PAD. FIG. 6 shows a cross-sectional structure near the outer peripheral portion of the wafer substrate 131. In FIG. 6, for simplification of the drawing, a film forming layer and an interlayer insulating film between the wafer substrate 131 and the wiring layer 132 (corresponding to the shield layer 400 in FIG. 5) are omitted. I have.
[0105]
As described above, in the vicinity of the outer peripheral portion of the wafer substrate 131, the wiring layer 132 is extended by the same film forming step as the step of forming the shield layer 400. On the wiring layer 132, the above-described fourth interlayer insulating film 132 (the same film as the interlayer insulating film 44 in FIG. 5) is formed on the entire surface.
[0106]
The contact hole forming process in step S1 of FIG. 1 shows the same process as the contact hole forming process in step S49 of FIG. As described above, the contact hole 89 for electrically connecting the ITO film serving as the pixel electrode 9a and the lower third relay electrode 402 is formed. In the next step S2, the resist mask used for forming the contact hole is removed.
[0107]
Next, in step S3, an ITO film 134 is formed on the entire surface of the interlayer insulating film 132 (44). FIG. 8A is for explaining a sputtering process used for various film forming processes. As shown in FIG. 8A, in the sputtering process, a target 145 is arranged on a wafer substrate 131 via a mask 146 (hatched portion) having an open central portion of the wafer substrate 131. A voltage is applied to the target 145 to form a film 147 on the wafer substrate 131. By using an ITO target, an ITO film 134 is formed. The mask 146 limits the range of the sputtering process to within the wafer substrate 131. Since the mask 146 is provided, the composition ratio of the ITO film 134 becomes abnormal near the outer peripheral portion of the wafer substrate 131. FIG. 6A shows a state in which an ITO film 134 is formed on the entire surface of the interlayer insulating film 133 (44).
[0108]
Next, in step S4, a photolithography process is performed to form a resist 136 on the ITO film 134. In this case, the resist 136 is subjected to edge rinsing in order to prevent the resist 136 from peeling off during transportation to the exposure device, and the resist 136 near the outer peripheral portion of the wafer substrate 131 is removed. Next, the resist 136 is patterned as a mask pattern according to the shape of the pixel electrode 9a, and then a dry etching step is performed (Step S5).
[0109]
FIG. 6B shows a state near the outer peripheral portion of the wafer substrate 131 during the dry etching process for the ITO film 134. A clamp 137 is arranged on the resist 135b on the outer peripheral portion of the wafer substrate 131. The clamp 137 fixes the wafer substrate 131. FIG. 8B shows the region 141 covered by the clamp 137 during the etching process for the ITO film 134 by the hatched portion. Etching is performed in a state where the outer peripheral portion of the wafer substrate 131 is covered by the clamp 137. Thus, the ITO film 134 is patterned to form an ITO film 135 (pixel electrode 9a). Further, since the outer peripheral portion of the wafer substrate 131 is covered with the clamp 137, this portion is not etched and the ITO film 135b remains. In the next step S6, the resist 136 is stripped.
[0110]
Next, in step S7, a photolithography step for forming a PAD is performed. That is, an opening for exposing the wiring layer 132 (400) formed below the ITO film 135 (9a) is formed. A resist 138 is formed in a pattern except for the opening.
[0111]
FIG. 6C shows this state. In the present embodiment, as shown in FIG. 6C, the resist 138 is extended to a region outside the remaining ITO film 135b on the outer peripheral portion of the wafer substrate 131, and the interlayer insulating film 133 (44) is formed. Is formed so as to cover the surface. Also, when the resist 138 is formed, edge rinsing is performed in the vicinity of the outer peripheral portion of the wafer substrate 131. In this case, since it is necessary to form the register and the 138 so as to cover the interlayer insulating film 133 (44), the resist 138 is not completely removed at the time of edge rinsing, but the thickness is reduced. I do.
[0112]
Next, in step S8, a wet etching process is performed to form an opening 139 (FIG. 6D). Next, in step S9, the resist 138 is stripped. Thus, the state shown in FIG.
[0113]
As shown in FIG. 8D, near the outer peripheral portion of the wafer substrate 131, the ITO film 135b remains on the interlayer insulating film 133 (44). The interlayer insulating film 133 (44) is covered with the resist 138 in the etching step of step S8, and is prevented from being etched. Thus, the bottom surface of the ITO film 135b near the outer peripheral portion of the wafer substrate 131 is supported by the interlayer insulating film 133 (44) without being exposed. Therefore, even if the film quality of the ITO film 135b is poor, it is difficult for the ITO film 135b to peel off.
[0114]
In step S10, electrical characteristics are inspected, and scrub cleaning is performed in step S11. During the scrub cleaning in step S11, the ITO film 135b near the outer peripheral portion of the wafer substrate 131 is not easily peeled off, so that the ITO film 135b in this portion is prevented from being peeled off and reattached to the wafer substrate 131 as foreign matter. You.
[0115]
When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as AL. Next, a coating liquid of a polyimide-based alignment film is applied on the pixel electrode 9a, and then a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle, and the alignment film 16 is formed. You.
[0116]
On the other hand, as the counter substrate 20, a glass substrate or the like is first prepared, and a light-shielding film 53 as a frame is formed by, for example, sputtering metal chromium and then performing photolithography and etching. The light-shielding film 53 does not need to be conductive, and may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr, Ni, or AL.
[0117]
Next, an opposing electrode 21 is formed by depositing a transparent conductive film such as an ITO film to a thickness of about 50 to 200 nm on the entire surface of the opposing substrate 20 by sputtering or the like. Further, an alignment film 22 is formed by applying a coating liquid of a polyimide-based alignment film to the entire surface of the counter electrode 21 and then performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.
[0118]
Next, the sealing material 52 is formed along the four sides of each TFT substrate 10 formed on the wafer substrate 131, and the upper and lower conductive materials 106 are formed at the four corners of the sealing material 52, so that the alignment films 16 and 22 are formed. The TFT substrates 10 and the opposing substrates 20 are attached to each other with the sealing member 52 so as to face each other. The upper and lower conductive members 106 contact the upper and lower conductive terminals 107 of the TFT substrate 10 at the lower end, and contact the common electrode 21 of the opposing substrate 20 at the upper end.
[0119]
Then, for example, a liquid crystal obtained by mixing a plurality of types of nematic liquid crystals is sucked into a space between the two substrates by vacuum suction or the like, and a liquid crystal layer 50 having a predetermined thickness is formed. Then, the liquid crystal panel including the TFT substrate 10 and the counter substrate 20 is separated from the wafer substrate 131.
[0120]
The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like, and is cured by ultraviolet light, heating, or the like in order to bond the two substrates together. In addition, if the liquid crystal device according to the present embodiment is applied to a liquid crystal device that is small and performs enlarged display such as a projector, the distance between the two substrates (the gap between the substrates) ) Is set to a predetermined value, and a cap material (spacer) such as glass fiber or glass beads is sprayed. Alternatively, such a gap material may be included in the liquid crystal layer 50 if the liquid crystal device is applied to a liquid crystal device that performs large-size and equal-size display such as a liquid crystal display or a liquid crystal television.
[0121]
If the delay of the scanning signal supplied to the scanning line 11a and the gate electrode 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area 10a.
[0122]
Further, on the TFT substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit for applying an image signal to a plurality of data lines 6a at a predetermined timing, a plurality of data lines 6a A precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping. Good.
[0123]
Further, in the above-described embodiment, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the wafer substrate 131, for example, the driving LSI mounted on a TAB (Tape Automated Bonding) substrate is provided with a wafer substrate. The connection may be made electrically and mechanically via an anisotropic conductive film provided on the periphery of the 131. For example, a TN (Twisted Nematic) mode, a VA (Vertically Aligned) mode, and a PDLC (Polymer Dispersed Liquid Crystal) are provided on the side of the opposite substrate 20 on which the projected light is incident and on the side of the emitted light of the wafer substrate 131, respectively. A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a mode or a normally white mode or a normally black mode.
[0124]
Further, in the above embodiment, an example of a substrate for a liquid crystal device has been described, but it is apparent that the present invention is also applicable to a semiconductor substrate having a laminated structure of a conductive material and an interlayer insulating film.
[0125]
As described above, in the present embodiment, at the time of wet etching performed after the dry etching of the ITO film, the resist is formed to the outside of the ITO film so as to cover the interlayer insulating film even at the outer peripheral portion of the wafer substrate, It is possible to prevent the interlayer insulating film below the ITO film in the outer peripheral portion of the substrate from being removed at the time of wet etching, and to prevent foreign matters from being mixed due to peeling of the ITO film in this portion. As a result, it is possible to prevent the occurrence of element defects such as a short circuit between adjacent pixel electrodes.
[0126]
(Example)
FIG. 10 shows an example of conditions for effectively preventing peeling of the ITO film near the outer peripheral portion of the wafer substrate. FIG. 10 shows the thickness of the ITO film 135b formed in the vicinity of the outer peripheral portion of the wafer substrate 131 and the outer peripheral position of the resist with respect to the interlayer insulating film 133 (44) in the outermost end of the ITO film 135b formed by the sputtering process. It is shown by the range of distance from.
[0127]
As shown in FIG. 10, as the thickness of the ITO film 135b is larger and the thickness of the interlayer insulating film 133 (44) is smaller, the resist is formed more outward from the outermost end of the ITO film.
[0128]
The substrate for an electro-optical device manufactured by the present invention is not limited to a substrate for a liquid crystal device, but may be applied to a substrate used for an organic electroluminescence device, an electroluminescence device of an inorganic electroluminescence device, an electrophoresis device, and the like. Needless to say. Further, an example in which a plurality of TFT substrates are formed on one wafer substrate has been described, but the present invention is similarly applicable to a case where one electro-optical device substrate is formed on one wafer substrate.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a method for manufacturing a substrate according to a first embodiment of the present invention.
FIG. 2 is a plan view of a liquid crystal device formed using the electro-optical device substrate manufactured in the present embodiment, together with components formed thereon, as viewed from the counter substrate side.
FIG. 3 is a cross-sectional view of the liquid crystal device after the assembly step of bonding an element substrate and a counter substrate and enclosing liquid crystal after completion of the assembly process, taken along the line HH ′ in FIG. 2;
FIG. 4 is an equivalent circuit diagram of various elements, wiring, and the like in a plurality of pixels forming a pixel region of the liquid crystal device illustrated in FIGS. 2 and 3;
FIG. 5 is a cross-sectional view illustrating a pixel structure of the liquid crystal device illustrated in FIGS. 2 and 3 in detail.
FIG. 6 is a process chart showing a method of forming an ITO film and a PAD in a sectional view in the order of steps.
FIG. 7 is an explanatory view showing a wafer substrate at the time of manufacturing an array.
FIG. 8 is an explanatory diagram for explaining an ITO film forming step and an etching step.
FIG. 9 is a flowchart showing a method for manufacturing a substrate for a liquid crystal device.
FIG. 10 is a table showing effective resist formation ranges.
FIG. 11 is an explanatory diagram for explaining a problem of a conventional example.
[Explanation of symbols]
S4: ITO sputtering step, S5: ITO photo step, S6: ITO etching step, S8: PAD photo step, S9: PAD etching step.

Claims (7)

Forming an interlayer insulating film disposed between a plurality of film layers stacked on the substrate,
Forming a film formation layer of a conductive material on the interlayer insulating film,
A method of manufacturing a substrate, comprising a step of coating at least the interlayer insulating film with a resist on an end face of the substrate during wet etching performed after patterning of a film formation layer with the conductive material. In the vicinity of the end face of the substrate, the resist is extended toward the outside of the substrate by a predetermined distance from the end face of the film formation layer made of the conductive material, so that the interlayer insulating film is coated on the end face of the substrate. The method for manufacturing a substrate according to claim 1, wherein: 2. The method of manufacturing a substrate according to claim 1, wherein the resist is edge-rinsed near an end face of the substrate, and has a smaller thickness than other portions. Forming a wiring layer below the interlayer insulating film before the step of forming the interlayer insulating film;
2. The method according to claim 1, further comprising, after the step of covering with the resist, a step of forming an opening for exposing the wiring layer by the wet etching. A step of forming an interlayer insulating film on a film formation layer laminated on the substrate,
Forming a transparent electrode on the interlayer insulating film;
A method of manufacturing a substrate for an electro-optical device, comprising a step of coating at least the interlayer insulating film with a resist on an end face of the substrate during wet etching performed after patterning of the transparent electrode. Forming a wiring layer on the substrate;
Forming an interlayer insulating film on the wiring layer;
Forming a transparent electrode on the interlayer insulating film;
After patterning the transparent electrode, forming a resist so as to cover at least the interlayer insulating film at the end face of the substrate,
Forming a hole for exposing the wiring layer by performing wet etching using the resist as a mask pattern. Liquid crystal using a substrate for a liquid crystal device manufactured by the method for manufacturing a substrate according to any one of claims 1 to 4 or the method for manufacturing a substrate for an electro-optical device according to any one of claims 5 and 6. A method for manufacturing a liquid crystal device, comprising manufacturing the device.

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