JP2004304107A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004304107A
JP2004304107A JP2003097895A JP2003097895A JP2004304107A JP 2004304107 A JP2004304107 A JP 2004304107A JP 2003097895 A JP2003097895 A JP 2003097895A JP 2003097895 A JP2003097895 A JP 2003097895A JP 2004304107 A JP2004304107 A JP 2004304107A
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JP
Japan
Prior art keywords
insulating film
diffusion layer
selective opening
forming
semiconductor device
Prior art date
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Pending
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JP2003097895A
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Japanese (ja)
Inventor
Taku Kondo
近藤  卓
Ryoichi Amishimoto
亮一 網師本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2003097895A priority Critical patent/JP2004304107A/en
Publication of JP2004304107A publication Critical patent/JP2004304107A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with an electrode extraction structure which can prevent the step cut of a metal electrode provided on a high impurity concentration diffusion layer of the semiconductor device, and to provide its manufacturing method. <P>SOLUTION: Insulating films 4a, 4b, and 4c are composed of laminated layers of two or more different insulating films partitioning a semiconductor element region selectively provided at a semiconductor substrate 1. The insulating film 4c laminated on the uppermost part is formed so as to cover the side face part on the selective aperture side and to reach the high impurity concentration diffusion layer. Accordingly, it can prevent a clearance like an eave from being formed on the selective aperture side face because of excessive etching to a specific insulating film only by the chemical etching to be executed at the time of forming the selective aperture. Also, a second selective aperture 6b is formed smaller than a first selective aperture 6a. The laminated structure of the insulating film is made into a terrace shape. As a result, the steep surface shape of the selective aperture can be improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置に関し、特に半導体基板上における拡散層領域からの電極取り出し構造を改善した半導体装置およびその製造方法に係わるものである。
【0002】
【従来の技術】
近年、半導体装置は高集積化及び微細化が著しく進み、表面実装化を受けて小型、薄型化される傾向にある。このため、従来では不具合とならなかったことが問題として生じており、これを解決するため、半導体装置の構造の改善や製造方法の改善などが提案されてきた(特許文献1参照)。
【0003】
図5は、特許文献1に記載された半導体チップの構造断面図である。
【0004】
同図の半導体チップは、まずN型シリコン基板1上に、二酸化シリコン膜3を選択的に形成し、この二酸化シリコン膜3で区画されるN型シリコン基板1上にP型拡散層2を形成する。さらに、これらの上に二酸化シリコン膜や窒化シリコン膜、リンシリケートグラスなどの絶縁膜4a、b、cを化学的気相成長法(CVD法)により堆積させる。次に、化学的エッチングにより、P型拡散層2に達する選択開孔6を前記絶縁膜4a、b、c上に形成し、その上にアルミニウムにより成る金属電極5を設けて成っている。
【0005】
【特許文献1】
特公昭54−35069号公報(第3頁、第9図)
【0006】
【発明が解決しようとする課題】
上記のような従来の半導体装置の構造によれば、素子間分離領域となる二酸化シリコン膜3上に、二つ以上の絶縁膜を積層する構造のため、P型拡散層2上に比べ最上部の絶縁膜4c上は数百nm以上高い位置となっており、極めて急峻な形状をしている。また、各絶縁膜のエッチングレートが異なるため、選択開孔6形成時におこなう化学的エッチングによって、特定の絶縁膜の層だけが過剰にエッチングされることにより、選択開孔6側面の一部がえぐれたひさしのような空隙が形成される。このため、選択開孔6上に被着される金属電極5の開孔内段差被覆性が悪くなり、金属電極5の段切れを起こすことになる。
【0007】
すなわち、チップ表面の電極が段切れを起こすことで、電極構造の不具合を生じ、半導体装置の特性及び品質に影響を及ぼすという問題があった。また、この問題は半導体装置の高集積化及び微細化に伴い、より顕著になる傾向にある。
【0008】
そこで本発明は、従来の上記実情に鑑みてなされたものであり、従来の技術に内在する上記課題を解決することを可能にする半導体装置およびその製造方法を提供することを目的とする。
【0009】
【課題を解決するための手段】
本発明による半導体装置は、半導体基板上に選択的に設けられた半導体素子領域を区画する絶縁膜と、半導体素子領域に設けられた高不純物濃度の拡散層と、この拡散層上に設けられた選択開孔と、この選択開孔上に選択的に設けられた金属電極とを含んで成る電極構造をし、絶縁膜が、二つ以上の異なる絶縁膜の積層から成り、最上部に積層されている絶縁膜が選択開孔側の側面部を覆い、高不純物濃度の拡散層にまで達している。また、二つ以上の異なる絶縁膜の積層から成る絶縁膜において、絶縁膜の選択開孔側の側面部が段丘状に積層されて成る。
【0010】
また、本発明による半導体装置の製造方法は、半導体基板上に半導体素子領域を区画する絶縁膜を選択的に形成する工程と、前記半導体素子領域に高不純物濃度の拡散層を形成する工程と、前記半導体素子領域の上に各種絶縁膜を形成する工程と、前記高不純物濃度の拡散層に達する第1の選択開孔を前記絶縁膜に形成する工程と、前記第1の選択開孔を含む前記半導体素子領域の全面を覆う単一の絶縁膜を形成する工程と、前記高不純物濃度の拡散層に達する前記第1の選択開孔よりも小さい第2の選択開孔を形成する工程と、前記第2の選択開孔を通して前記高不純物濃度の拡散層に達する電極用導電体膜を形成する工程と、からなる。
【0011】
本発明によると、半導体装置における電極構造を改善することで、電極の段切れを防ぐことができる。したがって、良好な特性および高い信頼性を有する半導体装置およびその製造方法を提供することができる。
【0012】
【発明の実施の形態】
以下、本発明の実施の形態について、図面を参照しながら説明する。
【0013】
図1は、本発明に係る半導体装置の実施の形態を説明するための半導体チップの構造断面図であり、図2(a)〜図4(j)は、その製造方法を示す工程断面図である。
【0014】
図1に示されるように、N型シリコン基板1上に、二酸化シリコン膜3が選択的に設けられており、この二酸化シリコン膜3で区画されるN型シリコン基板1上にP型拡散層2が形成されている。二酸化シリコン膜3上には、リンシリケートグラスや窒化シリコン膜、二酸化シリコン膜などの絶縁膜4a、b、cが堆積されており、P型拡散層2上に位置する絶縁膜4a、b、cには、P型拡散層2に達する選択開孔6が形成されており、最上部の絶縁膜4cが選択開孔6側の絶縁膜4a、bの側面部を覆い、P型拡散層2にまで達している。この上に、選択開孔6を通してP型拡散層2にまで達するアルミニウムなどの金属により成る金属電極5が選択被着されている。また、N型シリコン基板1の裏面には、裏面電極7が形成されている。
【0015】
この構造によれば、最上部の絶縁膜4cがその下の絶縁膜4a、bの選択開孔6側の側面部を覆っており、絶縁膜全体の積層構造が段球状になっている。このため、選択開孔6内の側面にひさしのような空隙がなく、また、選択開孔6の急峻な表面形状が緩和されているので、金属電極5の開孔内段差被覆性が著しく改善されている。したがって、従来の半導体装置の電極取り出し構造で見られた金属電極の段切れを防ぐことができる。
【0016】
次に、図2〜図4を参照して、本発明にかかる半導体装置の実施の形態の製造方法について説明する。図2(a)および(b)に示すように、N型シリコン基板1上に通常のパイロジェニックスチーム酸化法により、膜厚約600nmの二酸化シリコン膜3を形成し、所定のパターンのフォトレジスト8を形成しこれをマスクとして、二酸化シリコン膜3を選択的にエッチング除去することにより、半導体素子領域を区画する。次に、図2(c)に示すように、この二酸化シリコン膜3で区画されるN型シリコン基板1上に窒化ホウ素を蒸着し、拡散炉にてホウ素をN型シリコン基板1内へ熱拡散させることでP型拡散層2を形成する。
【0017】
図2(d)に示すように、この上に順次リンシリケートグラスや窒化シリコン膜、二酸化シリコン膜などの絶縁膜4a、bを科学的気相成長法により堆積させる。次に、図3(e)(f)に示すように、P型拡散層2上に位置する絶縁膜4a、bに、P型拡散層2に達する第1の選択開孔6aを所定のパターンのフォトレジスト8を形成しこれをマスクとして、化学的エッチングにより形成し、図3(g)に示すように、その上に二酸化シリコンまたは、窒化シリコンなどの絶縁膜を一種類だけ被着形成する。
【0018】
次に、図3(h)、図4(i)に示すように、P型拡散層2上に位置する絶縁膜4cに、P型拡散層2に達する第1の選択開孔6aよりも小さい第2の選択開孔6bを所定のパターンのフォトレジスト8を形成しこれをマスクとして、化学的エッチングにより形成する。次に、図4(j)に示すように、真空蒸着法によりアルミニウムを約4μmの膜厚に成長させ、フォトリソグラフィ法によりパターニングしてアルミニウムより成る金属電極5を形成し、最後に、N型シリコン基板1の裏面に電子ビーム蒸着法により金、アンチモン、ニッケルからなる合金を約2μmの膜厚に成長させ、裏面電極7を形成する。
【0019】
選択開孔を二度に分けて形成するため、最上部に被着された絶縁膜4cが選択開孔側の側面部を覆う構造となる。また、第1の選択開孔6aよりも第2の選択開孔6bの方が小さいため、絶縁膜の積層構造が段丘上となる。これにより、化学的エッチングによって特定の絶縁膜だけが過剰にエッチングされ、選択開孔6内側面にひさしのような空隙が形成するのを防ぐことができると同時に、選択開孔の急峻な表面形状を改善することができる。すなわち、金属電極5の開孔内段差被覆性が改善され、金属電極の段切れを防ぐことが可能となる。
【0020】
本発明の上記実施の形態では、PN接合ダイオードおよびその製造方法に関して説明したが、本発明はこれに限定されるものではなく、ショットキーバリアダイオード、トランジスタ、IC等の半導体装置の電極または配線取り出し構造に適用できるものである。
【0021】
【発明の効果】
本発明によれば、半導体基板上に選択的に設けられた半導体素子領域を区画する二つ以上の異なる絶縁膜の積層から成る絶縁膜において、最上部に積層されている絶縁膜が選択開孔側の側面部を覆い、高不純物濃度の拡散層にまで達しているため、選択開孔形成時におこなう化学的エッチングにより特定の絶縁膜だけが過剰にエッチングされて選択開孔側面にひさしのような空隙が形成されることを防ぐことができる。また、第1の選択開孔よりも第2の選択開孔の方が小さいため、絶縁膜の積層構造が段丘状となることから、選択開孔の急峻な表面形状が改善できる。すなわち、金属電極の開孔内段差被覆性が改善され、金属電極の段切れを防ぐことが可能となる。
【0022】
したがって、本発明によれば、半導体チップ表面の電極の段切れを防ぐことで、良好な特性および高い信頼性を有する半導体装置を提供することが可能となる。
【図面の簡単な説明】
【図1】本発明の実施の形態における半導体装置のチップ構造断面図
【図2】本発明の実施の形態における半導体装置の製造方法の工程断面図で、
(a)基板上に二酸化シリコン膜、フォトレジストを形成した状態の断面図
(b)半導体素子領域を区画形成した状態の断面図
(c)区画された基板上にP型拡散層を形成した状態の断面図
(d)P型拡散層上に絶縁膜を堆積形成した状態の断面図
【図3】本発明の実施の形態における半導体装置の製造方法の工程断面図で、
(e)絶縁膜に所定のフォトレジストを形成した状態の断面図
(f)絶縁膜に第1の選択開孔を形成した状態の断面図
(g)その上に絶縁膜を一種類だけ被着形成した状態の断面図
(h)絶縁膜に所定のフォトレジストを形成した状態の断面図
【図4】本発明の実施の形態における半導体装置の製造方法の工程断面図で、
(i)絶縁膜に、第1の選択開孔よりも小さい第2の選択開孔を形成した状態の断面図
(j)アルミニウムにより成る電極、さらに基板の裏面に電極を形成した断面図
【図5】従来の半導体装置のチップ構造断面図
【符号の説明】
1 N型シリコン基板
2 P型拡散層
3 二酸化シリコン膜
4a 絶縁膜
4b 絶縁膜
4c 絶縁膜
5 金属電極
6 選択開孔
6a 第1の選択開孔
6b 第2の選択開孔
7 裏面電極
8 フォトレジスト
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an improved electrode extraction structure from a diffusion layer region on a semiconductor substrate and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, high integration and miniaturization of semiconductor devices have been remarkably advanced, and there has been a tendency to be reduced in size and thickness due to surface mounting. For this reason, there has been a problem that no problem has occurred in the past. To solve this problem, improvements in the structure of the semiconductor device, improvements in the manufacturing method, and the like have been proposed (see Patent Document 1).
[0003]
FIG. 5 is a structural sectional view of a semiconductor chip described in Patent Document 1.
[0004]
In the semiconductor chip shown in FIG. 1, first, a silicon dioxide film 3 is selectively formed on an N-type silicon substrate 1, and a P-type diffusion layer 2 is formed on an N-type silicon substrate 1 partitioned by the silicon dioxide film 3. I do. Further, insulating films 4a, b, and c such as a silicon dioxide film, a silicon nitride film, and a phosphor silicate glass are deposited thereon by a chemical vapor deposition (CVD) method. Next, selective openings 6 reaching the P-type diffusion layer 2 are formed on the insulating films 4a, 4b and 4c by chemical etching, and a metal electrode 5 made of aluminum is provided thereon.
[0005]
[Patent Document 1]
JP-B-54-35069 (page 3, FIG. 9)
[0006]
[Problems to be solved by the invention]
According to the structure of the conventional semiconductor device as described above, two or more insulating films are stacked on the silicon dioxide film 3 serving as an element isolation region. Above the insulating film 4c is several hundred nm or higher, and has a very steep shape. Further, since the etching rates of the respective insulating films are different, only the layer of the specific insulating film is excessively etched by the chemical etching performed at the time of forming the selective opening 6, so that a part of the side surface of the selective opening 6 is scooped. A void like an eaves is formed. For this reason, the step coverage in the opening of the metal electrode 5 deposited on the selective opening 6 is deteriorated, and the step of the metal electrode 5 is caused.
[0007]
In other words, there has been a problem in that the electrode structure on the chip surface is disconnected, causing a problem in the electrode structure and affecting the characteristics and quality of the semiconductor device. In addition, this problem tends to become more remarkable as the integration and miniaturization of the semiconductor device increase.
[0008]
Therefore, the present invention has been made in view of the above-described conventional circumstances, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can solve the above-described problems inherent in the conventional technology.
[0009]
[Means for Solving the Problems]
The semiconductor device according to the present invention includes an insulating film for partitioning a semiconductor element region selectively provided on a semiconductor substrate, a diffusion layer having a high impurity concentration provided in the semiconductor element region, and provided on the diffusion layer. An electrode structure including a selective opening and a metal electrode selectively provided on the selective opening, wherein the insulating film is formed by laminating two or more different insulating films, and is laminated on the uppermost portion. The insulating film covers the side surface on the selective opening side and reaches the diffusion layer having a high impurity concentration. Further, in an insulating film formed by laminating two or more different insulating films, the side surface on the selective opening side of the insulating film is laminated in a terrace shape.
[0010]
In addition, the method for manufacturing a semiconductor device according to the present invention includes a step of selectively forming an insulating film for partitioning a semiconductor element region on a semiconductor substrate; and a step of forming a high impurity concentration diffusion layer in the semiconductor element region. A step of forming various insulating films on the semiconductor element region, a step of forming a first selective opening reaching the high impurity concentration diffusion layer in the insulating film, and the first selective opening Forming a single insulating film covering the entire surface of the semiconductor element region, and forming a second selective opening smaller than the first selective opening reaching the high impurity concentration diffusion layer; Forming a conductive film for an electrode reaching the diffusion layer having a high impurity concentration through the second selective opening.
[0011]
According to the present invention, disconnection of the electrode can be prevented by improving the electrode structure in the semiconductor device. Therefore, a semiconductor device having good characteristics and high reliability and a method for manufacturing the same can be provided.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
FIG. 1 is a structural cross-sectional view of a semiconductor chip for describing an embodiment of a semiconductor device according to the present invention, and FIGS. 2A to 4J are process cross-sectional views showing a manufacturing method thereof. is there.
[0014]
As shown in FIG. 1, a silicon dioxide film 3 is selectively provided on an n-type silicon substrate 1, and a p-type diffusion layer 2 is formed on an n-type silicon substrate 1 partitioned by the silicon dioxide film 3. Is formed. On the silicon dioxide film 3, insulating films 4a, b, c such as a phosphor silicate glass, a silicon nitride film, and a silicon dioxide film are deposited, and the insulating films 4a, b, c located on the P-type diffusion layer 2 are formed. Is formed with a selective opening 6 reaching the P-type diffusion layer 2, the uppermost insulating film 4c covers the side surfaces of the insulating films 4a and 4b on the selective opening 6 side. Has reached. A metal electrode 5 made of a metal such as aluminum which reaches the P-type diffusion layer 2 through the selective opening 6 is selectively deposited thereon. On the back surface of the N-type silicon substrate 1, a back surface electrode 7 is formed.
[0015]
According to this structure, the uppermost insulating film 4c covers the side surface of the insulating films 4a and b thereunder on the side of the selective opening 6, and the laminated structure of the entire insulating film has a spherical shape. For this reason, there is no gap like an eave on the side surface in the selective opening 6 and the sharp surface shape of the selective opening 6 is relaxed, so that the step coverage in the opening of the metal electrode 5 is remarkably improved. Have been. Therefore, it is possible to prevent disconnection of the metal electrode which is observed in the conventional electrode extraction structure of the semiconductor device.
[0016]
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIGS. 2A and 2B, a silicon dioxide film 3 having a thickness of about 600 nm is formed on an N-type silicon substrate 1 by a usual pyrogenic steam oxidation method, and a photoresist 8 having a predetermined pattern is formed. Is formed, and the silicon dioxide film 3 is selectively etched and removed using the mask as a mask, thereby defining a semiconductor element region. Next, as shown in FIG. 2C, boron nitride is deposited on the N-type silicon substrate 1 partitioned by the silicon dioxide film 3, and the boron is thermally diffused into the N-type silicon substrate 1 in a diffusion furnace. By doing so, the P-type diffusion layer 2 is formed.
[0017]
As shown in FIG. 2D, insulating films 4a and 4b such as a phosphor silicate glass, a silicon nitride film, and a silicon dioxide film are sequentially deposited thereon by a chemical vapor deposition method. Next, as shown in FIGS. 3E and 3F, the first selective openings 6a reaching the P-type diffusion layer 2 are formed in the insulating films 4a and 4b located on the P-type diffusion layer 2 in a predetermined pattern. Is formed by chemical etching using the photoresist 8 as a mask, and as shown in FIG. 3 (g), only one type of insulating film such as silicon dioxide or silicon nitride is deposited thereon. .
[0018]
Next, as shown in FIG. 3 (h) and FIG. 4 (i), the insulating film 4c located on the P-type diffusion layer 2 is smaller than the first selective opening 6a reaching the P-type diffusion layer 2. The second selective opening 6b is formed by forming a photoresist 8 having a predetermined pattern and using this as a mask by chemical etching. Next, as shown in FIG. 4 (j), aluminum is grown to a thickness of about 4 μm by vacuum evaporation and patterned by photolithography to form a metal electrode 5 made of aluminum. An alloy made of gold, antimony, and nickel is grown to a thickness of about 2 μm on the back surface of the silicon substrate 1 by electron beam evaporation to form a back electrode 7.
[0019]
Since the selective opening is formed twice, the insulating film 4c deposited on the uppermost portion covers the side surface on the selective opening side. In addition, since the second selective opening 6b is smaller than the first selective opening 6a, the laminated structure of the insulating film is on a terrace. Thereby, it is possible to prevent the specific insulating film from being excessively etched by the chemical etching and to form a gap like an eave on the inner side surface of the selective opening 6, and at the same time, to have a steep surface shape of the selective opening. Can be improved. That is, the step coverage in the opening of the metal electrode 5 is improved, and it is possible to prevent disconnection of the metal electrode.
[0020]
In the above embodiments of the present invention, a PN junction diode and a method of manufacturing the same have been described. However, the present invention is not limited to this, and the electrodes or wiring of semiconductor devices such as Schottky barrier diodes, transistors, and ICs are taken out. It is applicable to the structure.
[0021]
【The invention's effect】
According to the present invention, in an insulating film composed of a stack of two or more different insulating films that partition a semiconductor element region selectively provided on a semiconductor substrate, the insulating film stacked at the top is selectively opened. Because the side surface of the side is covered and reaches the diffusion layer with high impurity concentration, only the specific insulating film is excessively etched by the chemical etching performed at the time of forming the selective opening, and the like The formation of voids can be prevented. In addition, since the second selective aperture is smaller than the first selective aperture, the laminated structure of the insulating film has a stepped shape, so that the steep surface shape of the selective aperture can be improved. That is, the step coverage in the opening of the metal electrode is improved, and disconnection of the metal electrode can be prevented.
[0022]
Therefore, according to the present invention, it is possible to provide a semiconductor device having good characteristics and high reliability by preventing disconnection of an electrode on the surface of a semiconductor chip.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a chip structure of a semiconductor device according to an embodiment of the present invention; FIG. 2 is a process cross-sectional view of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
(A) Cross-sectional view in which a silicon dioxide film and a photoresist are formed on a substrate (b) Cross-sectional view in which a semiconductor element region is formed (c) A state in which a P-type diffusion layer is formed on a partitioned substrate FIG. 3 is a cross-sectional view of a state in which an insulating film is deposited and formed on a P-type diffusion layer. FIG. 3 is a cross-sectional view of a process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
(E) A cross-sectional view in which a predetermined photoresist is formed in the insulating film. (F) A cross-sectional view in a state in which a first selective opening is formed in the insulating film. (G) Only one type of insulating film is deposited thereon. FIG. 4 is a cross-sectional view of a state in which a predetermined photoresist is formed on an insulating film. FIG. 4 is a cross-sectional view of a manufacturing method of a semiconductor device according to an embodiment of the present invention.
(I) Cross-sectional view showing a state where a second selective opening smaller than the first selective opening is formed in an insulating film. (J) Cross-sectional view showing an electrode made of aluminum and an electrode formed on the back surface of the substrate. 5 Cross-sectional view of a conventional semiconductor device chip structure
REFERENCE SIGNS LIST 1 N-type silicon substrate 2 P-type diffusion layer 3 silicon dioxide film 4 a insulating film 4 b insulating film 4 c insulating film 5 metal electrode 6 selective opening 6 a first selective opening 6 b second selective opening 7 backside electrode 8 photoresist

Claims (3)

半導体基板上に選択的に設けられた半導体素子領域を区画する絶縁膜と、前記半導体素子領域に設けられた高不純物濃度の拡散層と、該拡散層上に設けられた選択開孔と、該選択開孔上に選択的に設けられた金属電極とを含んで成る電極構造を有する半導体装置において、前記絶縁膜は、二つ以上の異なる絶縁膜の積層から成る絶縁膜で、最上層部に積層されている絶縁膜が、前記絶縁膜における選択開孔側の側面部を覆い、前記高不純物濃度の拡散層にまで達していることを特徴とする半導体装置。An insulating film for partitioning a semiconductor element region selectively provided on a semiconductor substrate, a high impurity concentration diffusion layer provided in the semiconductor element region, a selective opening provided on the diffusion layer, In a semiconductor device having an electrode structure including a metal electrode selectively provided on a selective opening, the insulating film is an insulating film composed of a stack of two or more different insulating films, A semiconductor device, wherein a stacked insulating film covers a side surface of the insulating film on a selective opening side and reaches the diffusion layer having a high impurity concentration. 二つ以上の異なる絶縁膜の積層から成る絶縁膜において、絶縁膜の選択開孔側の側面部が段丘状に積層されていることを特徴とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein, in an insulating film formed by laminating two or more different insulating films, a side surface of the insulating film on a selective opening side is stacked in a stepped shape. 半導体基板上に半導体素子領域を区画する絶縁膜を選択的に形成する工程と、前記半導体素子領域に高不純物濃度の拡散層を形成する工程と、前記半導体素子領域の上に各種絶縁膜を形成する工程と、前記高不純物濃度の拡散層に達する第1の選択開孔を前記絶縁膜に形成する工程と、前記第1の選択開孔を含む前記半導体素子領域の全面を覆う単一の絶縁膜を形成する工程と、前記高不純物濃度の拡散層に達する前記第1の選択開孔よりも小さい第2の選択開孔を形成する工程と、前記第2の選択開孔を通して前記高不純物濃度の拡散層に達する金属電極を形成する工程と、からなることを特徴とした半導体装置の製造方法。A step of selectively forming an insulating film for partitioning a semiconductor element region on a semiconductor substrate, a step of forming a diffusion layer having a high impurity concentration in the semiconductor element region, and forming various insulating films on the semiconductor element region Forming a first selective opening reaching the high impurity concentration diffusion layer in the insulating film; and forming a single insulating layer covering the entire surface of the semiconductor element region including the first selective opening. Forming a film; forming a second selective opening smaller than the first selective opening reaching the high impurity concentration diffusion layer; and forming the high impurity concentration through the second selective opening. Forming a metal electrode reaching the diffusion layer of (1).
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