JP2004303333A - Ferroelectric storage device and its selection voltage adjustment method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric storage device wherein disturbance is reduced and high speed reading and low power consumption are possible and to provide its selection voltage adjustment method. <P>SOLUTION: The selection voltage adjustment method of the ferroelectric storage device has a step for respectively detecting voltages V<SB>0</SB>to V<SB>4</SB>outputted via either one of a wordline 14 and a bit line 16 connected to a ferroelectric memory cell 18 when a plurality of inspection voltages V<SB>+S0</SB>to V<SB>+S4</SB>are successively applied to the ferroelectric memory cell 18 in a prescribed unit of voltage. When difference between output voltages outputted when a pair of inspection voltages V<SB>+Sn-1</SB>and V<SB>+Sn</SB>adjacent to each other on a time axis are applied is made to be a prescribed value or below, one inspection voltage (e.g. V<SB>+S3</SB>) of a pair of the inspection voltages is judged to be the inspection voltage corresponding to a saturation polarization point C' of the ferroelectric memory cell 18. The selection voltage Vs outputted from a voltage reducing circuit 110 reducing power source voltage Vdd is adjusted based on the inspection voltage corresponding to the saturation polarization point C'. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory device, a driving method thereof, and a driving circuit.
[0002]
[Background Art]
A ferroelectric memory device that has a ferroelectric capacitor as its storage element has the operating speed of a DRAM and is non-volatile like a flash memory, so it can replace conventional memory. It is expected as a functional memory device.
[0003]
As a ferroelectric memory device, an active type having a 1T / 1C cell in which one transistor and one capacitor (ferroelectric) are arranged in each cell, or a 2T / 2C cell in which a reference cell is further arranged for each cell. Ferroelectric memories are known. However, considering future high integration, the 1T / 1C cell and the 2T / 2C cell have a limit in the degree of integration, and a smaller memory element structure is required.
[0004]
Since the ferroelectric material itself has a memory holding function and can perform a memory operation with only the ferroelectric capacitor, as shown in Patent Documents 1 and 2, it is called a cross point type, and one ferroelectric material is used. A memory cell composed only of a capacitor (1C cell) has been proposed.
[0005]
[Patent Document 1]
JP-A-9-116107
[Patent Document 2]
JP 2001-515256 A
[0006]
[Problems to be solved by the invention]
However, in the cross-point type ferroelectric memory device, since an unnecessary voltage is applied when it is not selected, there is a problem of disturbing the data and eventually making it impossible to determine the storage state. Not reached.
[0007]
In the cross-point ferroelectric memory device, a so-called imprint phenomenon in which the hysteresis characteristic of the ferroelectric memory cell shifts to the positive voltage side or the negative voltage side is pointed out. However, no attempt has been made to apply an appropriate selection voltage to a ferroelectric memory cell in which an imprint phenomenon has occurred.
[0008]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a cross-point type ferroelectric memory device capable of preventing disturbance and the like and a method of adjusting a selection voltage thereof.
[0009]
[Means for Solving the Problems]
One embodiment of the present invention is to apply a selection voltage to at least one selected memory cell of a plurality of ferroelectric memory cells formed at each intersection of a plurality of word lines and a plurality of bit lines, The present invention relates to a method for adjusting a selection voltage of a ferroelectric memory device, which applies a non-selection voltage to a memory device. In this selection voltage adjusting method, first, a plurality of inspection voltages are sequentially applied to at least one ferroelectric memory cell at predetermined voltage intervals. When the plurality of test voltages are sequentially applied to the at least one ferroelectric memory cell, the test voltage is output via one of the word line and the bit line connected to the at least one ferroelectric memory cell. Voltage is detected. Thereafter, when the difference between the output voltages when a pair of test voltages adjacent to each other on the time axis is applied becomes equal to or less than a predetermined value, one of the pair of test voltages is changed to the saturation polarization of the ferroelectric memory cell. It is determined that the inspection voltage corresponds to a point. Finally, the selection voltage output from the step-down circuit for stepping down the power supply voltage is adjusted based on the inspection voltage corresponding to the saturation polarization point.
[0010]
According to the method of the present invention, it is possible to determine a selection voltage having an absolute value necessary to reach the saturation polarization point, but having a lower absolute value than the power supply voltage. This selection voltage can be generated by stepping down the power supply voltage by a step-down circuit. By lowering the selection voltage, the absolute value of the non-selection voltage applied to the non-selected memory cells also decreases, and the effect of the disturbance can be reduced.
[0011]
In addition, the capacity of a non-selected memory cell to which a relatively low non-selection voltage is applied (corresponding to a slope of a tangent in a hysteresis curve of the polarization value-applied voltage) can be reduced. Therefore, the total capacity of the many non-selected memories on the bit line connected to the selected memory (which becomes the parasitic capacity of the bit line) is also reduced, so that the power consumption is reduced and the charge / discharge of the bit line is performed at high speed. Be converted to Therefore, data can be read at high speed.
[0012]
In one aspect of the present invention, the test voltage applying step may include a step of performing each of the plurality of positive test voltages and the plurality of negative test voltages. In this case, the voltage detection step is performed when each of the plurality of positive test voltages and the plurality of negative test voltages is applied. Further, the determining step includes setting a positive test voltage corresponding to a positive saturation polarization point of the ferroelectric memory cell and a negative test voltage corresponding to a negative saturation polarization point of the ferroelectric memory cell, respectively. The step of determining is included. The selection voltage adjusting step is performed based on a test voltage having a larger absolute value among the positive and negative test voltages.
[0013]
If the hysteresis characteristic of the ferroelectric capacitor is unknown, it is unknown whether the characteristic is shifted to the positive voltage side or the negative voltage side (imprint phenomenon). In such a case, the adjustment method according to one embodiment of the present invention is performed using the positive and negative test voltages. In this case, of the positive and negative test voltages corresponding to the positive and negative saturation polarization points of the ferroelectric memory cell, the one having the larger absolute value is determined as the selection voltage. When the determined positive / negative selection voltage is applied to the ferroelectric memory cell, the saturation polarization point is reached on both the positive voltage side and the negative voltage side.
[0014]
In one embodiment of the present invention, the step-down circuit includes a voltage dividing circuit that divides the power supply voltage and outputs a plurality of step-down voltages, and a selection circuit that selects any one of the plurality of step-down voltages. Can be included. In this case, the selection voltage adjustment step performs adjustment so as to select a specific one from the plurality of step-down voltages from the selection circuit.
[0015]
In one embodiment of the present invention, the selection circuit can include a plurality of fuse elements. In this case, in the selection voltage adjusting step, at least one of the plurality of fuse elements may be cut by, for example, a laser beam.
[0016]
The adjustment method described above is not limited to the method for one ferroelectric memory cell. For example, the voltage detecting step includes simultaneously applying the test voltage to a plurality of ferroelectric memory cells arranged along at least one line, and a plurality of ferroelectric memory cells arranged along at least one line. Detecting an output voltage from the dielectric memory cell via one of the word line and the bit line.
[0017]
One embodiment of the present invention is a step of supplying a test mode signal to a test mode control pad provided in the ferroelectric memory device, and supplying at least one of the test mode signals in the ferroelectric memory device by supplying the test mode signal. And turning on a first switch between the word line and the first test pad, and a second switch between at least one bit line in the ferroelectric memory device and the second test pad. Turning on the switch. In this case, in the voltage detecting step, the inspection voltage is applied to the at least one ferroelectric memory cell via the first and second test pads, and the first and second test pads are The output voltage is detected via one of them.
[0018]
In one embodiment of the present invention, the target ferroelectric memory may be mounted on a wafer. Since this type of storage device is inspected in a wafer state before being cut into chips and packaged, the selection voltage can be adjusted following the wafer inspection.
[0019]
A ferroelectric memory device according to another aspect of the present invention includes a memory cell array including a plurality of ferroelectric memory cells formed at intersections of a plurality of word lines and a plurality of bit lines, and a power supply voltage step-down unit. A voltage step-down circuit that outputs a selection voltage, and a voltage control that generates a plurality of types of drive voltages including the selection voltage necessary for driving the plurality of ferroelectric memory cells based on the selection voltage from the step-down circuit. And a circuit. The step-down circuit may include a voltage dividing circuit that divides the power supply voltage and outputs a plurality of step-down voltages, and a selection circuit that selects any one of the step-down voltages.
[0020]
This ferroelectric memory device can adjust the selection voltage according to the adjustment method described above, and generate the selection voltage by the step-down circuit.
[0021]
A ferroelectric memory device according to another aspect of the present invention includes a test mode control pad to which a test mode signal is input, first and second test pads, and one end of at least one of the plurality of word lines. A first switch disposed between the first test pad and the first test pad, the first switch being turned on when the test mode signal is input to the test mode control pad; and one end of at least one of the plurality of bit lines A second switch disposed between the second test pad and the second test pad, the second switch being turned on when the test mode signal is input to the test mode control pad.
[0022]
With such a configuration, a test mode for adjusting the selection voltage can be started by inputting a test mode signal.
[0023]
A ferroelectric memory device according to another aspect of the present invention is arranged between at least one other end of the plurality of word lines and the voltage control circuit, and the test mode signal is supplied to the test mode control pad. A third switch that is turned off when the signal is input, and a third switch that is disposed between at least one other end of the plurality of bit lines and the voltage control circuit; and the test mode signal is input to the test mode control pad. And a fourth switch that is turned off when the switch is turned off.
[0024]
Thus, the above-described test mode can be performed in a state where the voltage control circuit and the like used during normal driving are separated from the memory cells.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[0026]
(Description of ferroelectric memory device)
FIG. 1 is a block diagram of an FeRAM which is a ferroelectric storage device according to an embodiment of the present invention, and FIG. 2 is a perspective view schematically showing a memory array thereof. As shown in FIG. 2, the memory cell array 10 includes a ferroelectric thin film 12, a plurality of word lines 14 arranged on one surface of the ferroelectric thin film 12, and an array arranged on the other surface of the ferroelectric thin film 12. And a plurality of bit lines 16.
[0027]
With the above structure, ferroelectric memory cells 18 are formed at the respective intersections (cross points) of the plurality of word lines 14 and the plurality of bit lines 16 as shown in FIG. Due to such a structure, the memory shown in FIG. 2 is called a cross-point FeRAM or a passive type FeRAM. Therefore, the memory shown in FIG. 2 has a 1T / 1C cell in which one transistor and one capacitor (ferroelectric) are arranged in each cell, or a 2T / 2C cell in which a reference cell is further arranged for each cell. Different from active memory.
[0028]
Since the FeRAM of this embodiment does not require a transistor in the memory cell array 10, high integration is possible and the structure of FIG. 2 can be stacked in multiple stages. The drive circuit board on which the CMOS logic is mounted can be arranged, for example, below the structure of FIG.
[0029]
The ferroelectric used in the present embodiment is preferably SBT (strontium-bismuth-tantalium), PZT (lead-zirconium-titanium), BLT (bismuth-lanthanum-titanium) or an inorganic material which is an oxide of these. However, other inorganic materials or organic materials may be used.
[0030]
The electrode material used to form the word line 14 and the bit line 16 used in the present embodiment is platinum (Pt), iridium (Ir), iridium oxide (IrO 2), strontium— Ruthenium or its oxide can be suitably used, but other conductive materials may be used.
[0031]
As a driving circuit system of the memory cell array 10, a plurality of types of word line drivers 20 for driving a plurality of word lines 14, a bit line driver 22 for driving a plurality of bit lines 16, and word line and bit line drivers 10 and 22 are provided. And a power supply circuit 24 for supplying a drive voltage (for example, Vs, 2Vs / 3, Vs / 3, 0). The word line driver 20 is connected to one end (the left end in FIG. 1) of each of the plurality of word lines 14, and the bit line driver 22 is connected to each one end (the top end in FIG. 1) of the plurality of bit lines 16.
[0032]
The word line driver 20 includes a row direction address decoder, and supplies a potential to one address selected word line 14 and the remaining unselected word lines 14. Similarly, the bit line driver 22 includes a column-direction address decoder, and supplies a potential to at least one bit line 16 whose address has been selected and the remaining unselected bit lines 14.
[0033]
(General operation explanation)
Next, the operation of the FeRAM shown in FIG. 1 will be described. FIG. 3 shows a hysteresis characteristic represented by the voltage dependence of the spontaneous polarization P or the polarization charge Q (change in polarization P × capacitor area) of the memory cell 18 shown in FIG.
[0034]
In FIG. 3, for example, the direction in which the potential of the word line 14 is higher than the potential of the bit line 16 is plus (+). When the word line 14 and the bit line potentials are the same (including when the power supply is OFF at 0 V), the voltage applied to the memory cell 18 becomes 0 V. The ferroelectric capacitor at this time has two types of remanent polarization ± Pr (points A and D in FIG. 3). For example, by defining the remanent polarization Pr at point D in FIG. 3 as a memory state of “0” and the remanent polarization −Pr at point A of FIG. 3 as a memory state of “1”, a binary memory state can be obtained. it can.
[0035]
Here, points C and F in FIG. 3 are the saturation polarization points of the ferroelectric memory cell 18, respectively. Points B and E in FIG. 3 are points where the polarization directions are reversed. A voltage at which the polarization value is 0 as in the point B or the point E is called a coercive voltage.
[0036]
According to the hysteresis characteristic of FIG. 3, when writing data "0", a voltage Vs (generally, Vs = positive power supply voltage Vdd) is applied to the ferroelectric memory cell 18 and after shifting to the point C in FIG. Alternatively, the voltage applied to the ferroelectric memory cell 18 may be set to 0 V and the process may be shifted to the point D. Conversely, when writing data “1”, a voltage −Vs is applied to the ferroelectric memory cell 18, and after shifting to the point F in FIG. 3, the applied voltage to the ferroelectric memory cell 18 is set to 0V. It is sufficient to shift to A.
[0037]
Data reading is performed by applying the voltage + Vs to the ferroelectric memory cell 18 in the polarization state at the point A or the point D. Regardless of whether the remanent polarization in the selected cell 18a is point A or point D in FIG. 3, the polarization state at point C in FIG. 3 is obtained by the above-described read operation. At this time, when shifting from point A to point C (when reading the memory state “1”), the polarization direction is reversed from negative to positive beyond point B where the polarization value becomes 0. Therefore, a current corresponding to the relatively large charge amount Q1 shown in FIG. On the other hand, when shifting from the point D to the point C (when reading the memory state “0”), the polarization direction does not reverse. Therefore, a current corresponding to the relatively small charge amount Q2 shown in FIG. Therefore, by comparing the current flowing through the bit line 16 with a reference current (not shown), it can be determined whether the memory state is “1” or “0”. After all, reading data is the same as writing data “0”.
[0038]
Here, the operation of reading data “1” is the same as the operation of writing data “0” as described above, so that data “1” is destroyed. This is a phenomenon called so-called destructive reading.
[0039]
Therefore, after reading the data “1”, a rewriting operation of the data “1” is required. The operation of rewriting data “1” is the same as the operation of writing data “1” described above, and it suffices to apply −Vs to the ferroelectric memory cell 18.
[0040]
Thus, it can be seen that data writing requires writing “0” and writing “1”, and data reading also requires writing “0” (read) and writing “1” (rewrite).
[0041]
Next, the setting of the potential of the word line 14 and the bit line 16 will be described by taking data reading as an example. This potential setting is performed by the word line driver 20 and the bit line driver 22 that have been supplied with four types of potentials (Vs, 2Vs / 3, Vs / 3, 0) from the power supply circuit 24. Note that the potential Vs, 0 is two kinds of selection potentials, and the potentials 2Vs / 3, Vs / 3 are two kinds of non-selection potentials.
[0042]
FIG. 4 shows one selected cell 18a and another unselected cell 18b. The word line 14 connected to the selected cell 18a located at the address (2, 2) is set to the potential Vs (word selection potential), and the bit line 16 is set to the potential 0 (bit selection potential). Therefore, a positive electric field of Vs-0 = Vs is applied to the selected cell 18a. Therefore, regardless of whether the residual polarization in the selected cell 18a is point A or point D in FIG. 3, the polarization state at point C in FIG. 3 is obtained by the above-described read operation. Therefore, by detecting the current of the bit line 16 connected to the selected cell 18a, it is possible to determine whether the memory state is "1" or "0" as described above.
[0043]
Setting the polarization state at point C in FIG. 3 is the same as the operation of writing data “0”. Therefore, when writing data "0", the potential may be set as shown in FIG.
[0044]
Further, an actual data read operation is simultaneously performed on a plurality of memory cells 18 on one word line 14, and a group of data such as 8 bits or 16 bits is simultaneously read.
[0045]
(Explanation of the disturb phenomenon)
At the time of data reading, all the word lines 14 connected to the non-selected cells 18b shown in FIG. 4 are at the potential Vs / 3 (word non-selection potential), and all the bit lines 16 connected to the non-selected cells 18b are at the potential Vs / 3. It is set to 2Vs / 3 (bit non-selection potential). At this time, the voltage applied to the non-selected cells 18b is ± Vs / 3. As a result, the non-selected cell 18b in the polarization state at the point A moves to one of the points H and I in FIG. Even if the point shifts from the point A to the point I, it does not exceed the inversion point B, so that the stored data is not inverted. In addition, the non-selected cell 18b in the polarization state at the point D shifts to one of the points G and J in FIG. In this case as well, even if the transition from the point D to the point G does not exceed the reversal point E, the stored data is not reversed.
[0046]
However, if a non-selection voltage is repeatedly applied to the non-selected cells every time, for example, in the read operation mode, data will be degraded depending on the direction of the electric field. This will be described with reference to FIG.
[0047]
FIG. 5 shows that an unselected memory cell in the polarization state at the point D is placed in the direction of the electric field for reversing the polarization state (the direction of the electric field moving to the point E side in the direction of the minus electric field) every time the operation mode of the other selected cell is changed. , 10 ⁿ The case where the non-selection voltage −Vs / 3 is repeatedly applied in the order is shown. Similarly, in the non-selected memory cell in the polarization state at the point A, the electric field direction for inverting the polarization state (the electric field direction shifting to the point B side plus the positive electric field direction) is set to 10 in each operation mode of the other selected cells. ⁿ The case where the non-selection voltage Vs / 3 is repeatedly applied in the order is shown.
[0048]
In each case, the number of repetitions was 10 ⁿ When the exponent n becomes large, the absolute value of the remanent polarization Pr or -Pr becomes small. In such a case, a sufficient polarization charge margin is not generated at the time of data reading, and reading becomes impossible.
[0049]
(Use of proper selection voltage Vs generated by stepping down power supply voltage)
In the present embodiment, the voltage Vs is adjusted to reduce the above-described disturb phenomenon. FIG. 6 simplifies this solution principle. As described with reference to FIG. 3, generally, the voltage applied to the ferroelectric memory cell 18 at the time of "0" writing is the positive power supply voltage Vdd, and the voltage applied to the ferroelectric capacitor 18 at the time of "1" writing. Is the negative power supply voltage -Vdd.
[0050]
When the power supply voltage Vdd is applied to the ferroelectric memory cell 18, the power supply voltage Vdd moves to the saturation polarization point C. As is apparent from FIG. 6, even at the voltage Vs having an absolute value lower than the positive power supply voltage Vdd, the saturation polarization point C ′ is reached. Has reached. Similarly, the polarization saturation point F 'is reached even at -Vs, whose absolute value is lower than the negative power supply voltage -Vdd.
[0051]
Then, the power supply voltage Vdd is stepped down to generate the voltage Vs, and the positive voltage Vs is set to the “0” write voltage, the negative voltage −Vs is set to the “1” write voltage, and the positive and negative voltages + Vs and −Vs are selected voltages. Used as
[0052]
Then, a non-selection voltage ± Vs / 3 is applied to the non-selected memory cells. The absolute value of the non-selection voltage ± Vs / 3 is smaller than the absolute value of the non-selection ± Vdd / 3 applied to the non-selected memory cells when the power supply voltage Vdd is used as the selection voltage.
[0053]
As a result, the polarization value of the non-selected memory cell shown in FIG. 6 is higher when the non-selection voltage ± Vs / 3 is applied than when the non-selection voltage ± Vdd / 3 is applied. (Point B). Thus, the influence of the disturb phenomenon shown in FIG. 5 can be reduced.
[0054]
Here, the slope of the tangent to the polarization value of the unselected memory cell is equivalent to the capacitance of the unselected memory cell. As shown in an enlarged manner in FIG. 6, the inclination of the tangent line S1 at the polarization point of the non-selected memory cell to which the non-selection voltage Vs / 3 is applied is the slope of the non-selected memory cell to which the non-selection voltage Vdd / 3 is applied. It is clearly smaller than the slope of the tangent S2 at the polarization point. Therefore, the capacitance C1 of the non-selected memory cell to which the non-selection voltage Vs / 3 is applied is smaller than the capacitance C2 of the non-selected memory cell to which the non-selection voltage Vdd / 3 is applied. The same can be said for the negative voltage side.
[0055]
The smaller capacity of the non-selected memory cells is suitable for high-speed reading, and the power consumption can be reduced. This is because the capacitance of a large number of non-selected memory cells on the same bit line as the selected memory cell becomes a parasitic capacitance of the bit line and slows down the voltage change of the bit line. Further, since electric charges are charged to the capacitances of a large number of unselected memory cells on the same bit line as the selected memory cell, power consumption also increases.
[0056]
By using the voltage Vs obtained by stepping down the power supply voltage Vdd as in the present embodiment, high-speed reading and low power consumption can be achieved in addition to disturb measures.
[0057]
(Method of detecting proper selection voltage Vs)
7 to 9 are flowcharts for detecting an appropriate selection voltage Vs. The flowchart of FIG. 7 illustrates the candidate selection voltage V corresponding to the positive saturation polarization point C ′ shown in FIG. _{+ S} FIG. 4 shows steps for detecting. The flowchart of FIG. 8 illustrates the candidate selection voltage V corresponding to the negative saturation polarization point F ′ shown in FIG. _-S FIG. 4 shows steps for detecting. The flowchart of FIG. 9 shows the candidate selection voltage V obtained by the flowcharts of FIGS. _{+ S} , V _-S Is determined as the selection voltage Vs, and the shift voltage Vs _shift = Vdd-Vs. In the following description, the candidate selection voltage V _{+ S} , V _-S Is assumed to be smaller than the power supply voltage Vdd. This is because the present embodiment generates the selection voltage Vs by stepping down the power supply voltage Vdd.
[0058]
First, the initial inspection voltage V shown in FIG. _{+ Sn} (N = 0: V _{+ S0} ) Is applied to the ferroelectric memory cell 18 (step 1 in FIG. 7), and the output voltage V based on the polarization value in the ferroelectric memory cell 18 at that time is applied. ₀ Is detected (step 2 in FIG. 7). Next, n = n + 1 (= 1), and the second inspection voltage V shown in FIG. _{+ Sn} = V _{-S (n-1)} + N · ΔV = V _{+ S0} + ΔV is applied to the ferroelectric memory cell 18 (Step 3 in FIG. 7). Output voltage V at this time ₁ Is detected (step 4 in FIG. 7).
[0059]
Next, the absolute value | V of the difference between the two output voltages _n-1 -V _n | = | V ₀ -V ₁ Is within the range of a predetermined value A (corresponding to a minute voltage change amount per ΔV after reaching the saturation polarization point C ′) (step 5 in FIG. 7). According to FIG. 10, the inspection voltage V _{+ S1} Then, since the saturation polarization point C 'has not been reached, the determination in step 5 is NO. Therefore, thereafter, steps 3 to 5 in FIG. 7 are repeated.
[0060]
Here, when n = 4 is reached in step 3 of FIG. 7, the determination in subsequent step 5 turns to YES. This is because the inspection voltage V in FIG. _{+ S3} The saturation polarization point C 'was reached at _{+ S3} And inspection voltage V _{+ S4} The absolute value of the difference between the output voltages when ₄ -V ₃ Is in the range of the predetermined value A.
[0061]
By the above procedure, the inspection voltage V _{+ Sn-1} = V _{+ S3} Is the candidate selection voltage V on the positive voltage side. _{+ S} (Step 6 in FIG. 7). In FIG. 7, the last applied inspection voltage V _{+ S4} Inspection voltage V just before _{+ S3} Was determined to be the inspection voltage after reaching the saturation polarization point C ′. In addition to the above, the inspection voltage V applied last is expected in consideration of the safety factor. _{+ S4} May be used as the positive voltage side candidate selection voltage. That is, one of the pair of inspection voltages for which the determination in step 5 is YES is set to the positive voltage side candidate selection voltage V _{+ S} Should be determined.
[0062]
The above operation is performed by changing the inspection voltage to a negative voltage. This operation is shown in FIG. 8 and FIG. FIGS. 8 and 11 are substantially the same as the operations of FIGS. 7 and 10 except that the positive and negative voltages are different. By the detection operation using the negative test voltage, in step 6 of FIG. 8, as shown in FIG. _-S4 To the negative candidate selection voltage V _−s To be determined.
[0063]
After the operation according to the flowcharts of FIGS. 7 and 8 is completed, the process proceeds to the operation of the flowchart of FIG. As shown in the flowchart of FIG. 9, the positive candidate selection voltage V _{+ S} And the negative candidate selection voltage V _-S (Step 1 in FIG. 9), and the larger absolute value is determined as the selection voltage Vs (Steps 2 and 3 in FIG. 9).
[0064]
If the smaller one of the absolute values of the two candidate selection voltages is determined as the selection voltage Vs, when the positive selection voltage + Vs and the negative selection voltage -Vs are applied to the ferroelectric memory cell 18, either of them is determined. This is because one of them may not reach the saturation polarization point.
[0065]
In the examples of FIGS. 10 and 11, the negative candidate selection voltage V _-S4 Is the positive candidate selection voltage V _{+ S3} , The selection voltage Vs = | V _-S4 | Is determined.
[0066]
In other words, as in the examples of FIGS. 10 and 11, the case where the absolute value of the candidate selection voltage corresponding to the negative saturation polarization point is larger than the absolute value of the candidate selection voltage corresponding to the positive saturation polarization point It can be considered that the hysteresis characteristic of the ferroelectric memory cell 18 is shifted to the negative voltage side. In the ferroelectric memory cell 18 exhibiting the hysteresis characteristic shifted to the negative voltage side, the negative candidate selection voltage V _−s Can be determined as the selection voltage Vs. In this case, the operation in the flowchart in FIG. 7 and the step 1 in FIG. 9 can be omitted, and the process can be shifted from step 6 in FIG. 8 to step 3 in FIG.
[0067]
Conversely, in the ferroelectric memory cell 18 exhibiting the hysteresis characteristic shifted to the positive voltage side, the positive candidate selection voltage V _{+ S} Can be determined as the selection voltage Vs. In this case, the operation in the flowchart in FIG. 8 and the step 1 in FIG. 9 can be omitted, and the process can shift from step 6 in FIG. 7 to step 3 in FIG.
[0068]
Incidentally, such a shift of the hysteresis characteristic to the positive voltage side or the negative voltage side is known as an imprint phenomenon of the ferroelectric memory device. The imprint phenomenon may occur later when the applied voltage is biased toward the positive voltage side or the negative voltage side, or may occur earlier due to a material forming the ferroelectric.
[0069]
The present embodiment can be suitably applied to the determination of the selection voltage Vs in a ferroelectric memory device exhibiting a proactive imprint phenomenon caused by a material or the like. In particular, if the shift direction is known in advance, the operation step using one of the positive and negative test voltages in FIGS. 7 to 9 can be omitted.
[0070]
(Adjustment method of appropriate selection voltage Vs)
FIG. 12 is a block diagram of a ferroelectric memory device 100 before shipment and an adjusting device 200 for adjusting the selection voltage Vs. Note that the ferroelectric memory device shown in FIG. 12 can be preferably used in a wafer state. This kind of wafer is inspected by an inspection apparatus before being cut into individual chips and packaged. Therefore, it is preferable that the following adjustment method is performed on a non-defective product after the inspection is completed, or on a product after the defective circuit is switched to the redundant circuit in the wafer inspection apparatus.
[0071]
12, a ferroelectric memory device 100 to be inspected has a voltage step-down circuit 110 and a voltage control circuit 120 in addition to the memory cell array 10 shown in FIG. Step-down circuit 110 steps down power supply voltage Vdd and outputs selection voltage Vs. The voltage control circuit 120 generates a plurality of drive voltages (for example, Vs, 2Vs / 3, Vs / 3, 0) necessary for driving the ferroelectric memory cell 18 based on the selection voltage Vs from the step-down circuit 110. I do.
[0072]
As shown in FIG. 13, the step-down circuit 110 includes a voltage dividing circuit 112 that divides the power supply voltage Vdd and outputs a plurality of step-down voltages, and a selection circuit 114 that selects any one of the step-down voltages. Can be included.
[0073]
As shown in FIG. 13, the voltage dividing circuit 112 has a plurality of divided resistors r1, r2,... Rn connected in series between the terminal of the power supply voltage Vdd and the terminal of the ground voltage.
[0074]
The selection circuit 114 has a fuse element 116, first and second inverters 118 and 120, an N-type transistor 122, and a P-type transistor 124 corresponding to each of the divided resistors. When the fuse element 116 connected to the terminal of the power supply voltage Vdd is conductive, the output of the first inverter 118 becomes LOW, and the N-type transistor 122 is kept off. The output of the second inverter 120 becomes HIGH, and the P-type transistor 124 is also kept off.
[0075]
On the other hand, when the fuse element 116 is cut, the output of the first inverter 118 becomes HIGH, and the N-type transistor 122 is turned on. The output of the second inverter 120 becomes LOW, and the P-type transistor 124 is also turned on. When at least one P-type transistor 124 is turned on, a voltage is output from the selection circuit 114. Here, among the fuse elements 116 among the n pieces, the i-th fuse element 116 counted from the Vdd terminal side is cut off, so that the selection circuit 114 outputs Vs = [n− (i−1) as the selection voltage Vs. )] × Vdd / n.
[0076]
For example, when the fuse element 16 (Fuse1) at the top of FIG. 13 is cut, Vs = Vdd, and when the second fuse element 16 (Fuse2) is cut, Vs = (n-1). × Vdd / n,... When the nth (lowest stage) fuse element 16 (Fusen) is cut, Vs = Vdd / n.
[0077]
The ferroelectric memory device 100 further includes a test mode control pad 130 to which a test mode signal is input, and first and second test pads 132 and 134. Further, the ferroelectric memory device 100 includes a first switch (for example, an N-type transistor) 136 disposed between one end of, for example, one of the plurality of word lines 14 and the first test pad 132. And a second switch (for example, an N-type transistor) 138 disposed between one end of, for example, one of the plurality of bit lines 16 and the second test pad 134. These first and second switches 136 and 138 are turned on when a test mode signal (HIGH active) is input to the test mode control pad 130.
[0078]
The ferroelectric memory device 100 further includes a third switch (for example, an N-type transistor) 140 disposed between the other end of the word line 14 having one end connected to the first switch 136 and the voltage control circuit 120. And a fourth switch (for example, an N-type transistor) 142 disposed between the other end of the bit line 16 having one end connected to the second switch 138 and the voltage control circuit 120. The third and fourth switches 140 and 142 are turned off when the test mode signal is input by receiving a test mode signal as a control signal via the inverter 144.
[0079]
On the other hand, the adjustment device 200 includes a tester 210, a shift voltage detection unit 220, a voltage shift control code generation unit 230, and a fuse cutting unit 240.
[0080]
The tester 210 is connected to the first and second test pads 132 and 134 of the ferroelectric memory device 100. The tester 210 outputs the test voltages shown in FIGS. 7 and 8 to the ferroelectric memory device 100, and receives the output voltage from the ferroelectric memory device 100. Tester 210 is programmed to perform at least the operations of steps 1-4 in FIG. 7 and / or steps 1-4 in FIG.
[0081]
The shift voltage detection unit 220 performs, for example, each of steps 5 and 6 in FIGS. 7 and 8 and all the steps in FIG. 9, and finally executes the shift voltage V _shift To determine.
[0082]
Voltage shift control code generator 230 generates a code signal indicating which one of n fuse elements 116 shown in FIG. 13 should be cut off based on the output from shift voltage detector 230. Fuse cutting section 240 blows fuse element 116 corresponding to the code signal by, for example, a laser beam.
[0083]
In such an adjusting device 200, by supplying a test mode signal to the ferroelectric memory device 100, the memory cell array 10 disconnected from the voltage control circuit 120 used during normal operation can be used to select a voltage lower than the power supply voltage Vdd. The voltage Vs can be set.
[0084]
In FIG. 12, the above operation is performed based on the output voltage from one ferroelectric memory cell 18, but the present invention is not limited to this. Although not shown in FIG. 12, an inspection voltage is simultaneously applied to a plurality of ferroelectric memory cells 18 of at least one row via a bit line driver 22 (see FIG. 1) for driving a plurality of bit lines 6. Output voltages from a plurality of ferroelectric memory cells 18 for one row may be detected. Similarly, if the word line driver 20 (see FIG. 1) is used, a plurality of ferroelectric memory cells 18 over a plurality of rows can be targeted.
[0085]
Note that the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a block diagram of a ferroelectric memory device according to an embodiment of the present invention.
FIG. 2 is a schematic perspective view of the memory cell array shown in FIG.
FIG. 3 is a hysteresis characteristic diagram of the ferroelectric memory cell shown in FIG.
FIG. 4 is a schematic explanatory diagram showing set potentials of a word line and a bit line when reading (writing data “0”) a ferroelectric memory cell array.
FIG. 5 is a characteristic diagram for explaining a disturbance phenomenon of a ferroelectric capacitor.
FIG. 6 is a hysteresis characteristic diagram of a ferroelectric memory cell for explaining the necessity of adjusting a selection voltage.
FIG. 7 is a first flowchart of a selection voltage adjusting method according to an embodiment of the present invention.
FIG. 8 is a second flowchart of a selection voltage adjusting method.
FIG. 9 is a third flowchart of a selection voltage adjusting method.
FIG. 10 is a diagram illustrating a positive test voltage detected in the flowchart of FIG. 7;
FIG. 11 is a diagram illustrating a negative test voltage detected in the flowchart of FIG. 8;
FIG. 12 shows a ferroelectric memory device and a selection voltage adjusting device thereof according to an embodiment of the present invention.
FIG. 13 is a circuit diagram of the step-down circuit shown in FIG.
[Explanation of symbols]
10 memory cell array, 12 ferroelectrics, 14 word lines, 16 bit lines, 18 ferroelectric memory cells, 18a selected cells, 18b unselected cells, 20 word line drivers, 22 bit line drivers, 24 power supply circuits, 100 ferroelectrics Body memory device, 110 step-down circuit, 112 voltage division circuit, 114 selection circuit, 116 fuse element, 118 first inverter, 120 second inverter, 122 N-type transistor, 124 P-type transistor, 130 test mode control pad, 132 First test pad, 134 second test pad, 136 first switch, 138 second switch, 140 third switch, 142 fourth switch, 144 inverter, 200 selection voltage regulator, 210 tester , 220 shift voltage detector, 230 voltage shift control Code generator, 240 fuse cutting device

Claims (12)

A selection voltage is applied to at least one selected memory cell of a plurality of ferroelectric memory cells formed at intersections of a plurality of word lines and a plurality of bit lines, and a non-selection voltage is applied to other unselected memory cells. A method for adjusting a selection voltage of a ferroelectric memory device,
A step of sequentially applying a plurality of test voltages at predetermined voltage steps to at least one ferroelectric memory cell;
When the plurality of test voltages are sequentially applied to the at least one ferroelectric memory cell, the test voltage is output via one of the word line and the bit line connected to the at least one ferroelectric memory cell. Detecting each of the voltages
When a difference between respective output voltages when a pair of test voltages adjacent to each other on the time axis is applied is equal to or less than a predetermined value, one of the pair of test voltages is set to a saturation polarization point of the ferroelectric memory cell. Determining the corresponding test voltage;
A step of adjusting the selection voltage output from a step-down circuit that steps down a power supply voltage based on a test voltage corresponding to the saturation polarization point;
A method for adjusting a selection voltage of a ferroelectric memory device, comprising: In claim 1,
The test voltage applying step includes a step of performing each of a plurality of positive test voltages and a plurality of negative test voltages,
The voltage detecting step is performed for each of the plurality of positive test voltages and the plurality of negative test voltages when applied,
The determining step determines a positive test voltage corresponding to a positive saturation polarization point of the ferroelectric memory cell and a negative test voltage corresponding to a negative saturation polarization point of the ferroelectric memory cell. Process
The method for adjusting a selection voltage of a ferroelectric memory device according to claim 1, wherein the selection voltage adjusting step is performed based on an inspection voltage having a larger absolute value among the positive and negative inspection voltages. In claim 1 or 2,
The step-down circuit includes a voltage division circuit that divides the power supply voltage and outputs a plurality of step-down voltages, and a selection circuit that selects any one of the plurality of step-down voltages,
The method for adjusting a selection voltage of a ferroelectric memory device according to claim 1, wherein the selection voltage adjusting step includes a step of adjusting a selected one of the plurality of step-down voltages from the selection circuit. In claim 3,
The selection circuit includes a plurality of fuse elements,
The method of adjusting a selection voltage of a ferroelectric memory device according to claim 1, wherein the selecting voltage adjusting step includes a step of cutting at least one of the plurality of fuse elements. In any one of claims 1 to 4,
The voltage detecting step includes simultaneously applying the inspection voltage to a plurality of ferroelectric memory cells arranged along at least one line; and a plurality of ferroelectrics arranged along the at least one line. Detecting the output voltage from the memory cell via one of the word line and the bit line. In any one of claims 1 to 5,
Supplying a test mode signal to a test mode control pad provided in the ferroelectric memory device;
By supplying the test mode signal, a first switch between at least one word line in the ferroelectric memory device and a first test pad is turned on, and at least a first switch in the ferroelectric memory device is turned on. Turning on a second switch between one bit line and a second test pad;
Further comprising
In the voltage detecting step, the test voltage is applied to the at least one ferroelectric memory cell via the first and second test pads, and one of the first and second test pads is applied. Detecting the output voltage via the control circuit. In any one of claims 1 to 6,
A selection voltage adjustment method for a ferroelectric memory device, wherein the selection voltage is adjusted in a state where the ferroelectric memory is mounted on a wafer. In claim 7,
A method for adjusting a selection voltage of a ferroelectric memory device, wherein the selection voltage is adjusted after the inspection of the ferroelectric memory device mounted on the wafer is completed. A memory cell array including a plurality of ferroelectric memory cells formed at each intersection of a plurality of word lines and a plurality of bit lines;
A step-down circuit that steps down the power supply voltage and outputs a selection voltage;
A voltage control circuit that generates a plurality of types of drive voltages including the select voltage necessary for driving the plurality of ferroelectric memory cells based on the select voltage from the step-down circuit;
Has,
The step-down circuit includes a voltage dividing circuit that divides the power supply voltage and outputs a plurality of step-down voltages, and a selecting circuit that selects any one of the step-down voltages. Dielectric storage device. In claim 9,
The ferroelectric memory device, wherein the selection circuit includes a plurality of fuse elements, and at least one of the plurality of fuse elements is cut. In claim 9 or 10,
A test mode control pad to which a test mode signal is input;
First and second test pads;
A first switch disposed between at least one end of the plurality of word lines and the first test pad, and turned on when the test mode signal is input to the test mode control pad;
A second switch disposed between one end of at least one of the plurality of bit lines and the second test pad and turned on when the test mode signal is input to the test mode control pad;
A ferroelectric memory device further comprising: In claim 11,
The first switch is disposed between the other end of the at least one word line to which the first switch is connected and the voltage control circuit, and is turned off when the test mode signal is input to the test mode control pad. 3 switches,
The second switch is disposed between the other end of the at least one bit line to which the at least one bit line is connected and the voltage control circuit, and is turned off when the test mode signal is input to the test mode control pad. 4 switches,
A ferroelectric memory device further comprising:

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