JP2004303262A5 - - Google Patents
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- JP2004303262A5 JP2004303262A5 JP2004141722A JP2004141722A JP2004303262A5 JP 2004303262 A5 JP2004303262 A5 JP 2004303262A5 JP 2004141722 A JP2004141722 A JP 2004141722A JP 2004141722 A JP2004141722 A JP 2004141722A JP 2004303262 A5 JP2004303262 A5 JP 2004303262A5
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- input
- inverter
- integrated circuit
- gate capacitance
- signal terminal
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Claims (2)
上記ニューロンＭＯＳインバータを用いた、ｋ入力変数の任意の論理関数を実現する２段論理の論理関数機能再構成可能な集積回路であって、
上記論理関数機能再構成可能な集積回路の１段目に、（３／４）・２ ｋ 個の上記ニューロンＭＯＳトランジスタであるプリインバータ回路を具備し、
上記論理関数機能再構成可能な集積回路の２段目に、上記ニューロンＭＯＳトランジスタであるメインインバータを具備し、
上記プリインバータは、入力ベクトルを識別可能なように設定された入力ゲート容量値の入力ゲート容量を有し、
当該プリインバータのうち少なくとも１つは、３つ以上の閾値から１つを選択する第２の入力信号端子を有し、
上記メインインバータは、
入力ベクトルを識別可能なように設定された入力ゲート容量値の入力ゲート容量と、
入力ベクトルに対応する入力電荷量を小さい順に並べ、当該並べられた順に連続する４つの入力電荷量に対応する４つの入力ベクトルを１つのブロックとしたとき、各ブロック内の４つの入力ベクトルに対して、３つの上記プリインバータの出力信号の論理的組み合わせによってフローティングゲート閾値電位に対して大小異なる２つの値を取るように設定された、プリインバータの出力端子に接続された端子とフローティングゲートとの間の入力ゲート容量値の入力ゲート容量と、
を有することを特徴とする論理関数機能再構成可能な集積回路。 Neuron MOS transistor Tama other two inverter circuits using neuron MOS transistors with switch Yuron MOS inverter and call butoxy,
A two-stage logic function reconfigurable integrated circuit that realizes an arbitrary logic function of k input variables using the neuron MOS inverter,
(3/4) · 2 k pre-inverter circuits which are neuron MOS transistors are provided in the first stage of the logic function reconfigurable integrated circuit ,
The second stage of the logic circuit reconfigurable integrated circuit has a main inverter which is the neuron MOS transistor,
The pre-inverter has an input gate capacitance of an input gate capacitance value set so that an input vector can be identified,
At least one of the pre-inverters has a second input signal terminal for selecting one from three or more threshold values,
The main inverter is
The input gate capacitance of the input gate capacitance value set so that the input vector can be identified, and
When the input charge amounts corresponding to the input vectors are arranged in ascending order and the four input vectors corresponding to the four input charge amounts that are consecutive in the arranged order are taken as one block, the four input vectors in each block Between the terminal connected to the output terminal of the pre-inverter and the floating gate, which are set to take two values that are different in magnitude from the floating gate threshold potential by a logical combination of the output signals of the three pre-inverters. Input gate capacitance value between the input gate capacitance value,
A logic function function reconfigurable integrated circuit comprising:
上記３つ以上の閾値から１つを選択する第２の入力信号端子は、複数の第２の入力信号で表現される２値よりも多い多値表現によって制御する入力信号端子であるか、または、１つの第２の入力信号端子に多値電位を与えることによって制御する入力信号端子であることを特徴とする論理関数機能再構成可能な集積回路。The second input signal terminal that selects one of the three or more threshold values is an input signal terminal that is controlled by a multi-value expression that is more than two values expressed by a plurality of second input signals, or A logic function reconfigurable integrated circuit, wherein the integrated circuit is an input signal terminal controlled by applying a multilevel potential to one second input signal terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004141722A JP4475571B2 (en) | 2004-05-11 | 2004-05-11 | Logic function function reconfigurable integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004141722A JP4475571B2 (en) | 2004-05-11 | 2004-05-11 | Logic function function reconfigurable integrated circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000080022A Division JP3565495B2 (en) | 2000-01-07 | 2000-03-22 | Logic function reconfigurable integrated circuit and design method thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004303262A JP2004303262A (en) | 2004-10-28 |
| JP2004303262A5 true JP2004303262A5 (en) | 2006-05-11 |
| JP4475571B2 JP4475571B2 (en) | 2010-06-09 |
Family
ID=33411250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004141722A Expired - Fee Related JP4475571B2 (en) | 2004-05-11 | 2004-05-11 | Logic function function reconfigurable integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4475571B2 (en) |
-
2004
- 2004-05-11 JP JP2004141722A patent/JP4475571B2/en not_active Expired - Fee Related
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