JP4475571B2 - Logic function function reconfigurable integrated circuit - Google Patents

Description

The present invention relates to a circuit composed of elements that realize threshold logic and the design thereof, and particularly to an integrated circuit having neuron MOS transistors that can easily implement threshold logic. The present invention relates to an integrated circuit design method for realizing a function function and an integrated circuit having a logic function function.

  Research and development of Reconfigurable Computing System (RCS) using reconfigurable devices represented by FPGA (Field Programmable Gate Array) that can rewrite logic functions after device manufacture Yes. The said reconfigurable computing system (RCS) is (for example, refer nonpatent literature 1).

  In various RCSs in which research and development are progressing, device parts that enable reconfiguration of logic functions are reconfigurable devices such as FPGAs and memory circuits. Regarding the basic structure of these reconfigurable devices, Various proposals have been made.

  Conventionally, reconfigurable devices have been mainly used as a substitute for ASICs that require product prototyping and high-mix low-volume production. In this method of use, it is sufficient to configure necessary functions before or after being incorporated into the system. As basic devices in the variable logic part of the reconfigurable device that answers this requirement, there are mainly the following devices.

  FIG. 21 is a diagram showing a configuration of a conventional LUT (Look-Up Table) type variable logic unit.

  The first example is a LUT (Look-Up Table) type that directly implements the truth table shown in FIG. 21, and associates an input vector, which is a combination of input variables of a logical function, with an address of a memory circuit. This is an example in which a value held in a circuit is used as an output value. As the memory circuit, SRAM (Static RAM) is mainly used.

  FIG. 22 is a diagram showing the configuration of a conventional multiplexer (MUX) type variable logic unit.

  As shown in FIG. 22, the second example is a multiplexer (MUX, Multiplexer) type that implements a logical expression by Shannon expansion.

  In the second example, a logical variable is associated with a control input of a multiplexer, and a logical function is realized based on Shannon expansion. Generally, it is composed of a multi-stage connection of multiplexers. In order to suppress the signal propagation delay time that increases due to the multi-stage connection, this is realized by connecting / disconnecting wiring by anti-fusing, which has a low resistance. However, there is a feature that it is difficult to change the logical function after the connection by anti-feed once.

  FIG. 23 is a diagram illustrating a configuration of a PLA type variable logic unit.

  As shown in FIG. 23, the third example is a PLA (Programmable Logic Array) type that expresses a logical function in an AND-OR logical sum form or the like.

  In the third example, logic variability is realized by connecting or disconnecting a variable input line and a product term line by EPROM or EEPROM. In general, it is configured by a programmable AND plane that performs multi-variable wired AND and an OR plane in which product term lines and output lines are fixedly connected. Data writing to the EPROM is performed by avalanche injection of high energy electrons, and erasure is performed by ultraviolet rays. Further, writing and erasing to the EEPROM are performed with a tunnel current having a small current amount. Because of this feature, the time required to reconfigure the logic function in any data retention device is very long compared to using other storage devices or circuits.

  Among these devices, the condition that the time required for reconfiguring the logic function, which is one of the conditions for further improving the RCS function, satisfies the condition that the rewriting speed like the SRAM shown in the first example is satisfied. This is a LUT type using a fast memory circuit or a latch circuit or a circuit such as a DRAM other than an SRAM.

  Typical examples of reconfigurable devices using the feature of high-speed rewriting include DPGA (Dynamically Programmable Gate Array) and DRLE (Dynamically Reconfigurable Logic Engine) in which the LUT, which is a variable logic unit, is configured by a latch circuit. is there.

  The DPGA is already known (for example, see Non-Patent Document 2). The DRLE is also already known (for example, see Non-Patent Document 3).

However, since the LUT type variable logic unit has a truth table directly mounted on the circuit, even when only a logic function having a certain special property is used, a variable logic unit expressing all the logic functions is provided. 2 ^k memory cells are required as a mounting circuit in the variable logic part of the k input variable. Therefore, the LUT type variable logic unit has a problem of high area cost.

  As a means for solving this problem, a circuit that realizes only a symmetric function that is frequently used in arithmetic operations executed in a calculation unit (or data path unit) of a logic LSI and a control unit are frequently used. A method is conceivable in which the selector circuit and a circuit that realizes all the logical functions in a sense that complements the functions of the two circuits are implemented at a low area cost and combined.

  Thus, combining a plurality of basic functions to form a basic unit of a reconfigurable device is comparable to that a basic unit is composed of a plurality of LUTs in a conventional reconfigurable device. In general, the basic unit of the variable logic part of an actual reconfigurable device is configured in this way.

  In addition, a method has been proposed in which devices having different characteristics such as LUT type and PLA type are combined to form a basic unit of one variable logic unit (for example, see Non-Patent Document 4).

  However, it is difficult for a conventional reconfigurable device to realize only a function function having special properties.

  On the other hand, a symmetric function function is realized by a neuron MOS circuit composed of neuron MOS transistors that can easily implement threshold logic, which is a reconfigurable device with a different logic changing principle from the conventional reconfigurable device. (For example, refer nonpatent literature 5).

  FIG. 24 is a diagram showing the structure of a CMOS inverter using a conventional neuron MOS transistor. FIG. 24 (1) is a layout diagram, and FIG. 24 (2) is an X-type shown in FIG. 24 (1). FIG. 24 (3) is a circuit diagram of an n-input complementary neuron MOS inverter (abbreviated as neuron MOS inverter).

  Here, as shown in FIG. 24, the “neuron MOS transistor” has a floating gate on a region that separates the source region and the drain region of the MOS transistor and has a capacitive coupling with the floating gate. This is a transistor having an input gate.

  This neuron MOS transistor is already known (for example, see Non-Patent Document 6).

  FIG. 25 is a circuit diagram of a CMOS type inverter (neuron MOS inverter) using a conventional neuron MOS transistor. FIG. 25 (1) is a diagram described by transistor symbols, and FIG. 25 (2) is a logic symbol. FIG.

  Next, taking the neuron MOS inverter shown in FIG. 25 as an example, the inverter operation will be specifically described.

The signal potential input from each of the n input terminals is V _i , the value of the input gate capacitance between each input terminal and the floating gate is C _i , the source, drain, and substrate of the floating gate, NMOSFET, and PMOSFET ( When the sum of the capacitance values between the terminal and the well terminal is ΣC _nmos + ΣC _pmos , the following equation (1)

が成り立つと、各入力ゲート容量に蓄積する電荷量の総和Ｑ_ｆは、

When the above holds, the total amount Q _{f of} charge accumulated in each input gate capacitance is

であり、フローティングゲート電位Ｖ_ｆｇは、各入力ゲート容量に蓄積する電荷量の総和Ｑ_ｆにほぼ比例し、次の式（２）で表される。

The floating gate potential V _fg is approximately proportional to the total amount Q _{f of} charge accumulated in each input gate capacitance and is expressed by the following equation (2).

フローティングゲート電位Ｖ_ｆｇが、ニューロンＭＯＳインバータのフローティングゲートからみた閾値電位Ｖ_ｆｔｈに対して大きければ、ニューロンＭＯＳインバータの出力信号電位Ｖ_ｏｕｔは、閾値電位Ｖ_ｆｔｈに対するフローティングゲート電位Ｖ_ｆｇの論理的反転の電位になる。

If the floating gate potential V _fg is larger _than the threshold potential V _fth seen from the floating gate of the neuron MOS inverter, the output signal potential V _out of the neuron MOS inverter is the logical inversion of the floating gate potential V _{fg with} respect to the threshold potential V _fth . Potential.

As described above, the neuron MOS inverter is a kind of “threshold element” that performs “threshold processing”. In other words, the neuron MOS inverter calculates the floating gate potential V _fg that is approximately proportional to Q _f that is the result of the product-sum operation of V _i and C _i for all input signals by the threshold potential V _fth . It is a kind of “threshold element” that performs “threshold processing”.

  Next, a case where the input signal is binary will be described.

Input signal potential V _i is two take a stable potential {0, V _dd}, the input gate capacitance values C _i, using the input gate capacitance ratio w _i is a value normalized by its smallest value, When C _i = C · w _i , the total amount Q _{f of} charge accumulated in each input gate capacitance is expressed by the following equations (3) and (4).

ニューロンＭＯＳインバータの出力信号を、Ｖ_ｏｕｔとし、Ｖ_ｏｕｔ≧Ｖ_ｆｔｈの電位を、Ｖ_ｈｉｇｈで表現し、Ｖ_ｏｕｔ＜Ｖ_ｆｔｈの電位を、Ｖ_ｌｏｗで表現する。このときに、ニューロンＭＯＳインバータの出力信号Ｖ_ｏｕｔと、各入力ゲート容量に蓄積する電荷量の総和Ｑ_ｆとの関係は、次の式（５）、式（６）で表される。

The output signal of the neuron MOS inverter is V _out , the potential of V _out ≧ V _fth is expressed as V _high , and the potential of V _out <V _fth is expressed as V _low . At this time, the relationship between the output signal V _out of the neuron MOS inverter and the total amount Q _{f of} charge accumulated in each input gate capacitance is expressed by the following equations (5) and (6).

このように、入力信号として｛０，Ｖ_ｄｄ｝の２値を用いた場合は、ｘ_ｉ＝１を入力とする入力ゲート容量の容量比の和

As described above, when the binary value {0, V _dd } is used as the input signal, the sum of the capacitance ratios of the input gate capacitors having x _i = 1 as an input.

とＶ_ｆｔｈとによって、ニューロンＭＯＳインバータの出力信号値が決まる。

And V _fth determine the output signal value of the neuron MOS inverter.

  The operation of the neuron MOS inverter has been described above.

  Next, a known technique related to the circuit using the neuron MOS transistor and the neuron MOS transistor will be described.

  In recent years, research and development of neuron MOS transistors and circuits using the same have been actively conducted, but there are few reports targeting reconfigurable devices (for example, see Non-Patent Document 7). In this document, it has been reported that a circuit that realizes all logic functions has been produced, but there is no report regarding the circuit design technique and the characteristics of the circuit configuration.

  Regarding the structure of a neuron MOS transistor related to the capacitance value of an input gate electrode and a floating electrode, which is one of the important factors in designing a reconfigurable device using a neuron MOS circuit, Japanese Patent Laid-Open No. 3-6679 is disclosed. The basic structure is disclosed in Japanese Patent Publication.

In the above publication, the capacitance value between the input gate electrode and the floating gate electrode is obtained by applying a weighting factor of a neuron model or a neuron MOS transistor to a source follower type circuit, and applying a DA (Digital-Analog) ) It is positioned as a weighting factor in the production of the converter, and the idea as a factor for identifying the state of the input in the reconfigurable device is not shown (for example, see Non-Patent Document 8).
Sueyoshi Toshinori, Current Status and Issues of Reconfigurable Computing System -Toward Computer Evolution-, IEICE Technical Report, VLD96-79, CPSY96-91, pp.111-118, 1996-12 Andre DeHon, DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April, 1994 T. Fujii, et al., A Dynamically Reconfigurable Logic Engine with a Multi-Context / Multh-Mode Unified-Cell Architecture, ISSCC99, WA 21.3 pp. 360-361, 1999 A. Kaviani and S. Brown, The Hybrid Field-Programmable Archtecture, IEEE Design & Test of Computers, pp.74-83, April-June, 1999 Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima, Design method of symmetric function circuit using neuron MOS, Communication technique, CPSY99-90, pp.49-56, 1999-11 Tadashi Shibata and Tadahiro Omi, A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, IEEE Transactions on Electron Devices, Vol. 39, No. 6, pp. 1444-1445, 1992 Tadashi Shibata, et al., Real-Time Reconfigurable Logic Circuits Using Neuron MOS Transistors, ISSCC93, FA 15.3, pp. 238-239, 1993 WS McCulloch and WA Pitts, A Logical Calculus of the Ideas Immanent in Neural Nets, Bull.Match. Biophy., Vol. 5, pp. 115-133, 1992

  In the above background, in order to combine a circuit that realizes a symmetric function function and a low-area-cost circuit that realizes all logic function functions including an asymmetric function in the variable logic part of a reconfigurable device using a neuron MOS circuit, Development of the circuit configuration and the design method is desired.

The present invention has a method of efficiently realizing not only a symmetric function among logic functions but also an arbitrary k-input variable logic function using a neuron MOS circuit, and a logic function function designed using this method. An object of the present invention is to provide a neuron MOS circuit.

The present invention
When an inverter circuit using a neuron MOS transistor or a neuron MOS transistor with a switch is called a neuron MOS inverter,
A two-stage logic function reconfigurable integrated circuit that realizes an arbitrary logic function of k input variables (k is an integer of 2 or more) using the neuron MOS inverter,
The first input gate capacitance between each of the first input signal terminals to which the first input signal as the k input variable is input and the floating gate is a value obtained by standardizing the capacitance value. The input gate capacitance ratios are different from each other, and any number of the first input gate capacitance ratios is set to be different from each other,
For the input vector which is a vector representation of the first input signal, the input vectors when the input charge amounts accumulated in the first input gate capacitance are arranged in ascending order are divided into four blocks in order from one to the smallest. The input vector to which
In the first stage of the integrated circuit capable of reconfiguring the logic function function, a total of three (3/4) · 2 for each block. ^k Comprising pre-inverters which are the above-mentioned neuron MOS transistors,
The second stage of the logic circuit reconfigurable integrated circuit has a main inverter which is the neuron MOS transistor,
The pre-inverter has the first input signal capacitance set between the first input signal terminal and each of the first signal input terminals and a floating gate;
At least one of the pre-inverters includes a second input signal terminal to which a signal for selecting one from three or more threshold values is input, and between each of the second input signal terminals and the floating gate. A second input gate capacitance to be set;
Each of the second input gate capacitances is such that each of the three or more regions composed of four input vectors to the block to which the pre-inverter belongs has any one of the three or more threshold values. The capacity value is set,
An output signal indicating a magnitude relationship between the selected threshold and a normalized floating gate potential determined from an input variable input to the first input signal terminal of the pre-inverter is output to the output terminal;
The main inverter is
The first input signal terminal;
The first input gate capacitance set between each of the first input signal terminals and the floating gate;
A terminal connected to the output terminal of each pre-inverter;
A second terminal between the floating gate and a terminal connected to the output terminal of each pre-inverter, which is set to take a value that differs depending on the floating gate threshold potential by a logical combination of the output signals of the pre-inverter. A second input gate capacitance of the input gate capacitance value of
An output terminal;
A logic function function reconfigurable integrated circuit characterized by comprising:

  According to the integrated circuit design method for reconfigurable logic function functions of the present invention, it is possible to easily implement an arbitrary logic function function in a neuron MOS circuit at a low area cost.

Moreover, according to the integrated circuit designed by this method, the logic function function can be reconfigured, and the area cost can be reduced.

The best mode for carrying out the invention is the following examples.

[outline]
In order to realize an arbitrary k-input variable logic function having binary values as input variables on the integrated circuit, the integrated circuit needs to satisfy the following two conditions.
Condition (1): with a 2 ^k-number of different states corresponding to the combination of the input variables.
Condition (2): For 2 ^k-number of states, respectively, having a mechanism that can be set to one of two values.

When the integrated circuit is configured by the conventional neuron MOS inverter shown in FIG. 25, the condition (1) is “2 ^k with different potential V _{fg of the} floating gate” as described in “Prior Art”. In the above formula (5).

ことである。

That is.

  Each embodiment of the present invention is configured as follows in order to satisfy the above two conditions.

[First embodiment]
1st Example of this invention is the said conditions (1)

ような、重みベクトルＷの要素ｗ_ｉの決定方法と、その方法を実装したニューロンＭＯＳインバータである。

A method for determining the element w _i of the weight vector W and a neuron MOS inverter that implements the method.

The first embodiment discloses a guideline for creating 2 ^k states on a neuron MOS inverter.

[Second Embodiment]
The second embodiment of the present invention is a more specific and formulated method for determining the element w _i of the weight vector W in the first embodiment. The second embodiment discloses a guideline for creating 2 ^k states on a neuron MOS inverter.

[Third embodiment]
In the third embodiment of the present invention, when the minimum value of the element w _i of the weight vector W in the first embodiment is limited,

がより小さくなるような要素ｗ_ｉの決定方法である。ニューロンＭＯＳインバータに実装する際に、

Is a method for determining the element w _i such that becomes smaller. When mounted on a neuron MOS inverter,

は入力ゲート電極の面積に相当し、第３の実施例は、上記条件（１）を満たすニューロンＭＯＳインバータを低面積コストで実現する方法である。

Corresponds to the area of the input gate electrode, and the third embodiment is a method for realizing a neuron MOS inverter satisfying the above condition (1) at a low area cost.

[Fourth embodiment]
The fourth embodiment of the present invention satisfies the condition (1) and realizes the “mechanism” in the condition (2) for any one of the first to third embodiments. This is a method in which the method for designing a symmetric function circuit disclosed in Reference 5 introduced in the prior art is expanded to a method for designing a circuit that realizes an arbitrary logical function, and an integrated circuit designed by using the method. It is the composition. That is, the fourth embodiment is an integrated circuit design method and circuit configuration capable of reconfiguring an arbitrary logical function function.

[Fifth embodiment]
The fifth embodiment of the present invention satisfies the above condition (1) by using any one of the above first to third embodiments, and the “mechanism listed in the above condition (2)”. ”Is a method for designing an integrated circuit in which control of the“ mechanism ”is performed with a multivalued signal, and a circuit configuration. The fifth embodiment is an integrated circuit capable of obtaining the same function at a lower area cost than the fourth embodiment and a design method thereof.

[Sixth embodiment]
While the fifth embodiment expresses a multi-value by a plurality of binary signals at the physical level, the sixth embodiment of the present invention uses a multi-value signal at the physical level. The circuit configuration in the case. The sixth embodiment can obtain the same function at a lower area cost than the fifth embodiment.

  Next, each of the above embodiments will be specifically described.

(First embodiment)
The first embodiment of the present invention is based on “a method for determining an element w _i that can identify a combination of 2 ^k input variables x _i ” and “an implementation of a weight vector that can identify an input vector on a neuron MOS inverter”. It is configured.

[How to determine an element w _i that can identify a combination of 2 ^k input variables x _i ]
It is said condition (1)

は、「２^ｋ個存在する入力変数の組み合わせを識別できる」ことである。初めに、「入力変数の組み合わせ」と「識別できる」の定義について、入力変数が｛ｘ_１，ｘ_２，ｘ_３｝の３変数である場合を例にとって、具体的に説明する。

^Means “a combination of 2 ^k input variables can be identified”. _First , the definition of “combination of input variables” and “identifiable” will be specifically described by taking as an example the case where the input variables are _three variables of {x ₁ , x ₂ , x ₃ }.

For example, when each of the three input variables logically has a binary value of 1, 0, these combinations are {0, 0, 0}, {0, 0, 1}. , {0, 1, 0},..., {1, 1, 1}, and there are 2 ³ , and these 2 ³ combinations are called “input variable combinations”.

  Next, the fact that “a combination of input variables can be identified” will be described.

The above combination is a vector representation of vertex coordinates of a three-dimensional cube in a three-dimensional space when coordinates orthogonal to each other are set for three input variables. Hereinafter, this vector is referred to as “input vector X”. An arbitrary positive number (w ₁ , w ₂ , w ₃ ) is called a “weight vector W”. Using the input vector X and the weight vector W,

について、次の式（７）に示すように、内積を用いてベクトルをスカラに変換することができる。

As shown in the following equation (7), a vector can be converted to a scalar using an inner product.

この表現を用いて換言すれば、「入力変数の組み合わせを識別できる」とは、「入力ベクトルと重みベクトルとの内積の結果であるスカラが互いに異なること」である。

In other words, using this expression, “the combination of input variables can be identified” means “the scalars resulting from the inner product of the input vector and the weight vector are different from each other”.

Here, since the input vector X is a binary value of {0, 1}, in order for the scalars to be different from each other, an arbitrary number composed of non-overlapping elements of {w ₁ , w ₂ , w ₃ } The sum of elements must be different from each other. That is, it is necessary that w ₁ ≠ w ₂ ≠ w ₃ and w ₁ + w ₂ ≠ w ₂ + w ₃ ≠ w ₃ + w ₁ . As a specific example, if the weight vector W = (2 ⁰ , 2 ¹ , 2 ² ), the input vector X may be regarded as a binary representation and converted from a binary representation to a decimal representation by an inner product. . In this case, the eight input vectors are converted to different integers from 0 to 7.

  Next, a description will be given of the fact that there are a large number of weight vectors W that can make “scalars different from each other”, not only vectors composed of elements of powers of two.

Considering a weight vector W in which elements are numbered in ascending order, taking k = 4 as an example, in order to “scalars differ from each other”, w ₄ > w ₃ > w ₂ > w ₁ , w ₃ ≠ w ₁ + w ₂ , w ₄ ≠ w ₁ + w ₃ , w ₄ ≠ w ₂ + w ₃ , w ₄ ≠ w ₁ + w ₂ + w ₃ , w ₄ + w ₁ ≠ w ₃ + w ₂ .

Specific examples that satisfy this are (w ₁ , w ₂ , w ₃ , w ₄ ) = ( ₁ , 1.1, 1.2, 1.4), (w ₁ , w ₂ , w ₃ , w ₄ ). _{= (1,1.2,1.4,1.7), (w 1} , w 2, w 3, w 4) = (1,4,6,8), (w 1, w 2, w 3 , W ₄ ) = (1, 3, 9, 27).

In the case of an input vector composed of k elements, the above description can be made by identifying “{w ₁ , w ₂ ,..., W _i ,. It can be said that the sum of an arbitrary number of elements composed of non-overlapping elements in w _k } needs to be different from each other .

[Implementation of weight vector that can identify input vector to neuron MOS inverter]
As described in the above prior art, the element w _{i of the} weight vector corresponds to the capacitance ratio of the input gate capacitance between the input gate electrode corresponding to each input variable and the floating gate in the neuron MOS inverter. Therefore, in the neuron MOS inverter, an input vector can be identified by making the sum of an arbitrary number of input gate capacitance ratios composed of non-overlapping elements different from each other.

(Second embodiment)
The second embodiment of the present invention first shows a condition that guarantees that an input vector of an arbitrary number of elements can be identified in advance, and a weight vector that satisfies the condition, and then the number of input variables. This is an embodiment in which a weight vector that guarantees that an input vector can be identified by adding a restriction to is shown, and finally, the weight vector is implemented in a neuron MOS inverter.

  That is, in the second embodiment, “presentation of a condition with a restriction on the method of determining the weight vector of the first embodiment”, “a set of weight vectors that satisfy the restriction”, and “input It is composed of “a set of weight vectors when the number of variables is limited” and “implementation to a neuron MOS inverter”.

[Conditions in which the method for determining the weight vector of the first embodiment is limited]
When the values of k elements of the weight vector W are {w ₁ , w ₂ ,..., W _i ,..., W _k } in ascending order, the i-th element w _i satisfies the following expression (8). Set as follows.

上記式（８）は、第１の実施例で示した条件よりも強い制限条件であり、任意の数の要素を持つ入力ベクトルを識別できることを保証している。

The above equation (8) is a restrictive condition stronger than the condition shown in the first embodiment, and guarantees that an input vector having an arbitrary number of elements can be identified .

[A set of weight vectors that satisfy the conditions with restrictions]
Next, the element w _i of the weight vector W that satisfies the above equation (8) is specifically shown.

  First, the above equation (8) is transformed into the following equation (9).

上記式（９）を満たす解の１つであるｗ_ｉ＝α^ｉ−１（α＞１）であるときに、上記式（９）は、次の式（１０）で表される。

When w _i = α ⁱ⁻¹ (α> 1), which is one of the solutions satisfying the above equation (9), the above equation (9) is expressed by the following equation (10).

f (α, i) = g (α, i) / (α−1) (1 ≦ i ≦ k−1)... (10)
g (α, i) = α ⁱ · (α−2) +1 (11)
Since the sign of the function f (α, i) represented by the above equation (10) matches the sign of the function g (α, i) from the condition of α> 1, the sign of the function f (α, i) The determination can be performed using the function g (α, i). Therefore, the input vector can be identified when the following equation (12) holds.

g (α, i) = α ⁱ · (α−2) +1> 0 (1 ≦ i ≦ k−1) (12)
Further, when the first-order derivative of g (α, i) with respect to α is described as g ′ (α, i), the following equation (13) is established when i> 1.

式（１３）が成り立つので、関数ｇ（α，ｉ）は、１＜α＜２において、少なくとも１つの実根を持ち、α≧２において、任意のｉに対して常に正である。このために、次の式（１４）を満たす重みベクトルを用いると、任意の数の要素を持つ入力ベクトルを識別することができる。

Since equation (13) holds, the function g (α, i) has at least one real root when 1 <α <2, and is always positive for any i when α ≧ 2. Therefore, when a weight vector satisfying the following expression (14) is used, an input vector having an arbitrary number of elements can be identified .

In the above equation (14), an input vector having an arbitrary number of elements represents an identifiable weight vector, but even if 1 <α <2, α satisfying g (α, i)> 0 The presence of i indicates that the input vector can be identified by limiting i, that is, the number of elements k of the input vector .

  FIG. 6 is a diagram illustrating a relationship between α satisfying 0 ≦ α ≦ 2 and g (α, i) when i = 1, 2, 3, 4, 5.

  When 1 <α <2, the solution of g (α, i) = 0 is 1.6180, 1.8393, 1.9276, 1.9660 for i = 2, 3, 4, 5, respectively. It is.

  Since i ≦ k−1, FIG. 6 shows that when the number of elements k = 2, 3, 4, 5, 6, α> 1, α> 1.6180, α> 1.8393, α, respectively. If> 1.9276 and α> 1.9660, the condition of Expression (9) is satisfied, and in principle, the input vector can be identified.

Let S ₂ be a scalar that is the result of an inner product using (2 ⁰ , 2 ¹ ,..., 2 ⁱ⁻¹ ,..., 2 ^k−1 ) as a weight vector for an input vector that can be clearly identified. Also, let S _α be a scalar that is the result of the inner product of the weight vector and the input vector.

FIG. 7 is a diagram illustrating the relationship between the scalar S ₂ and the scalar S _α using α when α = 1.7, 1.9, 2.0, and 2.2.

When α ≧ 2, the function g (α, i)> 0 is satisfied. In the case shown in FIG. 7, the scalar S _α is a monotonically increasing function whose slope does not become 0 with respect to the scalar S ₂ . Therefore, as described above, in the scalar S _alpha for all input vectors, those with a value equal because there can identify the input vector to each other.

From FIG. 6, when α = 1.7 and α = 1.9, if S ₂ ≦ 7 and S ₂ ≦ 15, respectively, the slope of the scalar S _α is 0 with respect to the scalar S ₂ . Since this is a monotonically increasing function with no input, the input vector can be identified.

On the other hand, even if out of the above range, if S ₂ ≦ 31, there is no mutually equal S _α . In this case, although Expression (8) is not satisfied, this corresponds to the first embodiment in which the input vector can be identified .

[Mounting to neuron MOS inverter]
When the above method is mounted on an actual circuit, the actual capacitance value does not necessarily satisfy the equation described above for manufacturing reasons such as manufacturing variations. Further, even at the time of designing, it cannot be said that the equations in the above description are always satisfied by determining significant figures and securing a design margin. However, the above-described embodiment can be applied even when there is a difference in values due to such a variation in values due to manufacturing reasons or a method of taking a margin at the time of design. That is, it is clear that the present invention also includes the case where there is a difference in value due to manufacturing reasons as described above, or a difference in value due to a design margin or the like.

(Third embodiment)
In the third embodiment of the present invention, when the minimum value C · w ₁ of the elements of the weight vector shown in the prior art has a lower limit,

をできるだけ小さくし、入力ベクトルを識別できる重みベクトルを決める方法である。

Is as small as possible, and a weight vector that can identify an input vector is determined.

  In this method, when there is a lower limit in the minimum value of the input gate capacitance value in the neuron MOS inverter, the sum of the input gate capacitance values is made as small as possible to determine the input gate capacitance ratio that can identify the input vector. Equivalent to.

[Examples and problems when the minimum value is limited]
The case where a limit is imposed on the minimum input gate capacitance value may be a case where variation in the capacitance value in the capacitance manufacturing process is suppressed when mounted on an actual circuit. In the second embodiment, when the minimum capacitance value is limited by a certain value, the ratio of the input gate capacitance increases as a power of a certain value, so that the sum of the input gate capacitance values becomes very large, and the area There is a problem that the cost becomes high.

[How to lower the power order]
Therefore, in order to reduce the area cost, it is effective to reduce the power order. Here, when the elements of the weight vector are arranged in ascending order of values, if {w ₁ , w ₂ ,..., W _i ,..., W _k } are satisfied, Set the i-th element w _i . However, α> 1.

式（１５）のように設定した場合、次の式（１６）が成り立つ。

When set as in equation (15), the following equation (16) holds.

第３の実施例は、第２の実施例と同様に、α≧２の場合は、任意のｉ、すなわち、任意のｋにおいて、ｆ’（ｉ）＞０となり、入力ベクトルを識別でき、１＜α＜２であっても、ｋを制限することによって、ｆ’（ｉ）＞０にすることもでき、入力ベクトルを識別できる。

As in the second embodiment, in the third embodiment, when α ≧ 2, f ′ (i)> 0 at any i, that is, any k, and the input vector can be identified. Even if <α <2, f ′ (i)> 0 can be set by limiting k, and the input vector can be identified.

[Effect on area cost]
Next, in the case of w _i = α ⁱ⁻¹ in the second embodiment and in the third embodiment, the minimum input gate capacitance value is limited, both are w ₁ = 1, and α = 2. If the sums of the values of the weight vector elements in the second embodiment are Sum ₍₂₎ and Sum ₍₃₎ , respectively, the sum Sum ₍₂₎ of the values of the weight vector elements in the second embodiment is The sum Sum ₍₃₎ of the values of the elements of the weight vector in the third embodiment is the value shown in the following equation (18) .

Sum ₍₂₎ = 2 ^k −1 Expression (17)
Sum ₍₃₎ = 1 + (2 ^k−1 −1) (1 + β) Equation (18)
Therefore, the ratio η of the sum Sum _{(3 )} to the sum Sum ₍₂ ) is expressed by the following equation (19).

η = {1+ (2 ^k−1 −1) (1 + β)} / (2 ^k −1) (19)
FIG. 8 is a diagram illustrating the relationship between the weight modulation coefficient β and the ratio η of the sum Sum ₍₃₎ to the sum Sum _{( 2)} when k = 2, 3, and 4.

  That is, FIG. 8 is a diagram showing the area cost reduction rate in the third embodiment. When β = 0.5, the area cost varies somewhat depending on the number k of elements, but the area cost can be reduced to about 77% to 83%.

[Mounting to neuron MOS inverter]
When the above method is mounted on an actual circuit, the actual capacitance value does not necessarily satisfy the equation described above for manufacturing reasons such as manufacturing variations. Further, even at the time of designing, it cannot be said that the above-described equation is necessarily satisfied by how to determine significant figures and securing a design margin. However, the above-described embodiment can be applied even when there is a difference in values due to such a variation in values due to manufacturing reasons or a method of taking a margin at the time of design. That is, it is clear that the present invention also includes the case where there is a difference in value due to manufacturing reasons as described above, or a difference in value due to a design margin or the like.

(Fourth embodiment)
The fourth embodiment of the present invention is a weight vector that can identify the input vector described in the first to third embodiments, that is, 2 ^k inputs having ^k elements, depending on how the input gate capacitance ratio is determined. This is an integrated circuit that can set one of two values for a vector .

[Definition of terms]
First, definitions of terms that are frequently used when the operation of the integrated circuit is described below will be described. That is, terms for describing the operation of the neuron MOS inverter shown in FIG. 25 are defined.

  The “floating gate threshold potential” is the potential of the floating gate of the neuron MOS inverter when the output signal of the neuron MOS inverter shown in FIG. 25 is logically inverted with respect to the floating gate potential.

  The “maximum floating gate potential” is a floating gate potential when all input signals are logically 1.

The “normalized floating gate potential U _fg ” is a floating gate potential normalized by the maximum floating gate potential.

The “normalized floating gate threshold potential U _fth ” is a floating gate threshold potential normalized by the maximum floating gate potential.

“Input charge amount Q _i ” is the amount of charge accumulated in the input gate capacitance of the terminal to which the input variable is input.

"Input threshold charge amount _{Q i @ th"} is normalized floating gate voltage _{U fg} is input charge amount _{Q i} of when a normalized floating gate threshold voltage _{U fth.}

[Circuit configuration of an integrated circuit that realizes an arbitrary logic function]
FIG. 1 is a block diagram showing an integrated circuit IC1 capable of reconfiguring a logic function function according to a first embodiment of the present invention.

  First, the circuit configuration of the integrated circuit IC1 will be described.

  The integrated circuit IC1 that realizes the k-input variable logic function function is constituted by the two-stage logic of the neuron MOS inverter shown in FIG. 25, that is, the pre-inverter 101 and the main inverter 100.

  The pre-inverter 101 is a first-stage neuron MOS inverter, and the main inverter 100 is a second-stage neuron MOS inverter.

Pre inverter 101, ^{2 k} pieces are provided.

Each pre-inverter 101 receives input gate electrodes connected to first input signal terminals input1 [1] to input1 [k] to which k input variables are input and data constituting a logic function function. that one input gate electrode in the second input signal terminals ^{input2 [1] ~input2 [2 k} ] to the connected input gate electrode, the power source or ground to control the threshold as seen from the input signal of the pre-inverter 101 And an input gate electrode connected to a terminal having a fixed potential, and an output terminal.

  The main inverter 100 includes an input gate electrode connected to the k first input signal terminals, an input gate electrode connected to the output terminal of the first pre-inverter 101, and an output terminal. Have.

[Design of main inverter 100]
[How to determine the capacity ratio connected to the pre-inverter 101]
Next, a method for setting the capacitance ratio between the input gate electrode connected to the output terminal of the pre-inverter 101 and the floating gate in the main inverter 100 of the integrated circuit IC1 will be described.

  Here, the number of elements is k = 3, and the weight vector for identifying the input vector, that is, the ratio of the input gate capacitance for the first input signal is (1, 3, 5). Suppose there is.

FIG. 2 shows that in the above embodiment, when the number of elements k = 3 and the weight vector is (1, 3, 5), the input charge amount Q _i in the main inverter 100.

と、規格化フローティングゲート電位Ｕ_ｆｇとの関係を示す図である。

And a normalized floating gate potential U _fg .

In FIG. 2, the horizontal axis represents the input charge amount Q _i , and the vertical axis represents the normalized floating gate potential U _fg . On the horizontal axis, the input vector is also written at the position of Q _i of each input vector. In FIG. 2, C _total is the _total sum of all input gate capacitance values.

を示す。

Indicates.

_First , the normalized floating gate threshold potential U _fth is set to about _½ . When all the first input signals are logically 1, the input charge amount Q _i is maximized. The normalized floating gate potential U _fg due to the input charge amount Q _{i at} this time is _prevented from _{exceeding the} normalized floating gate threshold potential U _fth .

Then, when the input vector input charge amount _{Q i} is the maximum _{(x 3, x 2, x} 1) = (1,1,1), among the ^{2 3} are provided pre-inverter 101, The output of the pre-inverter 101 is such that the normalized floating gate potential U _fg when only the output signal of the eighth pre-inverter 101 is logically 1 is larger than the normalized floating gate threshold potential U _fth. A capacitance value C _p8 between the input gate electrode connected to the terminal and the floating gate is set.

However, in the case of an input vector (1, 1, 0) having an input charge amount one smaller than the input vector (1, 1, 1), the normalized floating gate potential U _fg is normalized in the same input signal state. It is made smaller than the floating gate threshold potential U _fth .

Similarly to the case of the input vector (1, 1, 1) and the capacitance value C _p8 , when the input vector is (1, 1, 0), the seventh and eighth pre-inverters 101 If only the output signal is logically 1, the normalized floating gate potential U _fg is larger than the normalized floating gate threshold potential U _fth and when the input vector is (1, 0, 1), the normalized floating gate potential U _fg is normalized. The value of the input gate capacitance value C _p7 connected to the seventh pre-inverter 101 is set so that the floating gate potential U _fg is smaller than the normalized floating gate threshold potential U _fth .

In the same manner as described above, the input vectors (1, 0, 1), (1, 0, 0), (0, 1, 1), (0, 1, 0), (0 , 0, 1) and (0, 0, 0), the values of input gate capacitance values C _p6 , C _p5 , C _p4 , C _p3 , C _p2 , and C _p1 are set.

By the method described above, to set the capacitance value of the input gate capacitance connected to the output terminal of the 2 ³ pre-inverters 101.

[Explanation that an arbitrary logical function can be realized]
Next, the point that the main inverter 100 having the input gate capacitance value set by the above method can realize an arbitrary logical function will be described.

For the input charge amount Q _i on the horizontal axis in FIG. 2, there are two input vectors sandwiching a predetermined input vector. That is, for a given input vector, an input vector with an input charge amount larger than the input charge amount of the input vector and an input vector with a small input charge amount exist, and other input between these three input charge amounts There is no input charge for the vector.

However, for the input vector (0, 0, 0), only the input vector (0, 0, 1) having a large input charge amount Q _i exists, and for the input vector (1, 1, 1). Only an input vector (1, 1, 0) having a small input charge amount Q _i exists.

One input charge amount Q _i between the given input vector and the input charge amount Q _i is larger input vectors, with one Q _i between the small input vector, in either the pre-inverter 101 Each pre-inverter 101 has a function of causing logic inversion and the logical value of the output signal changing from 1 to 0. In this case, the normalized floating gate potential U _fg and the normalized floating gate threshold value in each input vector The magnitude relationship with the potential U _fth depends only on the logical 1, 0 value of the output signal of the pre-inverter 101 corresponding one-to-one with each input vector.

2, black dots at each input vector indicates when the normalized floating gate voltage U _fg is larger than the normalized floating gate threshold voltage U _fth, the white circles at each input vector, the normalized floating gate voltage U _fg is standard A case is shown in which the floating gate threshold potential U _fth is smaller than that.

  Therefore, an arbitrary logical function can be realized by giving the pre-inverter 101 a control signal for selecting one of the two input threshold charge amounts of each pre-inverter 101 as data constituting the logical function function. Can do.

[Design of pre-inverter 101]
[Method of determining the volume ratio for having two _{Q ith]}
Next, a method of giving the pre-inverter 101 two input threshold charge amounts Q _ith will be described.

  FIG. 3 is a diagram illustrating a relationship between the circuit diagram of the j-th pre-inverter 101 and the capacitance value between each input gate electrode and the floating gate.

Hereinafter, among the pre-inverters 101 provided ^{2 3} will be described using a fifth pre-inverter 101 corresponding to the input vector (1,0,0).

FIG. 4 is a diagram showing the relationship between the input charge amount Q _i in the fifth pre-inverter 101 and the normalized floating gate potential U _fg .

In FIG. 4, C _total is

を示す。

Indicates.

First, similarly to the main inverter 100, the first input signal input gate capacitance value C _51i in the fifth pre-inverter 101 is set so that the input vector can be identified.

  In FIG. 4, the ratio of the input gate capacitance for each first input signal is set to the same capacitance ratio as that of the main inverter 100, but it is not necessarily the same, and the input vector can be identified. I just need it.

Next, when the second input signal is logically 0, the input threshold charge amount Q is 0 at which the normalized floating gate potential U _fg becomes the normalized floating gate threshold potential U _fth is _represented by the input vector (1, becomes between _{Q i} of 0,0) and _{Q i} of the (1,0,1), at the same time, when the second input signal is logical 1, the normalized floating gate voltage _{U fg} is standard as of floating gate threshold voltage _{U fth} become input threshold charge _{Q ITH1} becomes between _{Q i} of the _{Q i} of the input vector (1,0,0) (0,1,1), 5 th The first input signal input gate capacitance value C _51i and the second input signal input gate capacitance value C ₅₂₀ in the pre-inverter 101 are set.

At this time, if the input vector is (1, 0, 0), the value that can be taken by the normalized floating gate potential U _fg of the pre-inverter 101 is the standard when the second input signal is logically 1. A value larger than the normalized floating gate threshold potential U _fth (black circle in FIG. 4) and a value smaller than the normalized floating gate threshold potential U _fth when the second input signal is logically 0 (in FIG. 4) No. white circle).

FIG. 5 shows the logical value of the input vector (or input charge amount Q _i ) and the output signal of the pre-inverter 101 when the input vector and the normalized floating gate potential U _fg have the relationship shown in FIG. It is a figure which shows the relationship.

As shown in FIG. 5, until the input vector with a smaller _{Q i} than _{Q i} of the input vector (1,0,0) (0,1,1) is a logical 1, on the contrary, a large Q _For an input vector (1, 0, 1) with _i , it is logically zero. Thus, the above function of the pre-inverter 101 can be realized. Here, the logical value of the output signal is 0 if it is larger than the normalized floating gate potential U _fg and the normalized floating gate threshold potential U _fth , and conversely, if it is smaller, it is 1.

  The above description is a description of a method for designing a circuit that realizes all logical functions when k = 3. However, when k is an arbitrary value other than 3, Can be realized. Further, the integrated circuit IC1 can be designed by this method.

[Explanation when a neuron MOS inverter with a switch different from the neuron MOS inverter is used]
The above description is for the integrated circuit IC1 constituted by the neuron MOS inverter shown in FIG.

  Next, the integrated circuit IC1a constituted by the neuron MOS inverter with switch will be described.

  FIG. 20 is a configuration diagram showing an integrated circuit IC1a capable of reconfiguring a logic function function, which is a modification of the integrated circuit IC1 capable of reconfiguring the logic function function.

  The logic circuit function reconfigurable integrated circuit IC1a is an integrated circuit having a circuit configuration similar to that of the integrated circuit IC1 shown in FIG. The integrated circuit IC1a differs from the integrated circuit IC1 only in that a main inverter 110 is provided instead of the main inverter 100, and a preinverter 111 is provided instead of the preinverter 101.

  The main inverter 100 and the pre-inverter 101 in the integrated circuit IC1 have their floating gates in a completely floating state, and are not connected to any terminals.

  On the other hand, the main inverter 110 and the pre-inverter 111 in the integrated circuit IC1a are neuron MOS inverters with a switch having an inverter function using neuron MOS transistors with a switch.

  A neuron MOS transistor with a switch is a neuron MOS transistor whose floating gate can be connected to and disconnected from a terminal having a predetermined potential by conduction and interruption of a switch element such as an NMOSFET.

  In the integrated circuit IC1a, the main inverter 110 is electrically connected to and disconnected from a terminal having a predetermined potential via the main inverter initialization NMOSFET 113 whose conduction and interruption are controlled by a signal at the terminal ctlm. It is turned on and off to a terminal having a predetermined potential via a pre-inverter initialization NMOSFET 114 controlled by a ctlp signal.

  Except for the points described above, the circuit configuration of the integrated circuit IC1 and the circuit configuration of the IC 1a are the same.

Therefore, the following description will be made on a circuit using the main inverter 100 and the pre-inverter 101 used in the integrated circuit IC1 shown in FIG. The same design method can be used for the circuit configuration of the integrated circuit IC1a.

(Fifth embodiment)
In the fifth embodiment, the number of pre-inverters 101 in the integrated circuit IC1 in which the logic function function of the two-stage logic can be reconfigured is reduced by expressing the logic function configuration data in multiple values .

[Circuit configuration of integrated circuit when multi-value expression is used as configuration data]
FIG. 9 is a circuit diagram of an integrated circuit IC2 which is an embodiment of the present invention, and is a circuit diagram of the integrated circuit IC2 having the above function.

  The integrated circuit IC2 is an integrated circuit that realizes the k-input variable logic function function, and is configured by the two-stage logic of the neuron MOS inverter as described in the fourth embodiment, that is, the main inverter 901 and the pre-inverter 902. And the two-stage logic.

  The main inverter 901 has an input gate electrode connected to the first input signal terminals input1 [1] to input1 [k] to which k input variables are input, and an input gate connected to the output terminal of the pre-inverter 902. Electrode.

In addition to the first input signal terminal, the pre-inverter 902 is viewed from the input signal and the second input signal terminals input2 [11] to input2 [ha _h ] to which data constituting the logic function is input. And an input gate electrode connected to a terminal having a fixed potential typified by a power source or a ground for controlling the threshold value.

Here, comparing the circuit configuration with the fourth embodiment, the integrated circuit IC1 of the fourth embodiment has a circuit configuration having 2 ^k pre-inverters 101 having only one second input signal terminal. the case, the integrated circuit IC2, each pre-inverter 101 has a second input signal terminals of a plurality, forming the circuit in the pre-inverter 101 is less than 2 ^k pieces. That is, in FIG. 9, _{h of} the second input terminal input 2 [ha _h ] represents the number of pre-inverters and is smaller than 2 ^k , and a _h is the second input in the h-th pre-inverter 101. The number of signals.

  In addition, using a plurality of second input signals means using one multi-value signal in place of using one second input signal. For example, when two values are used, one input signal can represent two different values of {0, 1}, that is, only two values can be represented, but two input signals can be represented by {(0, 0 ), (0, 1), (1, 0), (1, 1)}, that is, four values can be expressed.

[Design of pre-inverter 902: Determination of input gate capacitance ratio]
Next, the circuit configuration of the pre-inverter 902 in the integrated circuit IC2 shown in Fig. 9, with respect to the input threshold charge Q _{i @ th} is a threshold value as seen from the input signal, it is possible to generate any of a plurality of Q _{i @ th,} the The point will be described.

  As a specific example, a case where k = 2 and two second input signals are used will be described.

  FIG. 10 is a circuit diagram showing a neuron MOS inverter INV3 having three threshold values as viewed from an input signal.

The neuron MOS inverter INV3 has two first input signal terminals input1 [1] and input1 [2], two second input signal terminals input2 [h1] and input2 [h2], and a terminal connected to the ground. And have. _Assume that the input gate capacitance values between the input gate electrodes and the floating gate are C ₁₁ , C ₁₂ , C _{2h 1} , C _{2h 2} , and C _gnd . Regarding the input gate capacitance values C ₁₁ and C ₁₂ , as described in the fourth embodiment, the input vector can be identified by setting C ₁₁ : C ₁₂ = 1: 2.

At this time, the input signal terminals with a capacity of input gate capacitance values _{C 11, C 12 input1 [1} ], the input variables corresponding to input1 _[2], and x 1, _{x 2,} a small input charge amount _{Q i} When the input vectors (x ₁ , x ₂ ) are arranged in order, they become (0, 0), (1, 0) (0, 1), (1, 1).

Next, the neuron MOS inverter INV3 shown in FIG. 10 includes an area between the input vectors (0, 0) and (1, 0), an area between (0, 1) and (1, 1). , A method of determining the input gate capacitance values C _2h1 , C _2h2 , and C _gnd so that each of the three regions including the region larger than (1, 1) has one input threshold charge amount Q _itth. .

FIG. 11 is a diagram showing the relationship between the input charge amount of the neuron MOS inverter INV3 having the above characteristics and the normalized floating gate potential _Ufg .

Further, it is assumed that the normalized floating gate threshold potential U _fth is set in the vicinity of _½ .

In FIG. 11, C _total indicates C ₁₁ + C ₁₂ + C _2h1 + C _2h2 + C _gnd, and line 0 indicates a normalized floating gate potential when all input signals other than the first input signal are logically 0. U _fg , line 1 represents the normalized floating gate potential U _fg when the second input signal input from input 2 [h 1] is always logically 1, and line 2 represents input 2 [h 1] and input 2 The normalized floating gate potential U _fg in the case where both of the second input signals input from [h2] are always logically 1 is shown.

To _{Q i} is larger area than the input vector (1,1), because it has a single _{Q i @ th,} the _{(C 11 + C 12) /} C total, is less than (1/2). That is, among the three input threshold charge amounts of the neuron MOS inverter INV3 shown in FIG. 11, the maximum input threshold charge amount is larger than the input charge amount Qi when the input vector is (1, 1). (C ₁₁ + C ₁₂ ) / C _total equivalent to the normalized floating gate potential when the vector is (1, 1) must be set smaller than the normalized floating gate threshold potential U _fth = 1/2. Don't be. As a result, line 0 intersects with the normalized floating gate threshold potential U _fth in the region of Q _i larger than that of the input vector (1, 1).

A straight line line0, line1, line2 in FIG. 11, the intersection between the normalized floating gate threshold voltage _{U fth} is _{Q i @ th,} normalized floating gate voltage _{U fg} of line0~line2 is from normalized floating gate threshold voltage _{U fth} If Q _i is smaller, the output signal of the neuron MOS inverter is logically 1; conversely, for large Q _i , the output signal is logically 0.

Also, we want to set the charge amount _{Q i} between the input vectors an input threshold charge _{Q i @ th} neuron MOS inverter INV3 and (0,1) and (1, 1), line1 and the normalized floating gate threshold voltage _{U fth} C _2hi / C _total is set so that the intersection point between and is between the input vectors (0, 1) and (1, 1) in FIG.

Similarly, in the _{Q i} between the input vectors (0, 0) and _(1,0), in order to provide a _{Q i @ th,} the intersection of the line2 and the normalized floating gate threshold voltage _{U fth,} FIG 11, C _2h2 / C _total is set to be between the input vectors (0, 0) and (1, 0).

Finally, 1− (C ₁₁ + C ₁₂ + C _2h1 + C _2h2 ) / C _total is set as C _gnd / C _total . Thus, by determining the respective input gate capacitance value, any input charge amount Q _i, it is possible to set the input threshold charge Q _{i @ th.}

[Input / output characteristics of pre-inverter 902]
FIG. 12 is a diagram showing the input / output characteristics of the neuron MOS inverter when the input gate capacitance value is set by the above method.

In FIG. 12, the horizontal axis indicates Q _i , and the vertical axis indicates a value obtained by normalizing the output potential V _out of the neuron MOS inverter with the power supply potential V _dd or a logical value. In FIG. 12, (1, 1), (1, 0), and (0, 0) are the logical values of the input signals from the second input signal terminals input2 [h1] and input2 [h2], respectively. Are (1, 1), (1, 0), (0, 0).

As can be seen from FIG. 12, the second input signal having two binary representations is input to the neuron MOS inverter, the values of the input gate capacitances are set as described above, and the second binary representation of the second binary representation is set. A neuron MOS inverter having three different thresholds is designed by using three values (1, 1), (1, 0), and (0, 0) among four values represented by the input signal can do.

[Circuit Configuration of Main Inverter 901]
Next, it will be described that the neuron MOS inverter designed by the above method is used as the pre-inverter 902, and that the integrated circuit IC2 configured with a smaller number of pre-inverters than the first embodiment can realize an arbitrary logical function function. As a specific example, a case where k = 2 will be described.

  FIG. 13 is a circuit diagram showing an integrated circuit IC3 that is an embodiment of the present invention. In the case where k = 2, the circuit diagram of the integrated circuit IC3 that can reconfigure the logic function function is shown.

In the fourth embodiment, when k = 2, 2 ^k = 4 pre-inverters 101 are required. However, in the integrated circuit IC3, the pre-inverter 902 using the above multi-value expression is used, and 3 ^k The same function as described above is realized by the two pre-inverters 902.

The main inverter 1300 includes a first input signal terminals input1 [1], i nput1 [ 2] and the capacitance of the input gate capacitance values _{C m1, C m @ 2} between the floating gate the input variables _x 1, _{x 2} are input And have capacitances of input gate capacitance values C _p1 , C _p2 , and C _p3 between the floating gates and the terminals connected to the output terminals of the pre-inverters 1301, 1302, and 1303.

Here, C _m1 : C _m2 = 1: 2, and the input vector can be identified. Further, the input gate capacitance values C _p1 , C _p2 , and C _p3 are determined as follows.

[How to determine the input gate capacitance ratio of the main inverter 1300]
In the fourth embodiment, a pre-inverter 101 corresponding one-to-one with each input vector is determined, and the logical value of the output signal and the logical value of the output signal of the main inverter 100 are associated with each other. Realize the function.

  In the integrated circuit IC3, a pre-inverter corresponding to a predetermined one input vector among four input vectors is determined from the pre-inverters 1301, 1302, and 1303. The logical value of the output signal is associated with the logical value of the output signal of the main inverter 1300. For the other three input vectors, the combination of the logical values of the output signals of the two pre-inverters is used. The logical value of the output signal of the inverter 1300 is determined.

FIG. 14 is a diagram showing a relationship between Q _i (or an input vector) in the main inverter 1300 of the integrated circuit IC3 shown in FIG. 13 and the normalized floating gate potential U _fg .

  In FIG. 14, the horizontal axis

は、Ｑ_ｉを示し、（０，０）、（１，０）、（０，１）、（１，１）は、入力変数（ｘ_１，ｘ_２）に対する入力ベクトルを示し、縦軸は、規格化フローティングゲート電位Ｕ_ｆｇを示している。

Indicates Q _i , (0,0), (1,0), (0,1), (1,1) indicate input vectors for the input variables (x ₁ , x ₂ ), and the vertical axis indicates The normalized floating gate potential U _fg is shown.

In FIG. 14, U _fth represents a normalized floating gate threshold potential, and C _total represents a sum of input gate capacitance values (C _m1 + C _m2 + C _p1 + C _p2 + C _p3 ).

In the input vector (1, 1) that is the maximum input charge amount, the normalized floating gate potential U _fg when the logical values of the output signals of the _preinverter are all 0 exceeds the normalized floating gate threshold potential U _fth C _p1 + C _p2 + C _p3 is set so as not to occur.

Here, the ratio of C _m2 , C _p1 , C _p2 , and C _p3 with C _m1 as a reference is set to w _m2 , w _p1 , w _p2 , and w _p3 . In the specific example shown in FIG. 14, w _m2 = 2 and (w _p1 + w _p2 + w _p3 ) = 4.

Next, in the input vector (0, 0) at the minimum input charge amount, when the output signals of the pre-inverters 1302 and 1303 are logically 1, the output signal of the pre-inverter 1301 is logically 0 When the normalized floating gate potential U _fg is smaller than the normalized floating gate threshold potential U _fth and the output signal of the pre-inverter 1301 is logically 1, the normalized floating gate potential U _fg is the normalized floating gate threshold. W _p1 and (w _p2 + w _p3 ) are set so as to be _higher than the potential U _fth . In the specific example shown in FIG. 14, w _p1 = 1 and (w _p2 + w _p3 ) = 3.

In addition, the pre-inverter 1301 has two Q _is as a _result of one second input signal, Q _i smaller than the input vector (0, 0), input vectors (0, 0), and (1, 0). Q _i in between.

Finally, w _p2 and w _p3 are set as follows.

In the input vector (1, 1), only the output signal of the pre-inverter 1303 is logically 1, and the normalized floating gate potential U _fg when the output signals of the pre-inverters 1301 and 1302 are logically 0 is larger than the normalized floating gate threshold voltage _{U fth,} in the input vector (0,1), normalized floating gate voltage _{U fg} of the same condition, to be smaller than the normalized floating gate threshold voltage _{U fth.}

Further, in the input vector (1, 0), the normalized floating gate potential U _fg when the combination of the logical values of the output signals of the pre-inverters 1301, 1302, and 1303 is (0, 1, 1) is the standard. of the floating gate threshold voltage _U greater than _fth, normalized floating gate voltage _{U fg} when a (0,1,0) is smaller than the normalized floating gate threshold voltage _{U fth,} the input vector (0,1 ), The normalized floating gate potential U _fg when the combination of the logical values of the output signals of the pre-inverters 1301, 1302, and 1303 is (0, 1, 0) is _greater than the normalized floating gate threshold potential U _fth . Also make it bigger.

W _p2 and w _p3 are determined so as to satisfy the above conditions. In the specific example shown in FIG. 14, w _p2 = 2 and w _p3 = 1.

  Further, in the pre-inverter 1302, by inputting two binary signals from the two second input signal terminals input2 [21] and input2 [22], the input vector (0, 0) and four threshold values are input. A region between (1, 0), a region between input vectors (1, 0) and (0, 1), and a region between input vectors (0, 1) and (1, 1). And an area larger than the input vector (1, 1).

  In the pre-inverter 1303, by inputting two binary signals from the two second input signal terminals input2 [31] and input2 [32], the input vectors (0, 0) and (1 , 0), an area between the input vectors (0, 1) and (1, 1), and an area larger than the input vector (1, 1).

  As described above, by determining the ratio of the input gate capacitance of the main inverter 1300 and the threshold values of the pre-inverters 1301, 1302, and 1303, an arbitrary logical function can be realized when the number of elements is k = 2. it can.

[Specific configuration data]
FIG. 15 shows a case where eight logic functions are realized by the integrated circuit IC3 shown in FIG. 13 among the 16 logic functions realized by the input variables x ₁ and x ₂ when the number of elements k = 2. FIG. 6 is a diagram showing the relationship between the normalized floating gate potential U _fg and the logical values (Y _p2 , Y _p3 ) of the output signals of the pre-inverters 1302 and 1303.

The normalized floating gate potential U _fg is expressed as 1 when it is larger than the normalized floating gate threshold potential U _fth and is expressed as 0 when it is smaller. The logical value of the output signal of main inverter 1300 is a logical inversion value of normalized floating gate potential U _fg in FIG.

  In the integrated circuit IC3, as shown in FIG. 14, when the input vector is (0, 0), only the logical value of the output signal of the pre-inverter 1301 is only the logical value of the output signal of the main inverter 1300. FIG. 15 shows only the case where the logical value of the output signal of the pre-inverter 1301 is zero.

In order to make the normalized floating gate potential U _fg larger than the normalized floating gate threshold potential U _{fth in the} input vector (0, 0), it is only necessary to set the logical value of the output signal of the pre-inverter 1301 to 1. It does not affect the state of other signals. Therefore, being able to realize eight logical functions in FIG. 15 means that all 16 logical functions can be realized.

[Summary when k = 2]
As described above, the integrated circuit IC3 shown in FIG. 13 can realize 16 arbitrary logical functions when the number of elements is k = 2. In the integrated circuit IC1 of the first embodiment, as shown in FIG. In the case where the number of elements k = 2, four pre-inverters 101 are required. However, in the integrated circuit IC3, the same functions as those in the integrated circuit IC1 can be realized by the three pre-inverters 902. Further, by reducing the number of pre-inverters, the area cost of an integrated circuit capable of reconfiguring a logic function function can be reduced.

[Explanation that the above method is a general purpose method]
Next, the design method of the above embodiment is not a special method that can be applied only when the number of elements k = 2, and is always the number of pre-inverters (3/4) · 2 for any k. ^The fact that this is an effective design method using ^k will be described.

FIG. 16 shows an expansion of a design method similar to that of the integrated circuit IC3 to the number of elements k = 3, and the input vector or input charge amount of the main inverter in the designed integrated circuit and the normalized floating gate potential U _fg . It is a figure which shows the relationship.

There are 2 ^k input vectors for k input variables. These input vectors are arranged in ascending order of input charge amount corresponding to the input vector . Four input vectors continuous in the order in which they are arranged are made into one block.

This creates 2 ^k−2 blocks. By applying a method similar to that used in the integrated circuit IC3 to each block, three pre-inverters are used for one block, thereby all logical functions for the input vectors belonging to that block. Can be realized.

In FIG. 16, input vectors (0, 0, 0) to (1, 1, 0) are one block, and input vectors (0, 0, 1) to (1, 1, 1) are also one block. It is. It can be seen that the relationship between the input vector and the normalized floating gate potential U _fg has a periodic structure in units of blocks.

[Summary of this example]
By using the method of the above embodiment, a logical function that can be realized by an arbitrary k input variable can be realized by using (3/4) · 2 ^k pre-inverters.

As shown in the above embodiment, when a plurality of binary signals are used and the logical function function configuration data is expressed in multiple values, the total number of second input signals in the integrated circuit is the total number in the case of the first embodiment. or equal to some 2 ^k, or more or of either. While the number of pre-inverters can be reduced, the number of second input signals increases, and the number of input gate electrodes therefor increases.

However, in general, the former effect is larger between the effect on the area when the number of pre-inverters is reduced and the effect due to the increase in the number of input gate electrodes for inputting the second input signal. Therefore, by using the above embodiment, an integrated circuit capable of reconfiguring a logic function can be realized at a low area cost.

(Sixth embodiment)
In the pre-inverter of the integrated circuit IC3 according to the fifth embodiment, by inputting a plurality of second input signals, a plurality of threshold values viewed from the input signals can be set to arbitrary input charge amounts.

Next, in the above embodiment, even if there is only one input terminal for the second input signal, it is possible to provide the same function by using a physically multi-valued signal as the input signal. Explain that there is .

[Circuit configuration of integrated circuit when multi-value potential is used: Comparison with fifth embodiment]
FIG. 17 is a diagram illustrating a circuit configuration of an integrated circuit IC4 in which a logic function can be reconfigured using a multilevel potential as the second input signal.

  The setting of each input gate capacitance value of the main inverter 1700 of the integrated circuit IC4 and the floating gate threshold potential is the same as that of the integrated circuit IC3 of the fifth embodiment. The integrated circuit IC4 is different from the integrated circuit IC3 in a method of setting the second number of input signal terminals in the pre-inverter 1701 and a plurality of threshold values viewed from the input signal.

[Circuit configuration and operation of pre-inverter]
FIG. 18 is a diagram showing a circuit configuration of the pre-inverter 1701 of the integrated circuit IC4.

  The circuit configuration and operation of this pre-inverter 1701 are compared with the neuron MOS inverter INV3 shown in FIG. 10, and a plurality of binary second input signals are input, and one second of a multi-value potential is input. It will be described that inputting an input signal is equivalent and having the same function.

A second input signal terminals input2 value _{C 2h} of the input gate capacitance connected to [h] of the pre-inverter 1701 shown in FIG. 18, the input gate for inputting the second input signal of the neuron MOS inverter INV3 shown in FIG. 10 The sum of the capacitance values C _2h1 and C _2h2 is set to C _2h1 + C _2h2 .

FIG. 19 is a diagram showing the relationship between the input vector or input charge amount Q _i of the pre-inverter 1701 and the normalized floating gate potential U _fg when the input gate capacitance value is used.

In FIG. 19, C _total = C ₁₁ + C ₁₂ + C _2h + C _gnd , and line 0 is a standardized floating gate when the signal input to the second input signal terminal input 2 [h] is logically 0 The potential U _fg , 1ine1 is the normalized floating gate potential U _fg when the signal input to the second input signal terminal input2 [h] is logically 1.

When the input signal is binary, only two states of 1ine0 and line1 can be taken. However, when multiple values can be used, all values between line0 and line1 can be taken. . As the multi-level, by using logically (1/3), it can be the same _{Q i} in FIG. 11, to set the input threshold charge _{Q i @ th.} That is, the same _{Q i} of FIG. _11, in order to set the _{Q i @ th,} as a second input signal of the pre-inverter 1701 of FIG. 18, 1, (1/3), may be used three values of 0.

In the above embodiment, the same function as when a plurality of binary input signals are used can be realized by using a multilevel potential as the second input signal.

It is a circuit configuration of an integrated circuit capable of reconfiguring a logical function function that realizes 2 ^k arbitrary logical function functions using k input variables, and is a diagram illustrating a circuit configuration based on two-stage logic using a neuron MOS inverter. In the above embodiment, when the number of elements k = 3 and the weight vector is (1, 3, 5), the relationship between the input charge amount Q _i in the main inverter 100 and the normalized floating gate potential U _fg FIG. It is a figure which shows the relationship between the circuit diagram of the jth pre inverter 101, and the capacitance value between each input gate electrode and a floating gate. An input charge amount Q _i in the fifth pre-inverter 101 is a diagram showing the relationship between the normalized floating gate voltage U _fg. When the input vector and the normalized floating gate potential U _fg have the relationship shown in FIG. 4, the relationship between the input vector (or the input charge amount Q _i ) and the logical value of the output signal of the pre-inverter 101 is expressed as follows. FIG. When i = 1, 2, 3, 4, 5, it is a figure which shows the relationship between (alpha) which is 0 <= (alpha) <= 2, and g ((alpha), i). It is a diagram showing the relationship _{S 2} and S _alpha in the case of α = 1.7,1.9,2.0,2.2. It is a figure which shows ₍ beta ₎ and ratio ₍ eta ₎ of sum Sum _{(3) with} respect to sum Sum _{( 2)} in the case of k = 2,3,4. FIG. 2 is a circuit diagram of an integrated circuit IC2 that is an embodiment of the present invention, and is a circuit diagram of the integrated circuit IC2 having the above functions. FIG. 5 is a circuit diagram showing a neuron MOS inverter INV3 having three threshold values as viewed from an input signal. It is a figure which shows the relationship between the input charge amount of neuron MOS inverter INV3 which has said characteristic, and the normalization floating gate electric potential _Ufg . It is a figure which shows the input / output characteristic of the neuron MOS inverter when the input gate capacitance value is set by the above method. FIG. 3 is a circuit diagram showing an integrated circuit IC3 which is an embodiment of the present invention, and is a circuit diagram of the integrated circuit IC3 capable of reconfiguring a logic function function when k = 2. _{Q i} (or input vectors) in the main inverter 1300 of the integrated circuit IC3 shown in FIG. 13 is a diagram showing the relationship between the normalized floating gate voltage _{U fg.} When 16 logic functions realized by the input variables x ₁ and x ₂ when the number of elements k = 2 is realized by the integrated circuit IC3 shown in FIG. It is a figure which shows the relationship between the floating gate electric potential _Ufg and the logical value ( _Yp2 , _Yp3 ) of the output signal of the pre inverters 1302, 1303. The design method similar to that of the integrated circuit IC3 is extended to the number of elements k = 3, and the relationship between the input vector or input charge amount of the main inverter and the normalized floating gate potential _Ufg in the designed integrated circuit is shown. FIG. It is a figure which shows the circuit structure of integrated circuit IC4 which can reconfigure | reconstruct a logic function using a multi-value potential as a 2nd input signal. It is a figure which shows the circuit structure of the pre inverter 1701 of integrated circuit IC4. Is a diagram illustrating the input vector of the pre-inverter 1701 or the input charge amount Q _i,, the relationship between the normalized floating gate voltage U _fg in the case of using the input gate capacitance values. FIG. 10 is a configuration diagram showing an integrated circuit IC1a capable of reconfiguring a logic function function, which is a modification of the integrated circuit IC1 capable of reconfiguring the logic function function. It is a figure which shows the structure of the variable logic part of the conventional LUT (Look-Up Table) type | mold. It is a figure which shows the structure of the conventional variable logic part of a multiplexer (MUX) type. It is a figure which shows the structure of a PLA type variable logic part. FIGS. 24A and 24B are diagrams illustrating a structure of a CMOS inverter using a conventional neuron MOS transistor, in which FIG. 24A is a layout diagram, and FIG. 24B is a cross-sectional view taken along line XX ′ in FIG. FIG. 24 (3) is a sectional view, and FIG. 24 (3) is a circuit diagram of an n-input complementary neuron MOS inverter (neuron MOS inverter). It is a circuit diagram of a CMOS type inverter (neuron MOS inverter) using a conventional neuron MOS transistor, (1) is a diagram described by transistor symbols, and (2) is a diagram described by logical symbols.

Explanation of symbols

IC1, IC1a, IC2, IC3, IC4... Integrated circuit with reconfigurable logic function,
100, 110, 901, 1300, 1700 ... main inverter,
101, 111, 902, 1301, 1302, 1303, 1701... Pre-inverter,
102, 112, 903 ... output buffer,
113 ... NMOSFET for main inverter initialization,
114 ... NMOSFET for pre-inverter initialization,
x _i ... input variables,
V _fg ... floating gate potential,
Q _f ... the total amount of charge accumulated in each input gate capacitance,
V _out ... neuron MOS inverter output signal,
W ... weight vector,
w _i ... element of weight vector W,
X ... input vector,
S _α ... The result of the inner product of the weight vector and the input vector,
S ₂ ... The result of the inner product of the input vector and the weight vector whose power is 2
η: ratio of the sum Sum ₍₃₎ to the sum Sum ₍₂₎ ,
U _fg ... normalized floating gate potential,
U _fth ... normalized floating gate threshold potential,
Q _i ... input charge amount,
Q _isth input threshold charge amount,
C _total ... Sum of all input gate capacitance values,
V _dd ... Power supply potential.

Claims (2)

When an inverter circuit using a neuron MOS transistor or a neuron MOS transistor with a switch is called a neuron MOS inverter,
A two-stage logic function reconfigurable integrated circuit that realizes an arbitrary logic function of k input variables (k is an integer of 2 or more) using the neuron MOS inverter,
The first input gate capacitance between each of the first input signal terminals to which the first input signal as the k input variable is input and the floating gate is a value obtained by standardizing the capacitance value. The input gate capacitance ratios are different from each other, and any number of the first input gate capacitance ratios is set to be different from each other,
For the input vector which is a vector representation of the first input signal, the input vectors when the input charge amounts accumulated in the first input gate capacitance are arranged in ascending order are divided into four blocks in order from one to the smallest. The input vector to which
In the first stage of the integrated circuit capable of reconfiguring the logic function function, a pre-inverter that is a total of (3/4) · 2 ^k neuron MOS transistors is provided for each block .
The second stage of the logic circuit reconfigurable integrated circuit has a main inverter which is the neuron MOS transistor,
The pre-inverter has an upper Symbol first input signal terminals, a set of the first input gate capacitance between the respective floating gates of the first signal input terminal,
At least one of the pre-inverters includes a second input signal terminal to which a signal for selecting one from three or more threshold values is input, and between each of the second input signal terminals and the floating gate. A second input gate capacitance to be set ;
Each of the second input gate capacitances is such that each of the three or more regions composed of four input vectors to the block to which the pre-inverter belongs has any one of the three or more threshold values. The capacity value is set,
An output signal indicating a magnitude relationship between the selected threshold and a normalized floating gate potential determined from an input variable input to the first input signal terminal of the pre-inverter is output to the output terminal;
The main inverter is
A first input signal terminals on reporting,
The first input gate capacitance set between each of the first input signal terminals and the floating gate ;
A terminal connected to the output terminal of each pre-inverter;
A second terminal between the floating gate and a terminal connected to the output terminal of each pre-inverter, which is set to take a value that differs depending on the floating gate threshold potential by a logical combination of the output signals of the pre-inverter. A second input gate capacitance of the input gate capacitance value of
An output terminal;
A logic function reconfigurable integrated circuit comprising: In claim 1,
The second input signal terminal to which a signal for selecting one of the three or more threshold values is input is an input signal controlled by a multi-value expression greater than two values expressed by a plurality of second input signals. A logic function reconfigurable integrated circuit, wherein the integrated circuit is a terminal or an input signal terminal controlled by applying a multilevel potential to one second input signal terminal.

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