JP2004302091A - Programmable light signal processor and method for controlling programmable light signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a programmable light signal processor capable of reducing the electric power consumption of a heater down to requisite minimum and a method for controlling the programmable light signal processor. <P>SOLUTION: All of the sets of 2N+1 set values of such a phase controller 4 by which desired characteristics are obtainable are calculated by a CPU circuit 16 for control and the set of the set values at which the total phase shift set quantity is minimized is selected from the sets of the calculated set values of the phase controller 4 and control is so performed as to execute the phase control based on the group of selected default setting. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

ここで、式中、ａ_ｋ はＮ＋１の各光路を通過してきた信号光の複素振幅を表す。βは光導波路コア１および２の伝搬定数、ω_ｏは周波数特性の周期を表している。また、この式（１）では、電子回路に関するディジタルフィルタ理論でよく行われるように、ｅ^{２πｊω／ω。}を複素数ｚと考えてｈ（ｅ^{２πｊω／ω。} ）を複素平面上の関数ｈ（ｚ）に拡張している。なお、このｚ複素平面上では、周波数関数ｈ（ω）は｜ｚ｜＝１の半径１の円周上の関数とみなされる。
【００４０】
式（１）において、スルー特性ｈ（ｚ）はｚ^−１の多項式で表現されている。この式はＦＩＲ型ディジタルフィルタの伝送特性に等しいことがわかる。この事実は、以下に述べる光フィルタの合成に重要な役割を演じる。同様に、ポート５から入射しポート８から出射される出力光ｆ（ｚ）は下式（２）のように表される。
【００４１】
【数２】

信号処理器は、２入力２出力なので、信号処理器全体の伝送行列Ｓは次式（３）で表される２×２の行列で表現される。
【００４２】
【数３】

ここで、サフィックス＊はパラ共役を表す。
【００４３】
【数４】
ｈ_＊ （ｚ）＝ｈ^＊（１／ｚ^＊） （４）
回路が無損失であると仮定すると、ｈ（ｚ）とｆ（ｚ）の間には、式（３）に示す行列の行列式が１になるという下式（５）で表されるユニモジュラスなユニタリ関係が成立する。
【００４４】
【数５】
ｈ（ｚ）ｈ_＊ （ｚ）＋ｆ（ｚ）ｆ_＊ （ｚ）＝１ （５）
本実施の形態では、クロス特性ｆ（ｚ）が所望特性をもつように、フィルタ設計をおこなった。クロス特性を表す前式（２）の自由度は、複素展開係数の個数がＮ＋１であることから、２Ｎ＋２である。後に述べる最大透過率を１００％に抑える拘束条件を考慮すれば自由度は１減り、２Ｎ＋１となる。
【００４５】
一方、本実施の形態においては、Ｎ＋１個の可変方向性結合器とＮ個の位相制御器より構成される。よって、回路に与えられた自由度は２Ｎ＋１である。この自由度は式（２）の自由度と一致する。このために、式（２）を与えることにより、すべての回路パラメータが原理的には求められる。
【００４６】
（光信号処理装置の構成）
図４は、本発明の実施の形態に係る光信号処理装置の構成を示す図である。光信号処理装置は、ヒータ電力供給回路１５、制御用ＣＰＵ回路１６、非対称マッハツェンダ干渉計１４を直列に多段に並べて接続したラティス構成の石英系基板型光導波路部品を一体のモジュールとして組み込んでいる。
【００４７】
ヒータ電力供給回路１５は、結合率可変な方向性結合器および位相制御器に設けられたヒータに供給する電力を個別に設定可能に制御する。
【００４８】
制御用ＣＰＵ回路１６は、図示しないＣＰＵ、ＲＯＭ、ＲＡＭ等を内部に有し、各ヒータに供給する電力を演算する。ＲＯＭに記憶されているエルビウム添加光ファイバアンプの利得形状と制御プログラムとをＣＰＵに与え、算出された最適な光回路パラメータに基づいてヒータを制御する。
【００４９】
ここで、ＲＯＭとは不揮発性記憶媒体であればよく、半導体リードオンリーメモリの他、フラッシュメモリやハードディスク等が利用可能である。
【００５０】
次に、図５に示すフローチャートを参照して、光信号処理装置の動作を説明する。なお、図５に示すフローチャートは、制御用ＣＰＵ回路１６に設けられたＲＯＭにプログラムとして記憶されている。また、図６は、あるエルビウム添加光ファイバアンプ（ＥＤＦＡ）の波長に対する相対利得特性を示すグラフである。
【００５１】
本実施の形態では、このような相対利得特性を有する利得等化器の設計例に適用して説明することとする。
【００５２】
まず、ステップＳ１０では、クロス所望伝送特性を近似したｚ^−１多項式ｆ（ｚ）を求め、式（２）に従ってフーリエ展開法などにより複素展開係数ｂ_ｋ を算出する。なお、展開項数をＮとする。
【００５３】
次いで、ステップＳ２０では、求めたクロス伝送特性の振幅周波数関数の最大値が１以下となるように規格化する。
【００５４】
次いで、ステップＳ３０では、エネルギー保存則を利用して、クロス特性ｆ（ｚ）よりスルー特性ｈ（ｚ）を求める。すなわち、ｈ（ｚ）の複素展開係数ａ_ｋ を算出する。
【００５５】
ここで、ディジタルフィルタの合成手法により求めた複素展開係数ｂ_ｋを次式（６）により振幅特性の絶対値が１００％を越えないように規格化を行う必要がある。
【００５６】
【数６】

このようにして求めた複素展開係数を有する複素振幅特性を本光信号処理装置のポート５からポート８への出力で実現するように、本光信号処理装置の伝送特性を表すＳ行列を求める。具体的には、Ｓ行列の残りの未知伝達関数ｈ（ｚ）を式（５）のユニモジュラスなユニタリ関係より求める。ｈ（ｚ）ｈ_＊ （ｚ）は、ユニモジュラスなユニタリ関係より、式（６）で規格化したｆ（ｚ）を用い、さらに、ｚに関する一次式の積の形に展開することにより次式（７）で表される。
【００５７】
【数７】

この式（７）中、ａ_０は既知であるｆ（ｚ）の複素展開係数ｂ_０と同じ位相をもたすようにとると、式（８）のように求められる。
【００５８】
【数８】

このとき、式（７）において、ｈ（ｚ）とｈ_＊（ｚ）の積の形で表される必要性から、右辺の多項式の零点は｛α_ｋ ，１／α_ｋ ^＊｝というＮ個のペアとして求められる。ｈ（ｚ）を求める際、ｈ（ｚ）の多項式は｛α_ｋ ，１／α_ｋ ^＊｝の根のペアの内どちらか一方を根として持っている必要があるので、この根の選択の仕方にともない、ｈ（ｚ）は２^Ｎ 個の解を持つ。
【００５９】
これら２^Ｎ 個のｈ（ｚ）の解は、振幅特性はともに等しく、異なる位相特性を持つ。全体としてｆ（ｚ）が共通でｈ（ｚ）が異なるＳ行列が２^Ｎ 個存在し、結果として、２^Ｎ 種類の回路パラメータが求まる。ただし、この２^Ｎ 個のいずれの回路パラメータで回路を作製しても、クロス特性は同一な特性ｆ（ｚ）になる。
【００６０】
ここでは、２^Ｎ 個のｈ（ｚ）に対してそれぞれ整数の番号を１から順に付与し、順番に１個の解を選択する。
【００６１】
｛α_ｋ，１／α_ｋ ^＊｝というＮ組の解からそれぞれ任意の１個を選択することで２^Ｎ セットの解が存在するが、それを順番に選択する。この選択した解から求めたｈ（Ｚ）及びｆ（ｚ）、すなわちａ_ｋ 及びｂ_ｋ より、２行２列の伝送行列を完成させる。
【００６２】
次いで、ステップＳ４０では、この伝送行列よりｋ段目の単位構成を表すｋ番目の単位伝送行列を分解する。ｋ番目の単位伝送行列がユニタリ性を持つ条件より、ｋ段目の単位回路を構成する可変方向性結合器の結合率と、非対称マッハツェンダ干渉計上の位相制御器の位相シフト量φ_ｋ を求める。可変方向性結合器の結合率から、可変方向性結合器の位相制御器の位相シフト量θ_ｋ を求める。
【００６３】
ここで、ステップＳ５０では、全段の分解が済んだか否かを判断する。全段の分解が済んでない場合には、ステップＳ４０に戻り、上述した処理を繰り返す。
【００６４】
一方、全段の分解が済んだ場合には、ステップＳ６０に進み、全可変方向性結合器の位相制御器の位相シフト量θ_ｋ と、非対称マッハツェンダ干渉計上の全位相制御器の位相シフト量φ_ｋ の算出を完了する。
【００６５】
次いで、ステップＳ７０では、全段の位相シフト量θ_ｋ と位相シフト量φ_ｋ とから、ヒータに供給すべき電力量の合計を算出する。ＲＡＭ上に記憶されている前回までの計算結果と比較し最小であれば全段の位相シフト量θ_ｋ と位相シフト量φ_ｋ とをＲＡＭに保持しておく。
【００６６】
ここで、ステップＳ８０では、２^Ｎセットの計算が済んだか否かを判断する。
【００６７】
２^Ｎセットの計算が済んでない場合には、ステップＳ３０に戻り、上述した処理を繰り返す。
【００６８】
２^Ｎセットの計算が済んだ場合には、ステップＳ９０に進み、ヒータに供給すべき電力が最小であった計算結果の全段の位相シフト量θ_ｋ と位相シフト量φ_ｋ とを採用し、全段の位相シフト量θ_ｋ と位相シフト量φ_ｋに基づいてヒータ電力供給回路１５を制御する。具体的には、制御用ＣＰＵ回路１６はＤ／Ａコンバータ回路によりヒータ電力供給回路１５に対してリファレンス電圧を出力する。ヒータ電力供給回路１５はこのリファレンス電圧に応じてヒータに供給する電圧を決定する回路となっており、これによりヒータに所望の電力を供給できる構成となっている。
【００６９】
このように、所望の特性が得られるような位相制御器の２Ｎ＋１個の設定値の組を全て算出し、算出された位相制御器の設定値の組から合計の位相シフト設定量が最小になる設定値の組を選択し、選択された設定値の組に基づいて、位相制御を実施するように制御することで、ヒータの消費電力量を必要最小限の消費電力まで削減することができる。
【００７０】
図７に、図６をターゲット関数としてフーリエ級数展開で求めたｆ（ｚ）の展開係数と、本発明の持徴である「合計の電力が最小となるように２^Ｎ 個の解の中から選択した最適な解」であるような、規格化されたｆ（ｚ）より求めたｈ（ｚ）の展開係数ａ_ｋ 、可変方向性結合器の位相制御器の位相シフト量θ_ｋ 、非対称マッハツェンダ干渉計上の位相制御器の位相シフト量φ_ｋ とを示す。なお、設計中心波長を１５４７ｎｍ、Ｆｒｅｅ Ｓｐｅｃｔｒａｌ Ｒａｎｇｅ（ＦＳＲ）を約５４００ＧＨｚとし、非対称マッハツェンダ干渉計の遅延アームの遅延量を０．１８６ｐｓとした。
【００７１】
このとき、設計されたクロスポート出力の透過損失特性は、図８に示すような特性になった。また、利得等化残差は、図９に示すように、２６ｎｍもの広帯域で０．１９ｄＢｐ−ｐであった。また、設計上の過剰損失は０．５５ｄＢであった。
【００７２】
（従来の技術との比較）
本実施の形態における特徴は、２^Ｎ 個の解全てを求め、その全てについて必要電力量を算出し、電力最小となる解を選択することにある。
【００７３】
ここで、本実施の形態における特徴を詳細に検討するとともに、解の選択基準を持たなかった従来の技術との比較検討を試みる。
【００７４】
図１０に、Ｎ＝１５である上記実施例において、利得等化器の設計過程で得られる１５組の３０個の解を｛α_ｋ，１／α_ｋ ^＊｝の根のペアがわかる形で示す。
【００７５】
この各ペアの任意の片方を選択した２^１５通りの組み合わせの全て（３２，７６８通り）について、ｈ（ｚ）の展開係数ａ_ｋ を求め、可変方向性結合器の位相制御器の位相シフト量θ_ｋ 、非対称マッハツェンダ干渉計上の位相制御器の位相シフト量φ_ｋ とに変換し、その必要電力量を求めた。
【００７６】
次に、２^１５通りすべてにおける必要電力量の分布を図１１にヒストグラムで示す。
【００７７】
ここでは、θ_ｋ 、φ_ｋ ともに０〜２πの位相シフト量に変換し、３１個の位相制御器すべてについて合計している。横軸は、「３１個の位相制御器すべての位相シフト量が２πのときに１」になるように換算している。
【００７８】
この中で、必要電力量が最小となったのは、図７に示した実施例であり、（１Ｂ，２Ｂ，３Ｂ，４Ｂ，５Ｂ，６Ｂ，７Ｂ，８Ｂ，９Ｂ，１０Ｂ，１１Ａ，１２Ｂ，１３Ｂ，１４Ａ，１５Ｂ）を解として選択した場合であり、この時の合計必要電力量は図１１に示す正規化電力量でいうと０．１２３である。これは、１個の位相制御器を２πシフトさせるのに必要な電力が４００ｍＷであるとすると、１，５２５ｍＷに相当する。
【００７９】
また、逆に、必要電力量が最大となったのは、（１Ｂ，２Ａ，３Ａ，４Ａ，５Ａ，６Ａ，７Ａ，８Ｂ，９Ａ，１０Ｂ，１１Ｂ，１２Ａ，１３Ａ，１４Ａ，１５Ｂ）を解として選択した場合であり、この時の合計必要電力量は正規化電力量で０．４５８であり、５，６８０ｍＷに相当する。
【００８０】
また、図１１で、正規化電力量の平均値は０．３１３であり、これは３，８８０ｍＷに相当する。
【００８１】
よって、本発明により、通常で３，３８０ｍＷ、最悪の場合で５，６８０ｍＷもの電力を従来必要としていたものが、１，５２５ｍＷに削減できたといえる。
【００８２】
参考として、適当に解を選択した場合の位相シフト量θ_ｋ 、φ _ｋ を図１２の比較例１、比較例２に、前述の必要電力量が最大となった（１Ｂ，２Ａ，３Ａ，４Ａ，５Ａ，６Ａ，７Ａ，８Ｂ，９Ａ，１０Ｂ，１１Ｂ，１２Ａ，１３Ａ，１４Ａ，１５Ｂ）を解として選択した場合の位相シフト量θ_ｋ 、φ _ｋ を比較例３に示す。比較例１が正規化電力量０．２９４で３，６４５ｍＷ相当、比較例２が正規化電力量０．２９８で３，６９５ｍＷ相当である。
【００８３】
なお、第１の実施の形態では、エルビウム添加光ファイバアンプの利得形状を予めデータテーブルとして制御用ＣＰＵ回路１６に与えたが、タップカプラとスペクトラムアナライザ、あるいはタップカプラと波長分波器とフォトダイオードなどを用いて光信号の状態を適宜検出し、その結果を制御用ＣＰＵ回路１６にフィードバック入力することによって自動利得等化器を構成するようにしても良い。
【００８４】
また、本発明は、位相制御器を光導波路の両方のアームに形成したものに対しても適用可能である。さらに、本発明は、電気光学効果を利用するラティス型プログラマブル光信号処理器に適用可能であり、高い電圧を必要としなくなるため回路が簡単になるという利点がある。
【００８５】
（第２の実施の形態）
図１３は、本発明の第２の実施の形態に係る光信号処理装置を適用することができる光信号処理器の構成を示す図である。
【００８６】
図１３に示すように、光信号処理器は、２本の光導波路コア１，２とこの２本の光導波路コア１，２をＮ＋１カ所の異なる位置で結合するＮ＋１個の結合率可変な方向性結合器３よりなる構成を有し、全体として非対称マッハツェンダ干渉計１４を直列に多段に並べて接続したラティス構成を有している。各非対称マッハツェンダ干渉計１４を構成する２本の光導波路コアはそれぞれ一定の光路長差を持ち、光導波路コア上の両方に所望の位相シフトを施す位相制御器４を配した構成を取っている。なお、図中、符号５，６は入力ポートであり、７，８は出力ポートである。
【００８７】
図１４は、図１３に示した光信号処理器のＡ−Ａ′における断面を表している。ここで、光導波路の製造工程について説明する。
【００８８】
光部品であるラティス型のプログラマブル光信号処理器は、石英系基板型光導波路からなり、シリコンウエハ上にプラズマＣＶＤ、フォトリソグラフィ、ドライエッチング、スパッタリングの各工程によって埋め込み型光導波路が形成されている。具体的には、以下のようになる。
【００８９】
第１工程では、プラズマＣＶＤ装置を用いて１ｍｍ厚のシリコンウエハ１２上に石英ガラス膜を堆積させ、下クラッドガラス層１３を形成する。
【００９０】
第２工程では、プラズマＣＶＤ装置を用いて下クラッド層の上にゲルマニウムドープ石英ガラス膜を堆積させ、コア層を形成する。
【００９１】
第３工程では、スパッタリング装置を用いてコア層の上にコアエッチング時のマスクとなるべき金属薄膜を形成する。この金属薄膜には、シリコン、クロム、タングステンシリサイド等を用いることができる。
【００９２】
第４工程では、金層薄膜層の上にフォトレジストを塗布しておき、コアパターンのガラスフォトマスクにてフォトリソ工程で露光・現像する。
【００９３】
第５工程では、ドライエッチングによりまずフォトレジストをエッチングマスクとして金属薄膜をエッチングし、次に金属薄膜をエッチングマスクとしてコア層をエッチングする。残ったフォトレジスト・金属薄膜は除去する。
【００９４】
第６工程では、プラズマＣＶＤ装置を用いて下クラッド層・コア層の上に石英ガラス膜を堆積させ、上クラッドガラス層３１を形成する。この石英ガラス膜としてボロン・リンドープ石英ガラス膜を用いることもできる。
【００９５】
次に、その表面に金属薄膜ヒータ４−５，４−６を作製した。金属薄膜ヒータ４−５，４−６は、ニクロムをスパッタリングしたものであり、光導波路上の少なくとも一方に所望の位相シフトを施す位相制御器４である。ワイヤボンディング工程を行うため、ニクロム層の表面にはごく薄く金をスパッタリングした。
【００９６】
このようにしてウエハが完成し、その後、ダイシング装置を用いてウエハを切断し、さらに、研削加工機・研磨機等の各種加工機を用いてチップ化した。次いで、別途作製した光ファイバアレイと調心接続し、接着剤を塗布して固定した。さらに、ケースに固定し、金ワイヤボンディングによりニクロムヒータ４−５，４−６と外部の電極とを接続した。
【００９７】
ここで、作製された光導波路コア１，２は単一モードになるようにコアサイズが決定された。位相制御器４は、石英薄膜の上にニクロムのヒータを形成することにより作製した。ヒータを加熱すると、石英薄膜の屈折率が変化し、導波路１，２の光路長を制御することが可能となる。
【００９８】
本実施の形態では、２本の導波路１および２の両方に位相制御器４を構成しているが、これは、一方のみでも制御可能である。ただし、両方の導波路１，２上に形成することの長所は、一方のみの場合、位相を制御するために、位相制御器４には０〜２πの位相変化を要求するが、両方にある場合には、それぞれの位相制御器４，４に要求される位相変化量は０〜πと、半分に抑えることができる点にある。
【００９９】
（光信号処理装置の構成）
図１５は、第２の実施の形態に係る光信号処理装置の構成を示す図である。光信号処理装置は、ヒータ電力供給回路１５、制御用ＣＰＵ回路１６、非対称マッハツェンダ干渉計１４を直列に多段に並べて接続したラティス構成の石英系基板型光導波路部品を一体のモジュールとして組み込んでおり、これらは第１の実施の形態に示す構成と同様であるので、その説明を省略する。
【０１００】
また、光信号処理装置の動作は、図５に示すフローチャートにより同様に説明できるので、その説明を省略する。
【０１０１】
本実施の形態においても、所望の特性が得られるような位相制御器の２Ｎ＋１個の設定値の組を全て算出し、算出された位相制御器の設定値の組から合計の位相シフト設定量が最小になる設定値の組を選択し、選択された設定値の組に基づいて、位相制御を実施するように制御することで、ヒータの消費電力量を必要最小限の消費電力まで削減することができる。
【０１０２】
【発明の効果】
請求項１及び請求項２記載の本発明によれば、所望の特性が得られるような２Ｎ＋１個の位相制御器の設定値の組を全て算出し、算出された位相制御器の設定値の組から合計の位相シフト設定量が最小になる設定値の組を選択し、選択された設定値の組に基づいて、位相制御を実施するように制御することで、ヒータの消費電力量を必要最小限の消費電力まで削減することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態に係る光信号処理器を示す回路構成図である。
【図２】図１に示すＡ−Ａ′線に沿う断面図である。
【図３】本発明の第１の実施の形態に係る光信号処理器を構成する可変方向性結合を示す回路構成図である。
【図４】本発明の第１の実施の形態に係る光信号処理装置の回路構成図である。
【図５】本発明の第１の実施の形態に係る光信号処理装置の制御手順を示すフローチャートである。
【図６】エルビウム添加光ファイバアンプの波長に対する相対利得特性を示すグラフの一例である。
【図７】本発明の第１の実施の形態に係る光信号処理装置により図６に示した相対利得特性を有するエルビウム添加光ファイバアンプに対する利得等化フィルタを構成する場合の展開係数と合計の電力が最小となるように選択した最適な解に基づく各位相制御器の位相シフト量を示す表である。
【図８】本発明の第１の実施の形態に係る光信号処理装置に図７の位相シフト量を設定することにより利得等化フィルタを構成する場合の設計されたクロスポート出力の透過損失特性を示すグラフである。
【図９】本発明の第１の実施の形態に係る光信号処理装置により形成されるフィルタの利得等化残差を示すグラフである。
【図１０】本発明の第１の実施の形態に係る光信号処理装置により算出された１５組３０個の根を示す表である。
【図１１】本発明の第１の実施の形態に係る光信号処理装置における必要電力量の分布を示すヒストグラムである。
【図１２】本発明の第１の実施の形態に係る光信号処理装置により算出された３１個の位相制御器の位相シフト量を表す３つの比較例を示す表である。
【図１３】本発明の第２の実施の形態に係る光信号処理器を示す回路構成図である。
【図１４】図１に示すＡ−Ａ′線に沿う断面図である。
【図１５】本発明の第２の実施の形態に係る光信号処理装置の回路構成図である。
【符号の説明】
１，２ 光導波路コア
３ 正および負の振幅結合率をもつ可変方向性結合器
４ 位相制御器
５，６ 入力ポート
７，８ 出力ポート
９ 正および負の振幅結合率をもつ３ｄＢ方向性結合器
１２ シリコン基板
１３ 下クラッドガラス層
１４ 非対称マッハツェンダ干渉計
１５ ヒータ電力供給回路
１６ 制御用ＣＰＵ回路
１７ ヒータ用電源線
２０ 検知器
２２ 参照光用光源
３１ 上クラッドガラス層[0001]
TECHNICAL FIELD OF THE INVENTION
INDUSTRIAL APPLICABILITY The present invention is useful in the field of optical communication and optical information processing such as optical communication, optical switching, and optical computing, and particularly as a variable optical filter that dynamically realizes an arbitrary shape in a high-density wavelength division multiplexing optical communication system. The present invention relates to a programmable optical signal processing device capable of reducing power consumption of a lattice-type programmable optical signal processor suitable for use and suppressing heat generation, and a method of controlling the programmable optical signal processing device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as one of optical signal processing apparatuses, a lattice-type optical signal processor in which asymmetric Mach-Zehnder interferometers are connected in series is disclosed in Patent Document 1 and Non-Patent Document 1.
[0003]
In these methods, it is possible to determine an optical circuit parameter by an optical circuit synthesis method similar to a design method of a digital filter without feedback called a FIR (Finite Impulse Response) type, and realize an arbitrary transfer characteristic. In fact, the above-mentioned document discloses an embodiment of a Chebyshev type optical frequency filter, a multi-channel optical frequency selector, and an optical group delay equalizer.
[0004]
This lattice type optical signal processor is composed of LiNbO₃ Although it can be realized by using an electro-optical effect material such as an organic optical material or the like, in many cases, it is realized by a quartz-based substrate type optical waveguide, and the thermo-optical effect is used for phase control. This is because the silica-based substrate type optical waveguide is suitable for connection with a general communication optical fiber and has excellent reliability.
[0005]
In a lattice-type optical signal processor using a silica-based substrate-type optical waveguide utilizing the thermo-optic effect described above, power is applied to a metal thin-film heater formed on the cladding surface of an embedded optical waveguide, and the heat generated there is used. And phase control is performed.
[0006]
[Patent Document 1]
JP-A-7-281215
[0007]
[Non-patent document 1]
Kaname Jinguji and Masao Kawachi, “Synthesis of Coherent Two-Port Lattice-Form Optical Delay-Line Circuit, 73-Journey, One-Thirty-Night Life.
[0008]
[Problems to be solved by the invention]
However, since the power required for the metal thin-film heater is large and the required number of metal thin-film heaters is large, a technique for suppressing the power consumption and heat generation of the lattice-type optical signal processor from the viewpoint of high-density mounting of modules is desired. It had been.
[0009]
For example, as disclosed in each embodiment of Patent Document 1, when a 23-stage lattice-type optical signal processor is configured, in order to dynamically realize an arbitrary transfer characteristic, variable directional coupling is required. Phase shift θ_k24 phase controllers for controlling the phase shift amount φ of the asymmetric Mach-Zehnder interferometer constituting the delay circuit_k  , And a total of 47 metal thin film heaters are required as a phase controller for controlling the temperature.
[0010]
It is also reported that when synthesizing an optical lattice circuit in which asymmetric Mach-Zehnder interferometers are connected in series, there are a plurality of circuit parameter selection methods for achieving the same characteristics.
[0011]
For example, as described in paragraph [0054] of Patent Document 1, when a through-port output characteristic h (z) is obtained by an N-stage optical lattice circuit, its polynomial is represented by ｛α._k, 1 / α_k ^*Since it is necessary to have either one of the root pairs of｝ as the root, h (z) is 2^N  You will have solutions. This 2^N  Regardless of which of the solutions is selected, a desired cross-port output characteristic f (z) is obtained.
[0012]
By the way, this 2^N  The selection criterion for individual solutions is described in Patent Literature 1 "Of course, h (z) is selected by appropriately providing selection criteria such as a low element sensitivity, an appropriate phase characteristic, and the like. In the case where the characteristics of h (z) are to be taken into account, it is suggested that a desired h (z) can be obtained by selecting according to the standard. ing.
[0013]
However, in practice, the characteristic of f (z) is the most important, and the same f (z) can be obtained regardless of which solution is selected. Therefore, an appropriate one solution is usually selected without any criterion. It had been. As a result, how much power is consumed in the range from the minimum to the maximum of the power applied to the heater is left to the choice of the solution.
[0014]
Therefore, it has been desired to select an optimal solution that minimizes the total power applied to the heater.
[0015]
The present invention has been made in view of the above, and an object of the present invention is to provide a programmable optical signal processing apparatus and a method for controlling the programmable optical signal processing apparatus, which can reduce the power consumption of a heater to a required minimum power consumption. Is to provide.
[0016]
[Means for Solving the Problems]
In order to solve the above problem, the invention according to claim 1 includes two optical waveguides and N + 1 positive and negative amplitude coupling ratios that can couple the two optical waveguides at N + 1 different positions. And a phase controller for setting the coupling ratio of the variable directional coupler to a desired value, and the two optical waveguides at N locations sandwiched between the (N + 1) variable directional couplers have the same optical path. A phase controller having a length difference and performing a desired phase shift on at least one of the two optical waveguides at N locations. In a programmable optical signal processing device that controls so as to perform an optical filtering process having the following characteristics, a calculating unit that calculates all sets of the set values of the phase controller so as to obtain a desired characteristic; Selecting means for selecting a set of set values that minimizes the total phase shift set amount from the set of set values of the phase controller, and performing phase control based on the set of set values selected by the select means. The gist of the present invention is to provide a control means for performing the control.
[0017]
According to a second aspect of the present invention, in order to solve the above problem, two optical waveguides and N + 1 positive and negative amplitude coupling ratios for coupling the two optical waveguides at N + 1 different positions are variable. And a phase controller for setting the coupling ratio of the variable directional coupler to a desired value, and the two optical waveguides at N locations sandwiched between the (N + 1) variable directional couplers have the same optical path. A phase controller having a length difference and performing a desired phase shift on at least one of the two optical waveguides at N locations. A control method of a programmable optical signal processing device for controlling to perform an optical filtering process having characteristics of: a calculating step of calculating all sets of set values of the phase controller so as to obtain desired characteristics; A selection step of selecting a set of set values that minimizes the total phase shift set amount from a set of set values of the phase controller calculated by the step, and a setting step based on the set of set values selected by the selection step. And a control step of performing control to execute the phase control.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0019]
(First Embodiment)
FIG. 1 is a diagram showing a configuration of an optical signal processor to which the optical signal processing device according to the first embodiment of the present invention can be applied.
[0020]
As shown in FIG. 1, the optical signal processor includes two optical waveguide cores 1 and 2 and N + 1 coupling ratio variable directions for coupling the two optical waveguide cores 1 and 2 at N + 1 different positions. And has a lattice configuration in which asymmetric Mach-Zehnder interferometers 14 are arranged in series and connected in multiple stages as a whole. The two optical waveguide cores constituting each asymmetric Mach-Zehnder interferometer 14 have a constant optical path length difference, and have a configuration in which a phase controller 4 for performing a desired phase shift on the optical waveguide core 1 is arranged. In the drawing, reference numerals 5 and 6 are input ports, and reference numerals 7 and 8 are output ports.
[0021]
In the present embodiment, the optical signal processor is constituted by a quartz-based substrate type optical waveguide excellent in mass productivity.
[0022]
(Manufacturing process of optical waveguide)
FIG. 2 shows a cross section taken along the line AA 'of the optical signal processor shown in FIG. Here, the manufacturing process of the optical waveguide will be described.
[0023]
A lattice-type programmable optical signal processor, which is an optical component, comprises a quartz-based substrate-type optical waveguide, and a buried optical waveguide is formed on a silicon wafer by plasma CVD, photolithography, dry etching, and sputtering. . Specifically, it is as follows.
[0024]
In the first step, a quartz glass film is deposited on a silicon wafer 12 having a thickness of 1 mm using a plasma CVD apparatus to form a lower clad glass layer 13.
[0025]
In the second step, a germanium-doped quartz glass film is deposited on the lower cladding layer using a plasma CVD apparatus to form a core layer.
[0026]
In the third step, a metal thin film to be used as a mask during core etching is formed on the core layer by using a sputtering apparatus. For this metal thin film, silicon, chromium, tungsten silicide, or the like can be used.
[0027]
In the fourth step, a photoresist is applied on the gold thin film layer, and is exposed and developed in a photolithography step using a glass photomask having a core pattern.
[0028]
In the fifth step, the metal thin film is etched by dry etching using the photoresist as an etching mask, and then the core layer is etched using the metal thin film as an etching mask. The remaining photoresist and metal thin film are removed.
[0029]
In the sixth step, a quartz glass film is deposited on the lower cladding layer / core layer by using a plasma CVD apparatus to form an upper cladding glass layer 31. As this quartz glass film, a boron / phosphorus-doped quartz glass film can be used.
[0030]
Next, a metal thin-film heater 4-5 was formed on the surface. The metal thin-film heaters 4-5 are sputtered with nichrome, and are phase controllers 4 for performing a desired phase shift on at least one of the optical waveguides. In order to perform the wire bonding process, gold was sputtered very thinly on the surface of the nichrome layer.
[0031]
Thus, the wafer was completed. Thereafter, the wafer was cut using a dicing apparatus, and further cut into chips using various processing machines such as a grinding machine and a polishing machine. Next, the optical fiber array was aligned and connected to an optical fiber array separately manufactured, and was fixed by applying an adhesive. Further, the chromium heater 4-5 was fixed to the case, and the external electrodes were connected by gold wire bonding.
[0032]
Here, the core sizes of the manufactured optical waveguide cores 1 and 2 were determined so as to be in a single mode. The phase controller 4 was manufactured by forming a nichrome heater on a quartz thin film. When the heater is heated, the refractive index of the quartz thin film changes, and the optical path length of the waveguide 1 can be controlled.
[0033]
In the present embodiment, a phase controller 4 is configured and controlled on one of the waveguides 1. However, when formed on the waveguide 1, the phase controller 4 requires a phase change of 0 to 2π in order to control the phase. In the present embodiment, the phase controller 4 is configured on one of the waveguides 1. However, instead of configuring the phase controller 4 only on the waveguide 1, the phase controller 4 is configured only on the waveguide 2. May be configured.
[0034]
FIG. 3 shows the variable directional coupler 3 used in the present embodiment. This constitutes a symmetric Mach-Zehnder interferometer composed of two optical waveguide cores 1 and 2 having the same optical path length and 3 dB directional couplers 9-1 and 2-1 disposed at both ends thereof. On each of the optical waveguide cores 1 and 2, phase controllers 4x and 4y made of a nichrome heater are arranged. As for the phase controllers 4x and 4y, similarly to the above, a variable directional coupler is formed even if a heater is provided only on one waveguide. Then, the coupling ratio can be changed from 100% to 0% by changing the phase difference between the two optical waveguide cores by 0 to π by this phase controller.
[0035]
In the variable directional coupler 3 having the symmetric Mach-Zehnder configuration having the same optical path length, when the phase shift amount of the phase controller 4 provided therein is 0, the directional coupler has 100% coupling, and the phase shift amount is At π, it becomes a directional coupler with 0% coupling. When the phase shift amount of the phase controller 4 is 0, the optical path lengths of the two waveguides 1 and 2 can be shifted in advance by a half wavelength so that the directional coupler has 0% coupling. Although not adopted here, the 3 dB directional couplers 9-1 and 9-1 constituting the variable directional coupler 3 are the same as the variable directional coupler 3 having the symmetric Mach-Zehnder interferometer configuration shown in FIG. It is also possible to replace with a coupler of the configuration. In order for the variable directional coupler to be completely variable from 0 to 100% coupling as designed, the coupling ratio of the 3 dB coupler constituting the coupler needs to be 3 dB with considerable accuracy. In order to accurately set the coupling rate of the 3 dB coupler to 3 dB, the 3 dB coupler is replaced with a variable directional coupler. This is because the variable directional coupler 3 having a symmetric Mach-Zehnder interferometer configuration shown in FIG. 3 can realize a coupling ratio of 3 dB even if the coupling ratio of the 3 dB coupler is slightly deviated from 3 dB. We are using.
[0036]
Note that the optical signal processor described in the present embodiment utilizes the coherent interference phenomenon of light, so that the signal light must be coherent light.
[0037]
(Principle related to cross characteristics of variable directional coupler)
In FIG. 1, a signal light incident from an input port 5 passes through each asymmetric Mach-Zehnder interferometer 14 and is output to output ports 7 and 8. At this time, the signal light is split by each variable directional coupler. For example, the signal light traveling the shortest optical path passes through the waveguides 2-1, 2-2, ..., 2-N. The signal light traveling the longest optical path passes through the waveguides 1-1, 1-2,..., 1-N. As described above, the output lights from the ports 7 and 8 are expressed as the sum of the signal lights passing through various optical paths. The physical optical path through which the optical signal passes is 2^N  Although there are several paths, those having the same optical path length are counted as one optical path.
[0038]
Here, when the optical path length difference between the two optical waveguide cores of each asymmetric Mach-Zehnder interferometer 14 is represented by ΔL, the signal light is any one of N + 1 optical paths having optical path lengths of 0, ΔL, 2ΔL,. Will pass through. Therefore, the complex amplitude of the output light from the port 7 is represented by the following equation (1).
[0039]
(Equation 1)

Where a_kRepresents the complex amplitude of the signal light passing through each of the N + 1 optical paths. β is the propagation constant of the optical waveguide cores 1 and 2, ω_oRepresents the period of the frequency characteristic. In this equation (1), as is often done in digital filter theory for electronic circuits, e^{2πjω / ω.}As a complex number z, h (e^{2πjω / ω.} ) Is extended to a function h (z) on the complex plane. Note that on this z complex plane, the frequency function h (ω) is regarded as a function on the circumference of the radius 1 of | z | = 1.
[0040]
In equation (1), the through characteristic h (z) is z^-1Is represented by the following polynomial. It can be seen that this equation is equal to the transmission characteristic of the FIR digital filter. This fact plays an important role in the synthesis of the optical filter described below. Similarly, output light f (z) entering from port 5 and exiting from port 8 is represented by the following equation (2).
[0041]
(Equation 2)

Since the signal processor has two inputs and two outputs, the transmission matrix S of the entire signal processor is represented by a 2 × 2 matrix expressed by the following equation (3).
[0042]
(Equation 3)

Here, the suffix * represents paraconjugate.
[0043]
(Equation 4)
h_*(Z) = h^*(1 / z^*) (4)
Assuming that the circuit has no loss, a unimodulus expressed by the following equation (5) is obtained between h (z) and f (z), where the determinant of the matrix shown in the equation (3) becomes 1. A simple unitary relationship holds.
[0044]
(Equation 5)
h (z) h_*(Z) + f (z) f_*(Z) = 1 (5)
In the present embodiment, the filter is designed so that the cross characteristic f (z) has a desired characteristic. The degree of freedom of the equation (2) representing the cross characteristic is 2N + 2 since the number of complex expansion coefficients is N + 1. The degree of freedom is reduced by 1 and becomes 2N + 1 by taking into account a constraint condition for suppressing the maximum transmittance to 100%, which will be described later.
[0045]
On the other hand, in the present embodiment, it is composed of N + 1 variable directional couplers and N phase controllers. Therefore, the degree of freedom given to the circuit is 2N + 1. This degree of freedom matches the degree of freedom of equation (2). For this purpose, by giving equation (2), all circuit parameters can in principle be determined.
[0046]
(Configuration of optical signal processing device)
FIG. 4 is a diagram showing a configuration of the optical signal processing device according to the embodiment of the present invention. The optical signal processing device incorporates a lattice-type quartz substrate-type optical waveguide component in which a heater power supply circuit 15, a control CPU circuit 16, and an asymmetric Mach-Zehnder interferometer 14 are arranged and connected in multiple stages in series as an integrated module.
[0047]
The heater power supply circuit 15 controls the power supplied to the heaters provided in the directional coupler having a variable coupling ratio and the phase controller so as to be individually settable.
[0048]
The control CPU circuit 16 has a CPU, a ROM, a RAM, and the like (not shown) therein, and calculates electric power supplied to each heater. The gain shape of the erbium-doped optical fiber amplifier and the control program stored in the ROM are supplied to the CPU, and the heater is controlled based on the calculated optimum optical circuit parameters.
[0049]
Here, the ROM may be a non-volatile storage medium, and a flash memory, a hard disk, or the like can be used in addition to a semiconductor read-only memory.
[0050]
Next, the operation of the optical signal processing device will be described with reference to the flowchart shown in FIG. The flowchart shown in FIG. 5 is stored as a program in a ROM provided in the control CPU circuit 16. FIG. 6 is a graph showing a relative gain characteristic with respect to a wavelength of a certain erbium-doped optical fiber amplifier (EDFA).
[0051]
In the present embodiment, description will be made by applying to a design example of a gain equalizer having such a relative gain characteristic.
[0052]
First, in step S10, z which approximates the desired cross transmission characteristic is used.^-1A polynomial f (z) is obtained, and a complex expansion coefficient b is calculated by Fourier expansion according to the equation (2)._k  Is calculated. The number of expansion terms is N.
[0053]
Next, in step S20, normalization is performed so that the obtained maximum value of the amplitude frequency function of the cross transmission characteristic is 1 or less.
[0054]
Next, in step S30, a through characteristic h (z) is obtained from the cross characteristic f (z) using the law of conservation of energy. That is, the complex expansion coefficient a of h (z)_k  Is calculated.
[0055]
Here, the complex expansion coefficient b obtained by the synthesis method of the digital filter_kNeeds to be normalized by the following equation (6) so that the absolute value of the amplitude characteristic does not exceed 100%.
[0056]
(Equation 6)

An S matrix representing the transmission characteristics of the present optical signal processing device is obtained so that the complex amplitude characteristic having the complex expansion coefficient thus obtained is realized by the output from the port 5 to the port 8 of the present optical signal processing device. Specifically, the remaining unknown transfer function h (z) of the S matrix is obtained from the unimodular unitary relation of Expression (5). h (z) h_*(Z) is expressed by the following equation (7) by using f (z) standardized by the equation (6) from the unimodular unitary relation and further developing it into a linear product of z. You.
[0057]
(Equation 7)

In this equation (7), a₀Is a known complex expansion coefficient b of f (z)₀If the same phase is obtained, it is obtained as shown in Expression (8).
[0058]
(Equation 8)

At this time, in equation (7), h (z) and h_*From the necessity expressed in the form of the product of (z), the zero of the polynomial on the right side is ｛α_k  , 1 / α_k ^*｝ Are obtained as N pairs. When calculating h (z), the polynomial of h (z) is ｛α_k  , 1 / α_k ^*Since it is necessary to have either one of the root pairs of｝ as the root, h (z) is 2^N  Has solutions.
[0059]
These two^N  The solutions of h (z) have equal amplitude characteristics and different phase characteristics. There are two S matrices having the same f (z) and different h (z) as a whole.^N  Exist, resulting in 2^N  The types of circuit parameters are determined. However, this 2^N  Regardless of the circuit parameter, the cross characteristic becomes the same characteristic f (z).
[0060]
Here, 2^N  An integer number is assigned to each of the h (z) in order from 1, and one solution is selected in order.
[0061]
｛Α_k, 1 / α_k ^*By selecting any one of the N sets of solutions｝, 2^N  There is a set of solutions, but we select them in order. H (Z) and f (z) obtained from the selected solution, ie, a_k  And b_k  Thus, a 2-by-2 transmission matrix is completed.
[0062]
Next, in step S40, the k-th unit transmission matrix representing the k-th unit configuration is decomposed from the transmission matrix. From the condition that the k-th unit transmission matrix has unitary property, the coupling ratio of the variable directional coupler constituting the k-th unit circuit and the phase shift amount φ of the phase controller of the asymmetric Mach-Zehnder interferometer_k  Ask for. From the coupling ratio of the variable directional coupler, the phase shift amount θ of the phase controller of the variable directional coupler_k  Ask for.
[0063]
Here, in step S50, it is determined whether or not all stages have been disassembled. If all stages have not been disassembled, the process returns to step S40, and the above-described processing is repeated.
[0064]
On the other hand, if the decomposition of all stages has been completed, the process proceeds to step S60, where the phase shift amount θ of the phase controller of the all variable directional couplers is set._k  And the phase shift φ of all the phase controllers of the asymmetric Mach-Zehnder interferometer_k  Is completed.
[0065]
Next, in step S70, the phase shift amounts θ of all stages_k  And phase shift φ_k  Then, the total amount of electric power to be supplied to the heater is calculated. Compared to the previous calculation result stored in the RAM, if it is the smallest, the phase shift amount θ of all stages_k  And phase shift φ_k  Are stored in the RAM.
[0066]
Here, in step S80, 2^NIt is determined whether the set has been calculated.
[0067]
2^NIf the set has not been calculated, the process returns to step S30, and the above-described processing is repeated.
[0068]
2^NIf the set has been calculated, the process proceeds to step S90, in which the phase shift amounts θ of all the stages in the calculation result in which the power to be supplied to the heater is the minimum are obtained._k  And phase shift φ_kAnd the phase shift amount θ of all stages_k  And phase shift φ_kThe heater power supply circuit 15 is controlled based on Specifically, the control CPU circuit 16 outputs a reference voltage to the heater power supply circuit 15 by a D / A converter circuit. The heater power supply circuit 15 is a circuit that determines a voltage to be supplied to the heater according to the reference voltage, and is configured to be able to supply desired power to the heater.
[0069]
In this way, all sets of 2N + 1 set values of the phase controller that can obtain desired characteristics are calculated, and the total phase shift set amount is minimized from the calculated set of phase controller set values. By selecting a set of set values and performing control so as to perform phase control based on the selected set of set values, the power consumption of the heater can be reduced to the required minimum power consumption.
[0070]
FIG. 7 shows the expansion coefficient of f (z) obtained by Fourier series expansion using FIG.^N  Expansion coefficient a of h (z) obtained from standardized f (z) such that "the optimum solution selected from the number of solutions"_k  , The phase shift amount θ of the phase controller of the variable directional coupler_k  , Phase shift amount φ of phase controller of asymmetric Mach-Zehnder interferometer_k  And The design center wavelength was 1547 nm, the Free Spectral Range (FSR) was about 5400 GHz, and the delay amount of the delay arm of the asymmetric Mach-Zehnder interferometer was 0.186 ps.
[0071]
At this time, the designed transmission loss characteristic of the cross port output is as shown in FIG. Further, the gain equalization residual was 0.19 dBp-p in a wide band of 26 nm as shown in FIG. The excess loss in design was 0.55 dB.
[0072]
(Comparison with conventional technology)
The feature of this embodiment is 2^N  The solution is to find all the solutions, calculate the required amount of power for all of them, and select the solution with the minimum power.
[0073]
Here, the features in the present embodiment will be examined in detail, and a comparison examination with a conventional technique which does not have a solution selection criterion will be attempted.
[0074]
In FIG. 10, in the above embodiment where N = 15, 15 sets of 30 solutions obtained in the process of designing the gain equalizer are represented by ｛α._k, 1 / α_k ^*The root pairs of｝ are shown in such a way that they can be understood.
[0075]
Any one of this pair is selected 2^FifteenThe expansion coefficient a of h (z) for all of the combinations (32,768)_k  And the phase shift amount θ of the phase controller of the variable directional coupler._k  , Phase shift amount φ of phase controller of asymmetric Mach-Zehnder interferometer_k  And the required power was obtained.
[0076]
Next, 2^FifteenFIG. 11 is a histogram showing the distribution of the required power in all the cases.
[0077]
Here, θ_k  , Φ_k  Both are converted into the phase shift amounts of 0 to 2π, and are summed up for all 31 phase controllers. The horizontal axis is converted so as to be “1 when the phase shift amounts of all 31 phase controllers are 2π”.
[0078]
Among these, the required power amount became the smallest in the embodiment shown in FIG. 7, and (1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11A, 12B, 13B, 14A, and 15B) as the solution, and the total required power at this time is 0.123 in terms of the normalized power shown in FIG. This corresponds to 1,525 mW, assuming that the power required to shift one phase controller by 2π is 400 mW.
[0079]
On the other hand, the reason why the required power amount becomes the maximum is that (1B, 2A, 3A, 4A, 5A, 6A, 7A, 8B, 9A, 10B, 11B, 12A, 13A, 14A, 15B) is the solution. In this case, the total required power is 0.458 in normalized power, which is equivalent to 5,680 mW.
[0080]
In FIG. 11, the average value of the normalized power amount is 0.313, which corresponds to 3,880 mW.
[0081]
Therefore, it can be said that the present invention has reduced the power that conventionally required 3,380 mW in the normal case and 5,680 mW in the worst case to 1,525 mW.
[0082]
For reference, the phase shift amount θ when an appropriate solution is selected_k  , Φ_kCompared with Comparative Example 1 and Comparative Example 2 in FIG. 12, the above-mentioned required power amount became the maximum (1B, 2A, 3A, 4A, 5A, 6A, 7A, 8B, 9A, 10B, 11B, 12A, 13A, 14A, 15B) as the solution, the phase shift amount θ_k  , Φ_k  Is shown in Comparative Example 3. Comparative Example 1 has a normalized power amount of 0.294 and corresponds to 3,645 mW, and Comparative Example 2 has a normalized power amount of 0.298 and corresponds to 3,695 mW.
[0083]
In the first embodiment, the gain shape of the erbium-doped optical fiber amplifier is given to the control CPU circuit 16 as a data table in advance. However, the tap coupler and the spectrum analyzer, or the tap coupler, the wavelength demultiplexer, and the photodiode The automatic gain equalizer may be configured by appropriately detecting the state of the optical signal using, for example, and feeding the result back to the control CPU circuit 16.
[0084]
The present invention is also applicable to a case where the phase controller is formed on both arms of the optical waveguide. Further, the present invention is applicable to a lattice type programmable optical signal processor utilizing the electro-optic effect, and has an advantage that a circuit is simplified because a high voltage is not required.
[0085]
(Second embodiment)
FIG. 13 is a diagram illustrating a configuration of an optical signal processor to which the optical signal processing device according to the second embodiment of the present invention can be applied.
[0086]
As shown in FIG. 13, the optical signal processor includes N + 1 optical waveguide cores 1 and 2 and N + 1 coupling ratio variable directions for coupling the two optical waveguide cores 1 and 2 at N + 1 different positions. And has a lattice configuration in which asymmetric Mach-Zehnder interferometers 14 are arranged in series and connected in multiple stages as a whole. Each of the two optical waveguide cores constituting each asymmetric Mach-Zehnder interferometer 14 has a constant optical path length difference, and has a configuration in which a phase controller 4 for performing a desired phase shift on both of the optical waveguide cores is arranged. . In the drawing, reference numerals 5 and 6 are input ports, and reference numerals 7 and 8 are output ports.
[0087]
FIG. 14 illustrates a cross section taken along line AA ′ of the optical signal processor illustrated in FIG. Here, the manufacturing process of the optical waveguide will be described.
[0088]
A lattice-type programmable optical signal processor, which is an optical component, comprises a quartz-based substrate-type optical waveguide, and a buried optical waveguide is formed on a silicon wafer by plasma CVD, photolithography, dry etching, and sputtering. . Specifically, it is as follows.
[0089]
In the first step, a quartz glass film is deposited on a silicon wafer 12 having a thickness of 1 mm using a plasma CVD apparatus to form a lower clad glass layer 13.
[0090]
In the second step, a germanium-doped quartz glass film is deposited on the lower cladding layer using a plasma CVD apparatus to form a core layer.
[0091]
In the third step, a metal thin film to be used as a mask during core etching is formed on the core layer by using a sputtering apparatus. For this metal thin film, silicon, chromium, tungsten silicide, or the like can be used.
[0092]
In the fourth step, a photoresist is applied on the gold thin film layer, and is exposed and developed in a photolithography step using a glass photomask having a core pattern.
[0093]
In the fifth step, the metal thin film is etched by dry etching using the photoresist as an etching mask, and then the core layer is etched using the metal thin film as an etching mask. The remaining photoresist and metal thin film are removed.
[0094]
In the sixth step, a quartz glass film is deposited on the lower cladding layer / core layer by using a plasma CVD apparatus to form an upper cladding glass layer 31. As this quartz glass film, a boron / phosphorus-doped quartz glass film can be used.
[0095]
Next, metal thin film heaters 4-5 and 4-6 were formed on the surface. The metal thin-film heaters 4-5 and 4-6 are sputtered with nichrome, and are phase controllers 4 for performing a desired phase shift on at least one of the optical waveguides. In order to perform the wire bonding process, gold was sputtered very thinly on the surface of the nichrome layer.
[0096]
Thus, the wafer was completed. Thereafter, the wafer was cut using a dicing apparatus, and further cut into chips using various processing machines such as a grinding machine and a polishing machine. Next, the optical fiber array was aligned and connected to an optical fiber array separately manufactured, and was fixed by applying an adhesive. Further, it was fixed to the case, and the nichrome heaters 4-5 and 4-6 were connected to external electrodes by gold wire bonding.
[0097]
Here, the core sizes of the manufactured optical waveguide cores 1 and 2 were determined so as to be in a single mode. The phase controller 4 was manufactured by forming a nichrome heater on a quartz thin film. When the heater is heated, the refractive index of the quartz thin film changes, and the optical path lengths of the waveguides 1 and 2 can be controlled.
[0098]
In the present embodiment, the phase controller 4 is configured in both of the two waveguides 1 and 2, but this can be controlled by only one of them. However, the advantage of forming on both the waveguides 1 and 2 is that, in the case of only one, the phase controller 4 requires a phase change of 0 to 2π in order to control the phase. In this case, the amount of phase change required for each of the phase controllers 4 and 4 can be suppressed to half, from 0 to π.
[0099]
(Configuration of optical signal processing device)
FIG. 15 is a diagram illustrating a configuration of an optical signal processing device according to the second embodiment. The optical signal processing device incorporates a quartz-based substrate-type optical waveguide component having a lattice configuration in which a heater power supply circuit 15, a control CPU circuit 16, and an asymmetric Mach-Zehnder interferometer 14 are connected in series and connected in multiple stages, as an integrated module. Since these are the same as the configuration shown in the first embodiment, the description is omitted.
[0100]
Also, the operation of the optical signal processing device can be described in the same way by referring to the flowchart shown in FIG.
[0101]
Also in the present embodiment, all the 2N + 1 set value sets of the phase controller that can obtain the desired characteristics are calculated, and the total phase shift set amount is calculated from the calculated set value of the phase controller. To reduce the power consumption of the heater to the minimum required power consumption by selecting a set of minimum set values and performing control so that phase control is performed based on the selected set of set values. Can be.
[0102]
【The invention's effect】
According to the first and second aspects of the present invention, all sets of 2N + 1 set values of phase controllers that can obtain desired characteristics are calculated, and the set of calculated set values of phase controllers are calculated. From the set value that minimizes the total phase shift set amount, and controls the phase control based on the selected set value to minimize the power consumption of the heater. Power consumption can be reduced to a minimum.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing an optical signal processor according to a first embodiment of the present invention.
FIG. 2 is a sectional view taken along the line AA 'shown in FIG.
FIG. 3 is a circuit configuration diagram illustrating variable directional coupling included in the optical signal processor according to the first embodiment of the present invention.
FIG. 4 is a circuit configuration diagram of the optical signal processing device according to the first embodiment of the present invention.
FIG. 5 is a flowchart showing a control procedure of the optical signal processing device according to the first embodiment of the present invention.
FIG. 6 is an example of a graph showing relative gain characteristics with respect to wavelength of an erbium-doped optical fiber amplifier.
FIG. 7 shows the sum of the expansion coefficient and the sum when the optical signal processing device according to the first embodiment of the present invention constitutes a gain equalizing filter for an erbium-doped optical fiber amplifier having the relative gain characteristics shown in FIG. 9 is a table showing the amount of phase shift of each phase controller based on an optimal solution selected so as to minimize power.
FIG. 8 is a transmission loss characteristic of a designed cross-port output when a gain equalization filter is configured by setting the phase shift amount of FIG. 7 in the optical signal processing device according to the first embodiment of the present invention; FIG.
FIG. 9 is a graph showing a gain equalization residual of a filter formed by the optical signal processing device according to the first embodiment of the present invention.
FIG. 10 is a table showing 15 sets of 30 roots calculated by the optical signal processing device according to the first embodiment of the present invention.
FIG. 11 is a histogram showing a distribution of required power in the optical signal processing device according to the first embodiment of the present invention.
FIG. 12 is a table showing three comparative examples showing the phase shift amounts of 31 phase controllers calculated by the optical signal processing device according to the first embodiment of the present invention.
FIG. 13 is a circuit configuration diagram showing an optical signal processor according to a second embodiment of the present invention.
FIG. 14 is a cross-sectional view taken along the line AA ′ shown in FIG.
FIG. 15 is a circuit configuration diagram of an optical signal processing device according to a second embodiment of the present invention.
[Explanation of symbols]
1,2 optical waveguide core
3. Variable directional coupler with positive and negative amplitude coupling ratio
4 Phase controller
5, 6 input port
7, 8 output port
9. 3 dB directional coupler with positive and negative amplitude coupling ratio
12 Silicon substrate
13 Lower cladding glass layer
14 Asymmetric Mach-Zehnder interferometer
15 Heater power supply circuit
16 Control CPU circuit
17 Power line for heater
20 detector
22 Reference light source
31 Upper clad glass layer

Claims (2)

Two optical waveguides,
A phase controller for setting the coupling ratio of the N + 1 variable directional couplers having variable positive and negative amplitude coupling ratios for coupling the two optical waveguides at N + 1 different positions to a desired value;
The two optical waveguides at N locations sandwiched between the N + 1 variable directional couplers respectively have the same optical path length difference, and at least one optical waveguide among the two optical waveguides at N locations A phase controller for performing a desired phase shift on the, and, for an optical signal processor of the lattice configuration having, in a programmable optical signal processing device that controls to perform an optical filtering process having desired characteristics,
Calculating means for calculating all sets of set values of the phase controller such that desired characteristics are obtained,
Selecting means for selecting a set of set values that minimizes the total phase shift set amount from the set of phase controller set values calculated by the calculating means;
Control means for controlling the phase control based on the set of setting values selected by the selection means. Two optical waveguides,
A phase controller for setting the coupling ratio of the N + 1 variable directional couplers having variable positive and negative amplitude coupling ratios for coupling the two optical waveguides at N + 1 different positions to a desired value;
The two optical waveguides at N locations sandwiched between the N + 1 variable directional couplers respectively have the same optical path length difference, and at least one optical waveguide among the two optical waveguides at N locations And a phase controller for performing a desired phase shift on the optical signal processor having a lattice configuration having a desired phase shift. ,
A calculating step of calculating all the set of set values of the phase controller such that a desired characteristic is obtained,
A selection step of selecting a set of set values that minimizes the total phase shift set amount from the set of phase controller set values calculated by the calculation step;
A control step of performing control so as to execute phase control based on a set of set values selected in the selection step.

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