JP2004296732A - Ferroelectric memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a ferroelectric memory device that is superior in hydrogen barrier performance. <P>SOLUTION: The ferroelectric memory device (100) is provided with a memory cell array (101) that is formed in a direction where striped upper electrodes (13) and lower electrodes (11) cross each other, and where ferroelectric capacitors are arranged like a matrix in which a ferroelectric film is interposed in an area where at least the upper electrode (13) and the lower electrode (11) cross each other; and a hydrogen barrier film (52) that is formed as to cover the memory cell array (101). The hydrogen barrier film (52) and a wiring layer (51) are located on the same layer, and films are formed for both through the same step. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory device, and more particularly to a technique for manufacturing a ferroelectric memory device having excellent hydrogen barrier characteristics.
[0002]
[Prior art]
Since the characteristics of a ferroelectric capacitor deteriorate when exposed to a reducing atmosphere, conventionally, the deterioration of the characteristics is prevented by, for example, coating the ferroelectric capacitor with a hydrogen barrier film. Among the manufacturing processes of the ferroelectric memory device, the process in which the atmosphere is particularly reduced includes, for example, an interlayer insulating film forming process for separating a ferroelectric capacitor and a wiring layer, an etching process, a passivation film forming process, and the like. . Among them, a hydrogen barrier film is formed so as to cover an aluminum wiring layer wired on an interlayer insulating film, in order to prevent reduction and deterioration of a ferroelectric capacitor in a passivation film forming step in which the hydrogen concentration is particularly high. A passivation film was formed thereon.
[0003]
[Problems to be solved by the invention]
However, since the aluminum wiring is minutely steep, the coverage of the hydrogen barrier film on the aluminum wiring is poor, and it is not possible to sufficiently prevent hydrogen penetration during the formation of the passivation film. If the hydrogen barrier film is multi-layered in order to suppress the intrusion of hydrogen from the gap between the aluminum wiring and the hydrogen barrier film, the throughput is reduced by the additional manufacturing process.
[0004]
Therefore, an object of the present invention is to solve the above-mentioned problem and to propose a ferroelectric memory device having a structure for preventing reduction deterioration of a ferroelectric capacitor. Another object of the present invention is to propose a method for manufacturing a ferroelectric memory device having good hydrogen barrier characteristics without lowering the throughput.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, a ferroelectric memory device according to the present invention is configured such that a stripe-shaped upper electrode and a lower electrode are formed in a direction crossing each other, and at least in a region where the upper electrode and the lower electrode cross each other. It comprises a memory cell array in which ferroelectric capacitors having a dielectric film interposed are arranged in a matrix, and a hydrogen barrier film formed on the ferroelectric capacitor.
[0006]
By forming a hydrogen barrier film on the memory cell array, reduction deterioration of the ferroelectric capacitor can be prevented from a reducing atmosphere in a process of forming a passivation film or the like. Here, the “upper layer” of the memory cell array is not limited to a layer directly stacked on the memory cell array, but includes a layer stacked via one or more interlayer insulating layers.
[0007]
Here, it is preferable that the hydrogen barrier film is formed so as to cover the entire memory cell array. By forming the hydrogen barrier film so as to cover the entire memory cell array, the ferroelectric capacitor can be protected from a reducing atmosphere such as a step of forming a passivation film. Further, since active elements such as transistors are not formed in the memory cell array and the ferroelectric capacitors are arranged in a matrix, a hydrogen barrier film can be formed so as to cover the entire memory cell array.
[0008]
Further, in the above configuration, the semiconductor device further includes a peripheral circuit for writing or reading data to or from a ferroelectric capacitor, and a wiring layer connecting the ferroelectric capacitor and the peripheral circuit, wherein the wiring layer and the hydrogen The barrier films are preferably formed on the same layer. With this configuration, the wiring layer and the hydrogen barrier film can be formed in the same step, and the throughput in manufacturing is improved.
[0009]
Further, it is preferable that the wiring layer and the hydrogen barrier film are separated so as not to be electrically connected. By separating the wiring layer and the hydrogen barrier film, it is possible to eliminate problems such as conduction of the wiring layer with other wiring layers through the hydrogen barrier film.
[0010]
Further, it is preferable that the wiring layer and the hydrogen barrier film are metal films formed in the same step. With such a configuration, the manufacturing process can be simplified.
[0011]
Further, it is preferable that a metal oxide or a metal nitride is formed on the surface of the hydrogen barrier film. With this configuration, the hydrogen storage performance of the hydrogen barrier film can be improved.
[0012]
In the method of manufacturing a ferroelectric memory device according to the present invention, a stripe-shaped upper electrode and a lower electrode are formed in a direction crossing each other, and a ferroelectric film is interposed at least in a region where the upper electrode and the lower electrode cross each other. A method for manufacturing a ferroelectric memory device including a memory cell array in which ferroelectric capacitors are arranged in a matrix, comprising: forming the memory cell array; and forming an interlayer insulating film covering the memory cell array. Performing a step of opening a contact hole for connecting the ferroelectric capacitor and a peripheral circuit in the interlayer insulating film; and forming a desired hole on the interlayer insulating film so as to cover at least the contact hole. Forming a metal layer in the region.
[0013]
The metal film formed on the interlayer insulating film can function as a wiring layer, and the metal film formed on the memory cell array can function as a hydrogen barrier film. This can be simplified.
[0014]
In the step of forming a metal layer, the metal layer is preferably formed so as to cover at least the entire memory cell array. By forming a metal film so as to cover the entire memory cell array, the ferroelectric capacitor can be protected from a reducing atmosphere such as a step of forming a passivation film, and the metal layer formed on the interlayer insulating film can be protected. By patterning, a part of the metal layer is used as a wiring layer connecting the ferroelectric capacitor and the peripheral circuit, and a part of the remaining metal layer is used as a hydrogen barrier film covering the entire memory cell array. Preferably, the method further includes a step.
[0015]
With such a manufacturing process, the wiring layer and the hydrogen barrier film can be manufactured in the same process, so that the manufacturing process can be simplified and the throughput can be improved. Further, since active elements such as transistors are not formed in the memory cell array and the ferroelectric capacitors are arranged in a matrix, a metal film can be formed so as to cover the entire area of the memory cell array.
[0016]
Further, by including a step of oxidizing or nitriding the surface of the hydrogen barrier film, the hydrogen storage performance of the hydrogen barrier film can be improved.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0018]
FIG. 3 shows a plan view of the ferroelectric memory device 100. The ferroelectric memory device 100 includes a memory cell array 101, a bit line driver 21, and a word line driver 22. In the memory cell array 101, stripe-shaped lower electrodes (word lines) 11 arranged in a row direction and stripe-shaped upper electrodes (bit lines) 13 arranged in a column direction are formed to be orthogonal to each other. A ferroelectric film (not shown) is formed between the lower electrode 11 and the upper electrode 13, and a ferroelectric capacitor is formed at a point where the lower electrode 11 and the upper electrode 13 intersect.
[0019]
In the figure, A1 indicates an area where the above-described memory cell array 101 is formed, and A2 indicates an area where a peripheral circuit including the above-described bit line driver 21 and word line driver 22 is formed. In the area A1, ferroelectric capacitors are arranged in a matrix, and in the area A2, logic elements such as transistors constituting a Y gate, a sense amplifier, an input / output buffer, an X address decoder, a Y address decoder, an address buffer, and the like. Are formed in large numbers. Since no transistor is arranged in the region A1 unlike the conventional 1T1C type memory element, the integration degree of the ferroelectric capacitor can be increased. The area A2 where the peripheral circuit is formed is arranged near the outer periphery of the area A1 where the ferroelectric memory device group is formed.
[0020]
It should be noted that the ferroelectric memory device shown in the figure shows the configuration at the stage when the memory cell array 101, the bit line driver 21, and the word line driver 22 are formed. Through this, the ferroelectric memory device 100 is completed.
[0021]
FIG. 1A is a sectional view taken along line AA of FIG. An element isolation insulating layer 32 is formed on a silicon substrate 31 by LOCOS selective oxidation, and a MOS transistor 38 including a gate insulating film 34, a gate oxide film 35, a drain region 36, and a source region 37 is formed in the element isolated region. Is formed. The MOS transistor 38 is formed in the region A2 and forms a logic element of the word line driver 22. The surfaces of the MOS transistor 38 and the element isolation layer 32 are covered with an interlayer insulating film 33.
[0022]
In a region A1 on the interlayer insulating film 33, a ferroelectric capacitor 10 including a lower electrode 11, a ferroelectric film 12, and an upper electrode 13 is formed. The lower electrode 11 and the upper electrode 13 are obtained by forming a noble metal such as platinum (Pt) or iridium (Ir) or an oxide thereof (IrO _x ) by sputtering and patterning it in a stripe shape. The ferroelectric film 12 is not particularly limited, but PZT (Lead Zirconate Titanate), SBT (Strontium Bismuth Tantalates), BST (Barium Strontium Titanate), and the like are preferable. The film can be formed by a method such as a CVD method.
[0023]
By forming the ferroelectric capacitor 10 formed in the region A1 and the MOS transistor 68 formed in the region A2 on different layers, the manufacturing process of the ferroelectric capacitor 10 and the manufacturing process of the MOS transistor 68 are performed. Can be separated. An interlayer insulating film 41 is formed almost entirely over the regions A1 and A2 so as to cover the ferroelectric capacitor 10. The interlayer insulating film 41 is a silicon oxide film formed by plasma CVD using TEOS as a source gas. Contact holes h1 and h2 for forming a wiring layer in a later step are opened in the interlayer insulating film 41. The contact hole h1 communicates with the lower electrode 11, and the contact hole h2 communicates with the MOS transistor.
[0024]
FIG. 4 is a plan view showing the configuration of the ferroelectric memory device 100 after the completion of the wiring step. FIG. 1B corresponds to a cross-sectional view taken along line BB of FIG. In the wiring step, a metal layer (wiring material layer) is formed on almost the entire area of the interlayer insulating film 41 including the regions A1 and A2, and the metal layer is patterned into a predetermined shape, so that the wiring layer 51 and the hydrogen barrier layer are formed. A film 52 is formed. The wiring layer 51 is connected to the lower electrode 11 and the word line driver 22 (more specifically, a logic element such as the MOS transistor 38) through the contact holes h1 and h2, as shown in FIGS. 1B and 4. Is patterned like a line. In this step, the upper electrode 13 and the bit line driver 21 are also connected by the wiring layer 51 as shown in FIG.
[0025]
The hydrogen barrier film 52 is patterned over substantially the entire region A1 so as to cover at least the region where the memory cell array 101 is formed. As described above, by removing at least a part of the metal layer formed on the region A1 in the wiring step without removing it, the remaining metal layer can function as the hydrogen barrier film 52. . In general, the metal layer can function as the hydrogen barrier film 52, and the material thereof is not particularly limited. However, aluminum (Al) is preferable for the convenience of the manufacturing process. In general, a sputtering method is used for forming an aluminum film. Originally, in the above-described example, the hydrogen barrier film 52 was formed over substantially the entire region A1 so as to cover the region where the memory cell array 101 was formed. However, the present invention is not limited to this. The hydrogen barrier film 52 may be formed in a stripe shape along the line of the lower electrode 11 or 13, or the hydrogen barrier film 52 may be scattered at each point where the upper electrode 13 and the lower electrode 11 intersect. .
[0026]
In the above-described configuration, the hydrogen barrier film 52 is separately formed so as not to be electrically connected to any of the wiring layer 51, the upper electrode 13, and the lower electrode 11, and is in an electrically floating state. However, in the present invention, the hydrogen barrier film 52 and the wiring layer 51 do not necessarily have to be separated, and as shown in FIG. 2F, the metal layer 50 is formed over almost the entire area of the interlayer insulating film 41 including the regions A1 and A2. It is also possible to form a film and integrate the above-described wiring layer 51 and the hydrogen barrier film 52.
[0027]
Now, when the wiring layer 51 and the hydrogen barrier film 52 are formed on the interlayer insulating film 41, as shown in FIG. 1C, the wiring layer 52 and the hydrogen barrier film 52 are formed under an environment of an oxygen atmosphere or a nitrogen atmosphere. An alumina layer (Al ₂ O ₃ ) or an aluminum nitride layer (AlN) is applied to the surface (more specifically, the upper surface portion and the side wall portion) by performing a short-time heat treatment or exposing to an oxygen plasma or a nitrogen plasma. The oxide or nitride layers 51a and 52a made of are formed. By using the oxide layer or the nitride layer 52a as the upper layer of the hydrogen barrier film 52, good hydrogen barrier characteristics can be obtained.
[0028]
However, when the upper layer of the wiring layer 51 is simultaneously oxidized or nitrided together with the hydrogen barrier film 52, only the upper layer of the surface is oxidized or nitrided so that the entire wiring layer 51 is not oxidized or nitrided to become an insulating film. The above-mentioned heat treatment time or plasma exposure time is adjusted so as to be performed. Of course, in the present invention, the wiring layer 51 does not necessarily need to be oxidized or nitrided together with the hydrogen barrier film 52, and a mask 70 for covering the wiring layer 51 is formed as shown in FIG. The oxide layer or the nitride layer 52a may be formed by oxidizing or nitriding the surface of the hydrogen barrier film 52 so that the surface of the layer 51 is not oxidized or nitrided.
[0029]
In the case where the hydrogen barrier film 52 has a two-layer structure of Al / Al ₂ O ₃ or Al / AlN, an aluminum layer is formed as described above, and then this is oxidized or nitrided. Then, the above-mentioned two-layer structure may be realized at the stage of forming an aluminum layer. For example, there is a method in which pure Al is formed by sputtering using aluminum as a target, and oxygen gas or nitrogen gas is introduced during the formation of the Al film, so that Al ₂ O ₃ or AlN is stacked thereon. Conceivable.
[0030]
Note that, as the hydrogen barrier film 52, in addition to the above, various metal oxides or metal nitrides such as titanium oxide, titanium nitride, and iridium oxide can be used. Although not shown in FIGS. 1 and 2, a hydrogen barrier film may be formed so as to cover each ferroelectric capacitor 10 in addition to the above-described configuration. When the wiring layer 51 and the hydrogen barrier film 52 are formed on the interlayer insulating film 41 through the above steps, as shown in FIG. 2D, the passivation film 60 is formed over the entire region including the regions A1 and A2. By forming the film, the ferroelectric memory device 100 is completed. As the passivation film 60, SiN or the like is preferable.
[0031]
As described above, according to the structure of the ferroelectric memory device of the present embodiment, a peripheral circuit (bit line driver 21) including transistors and the like is provided around a memory cell array 101 in which ferroelectric capacitors 10 are arranged in a matrix. Since the word line driver 22) is formed, a metal layer can be formed on the memory cell array at the time of the wiring step, and the metal layer can be left without being removed, so that the hydrogen barrier film can be formed. It is possible to function as. That is, it is not necessary to perform the step of forming the wiring layer and the hydrogen barrier film in separate steps, and the processing can be performed collectively in the same step.
[0032]
In addition, the hydrogen barrier film 52 formed over the memory cell array 101 can be oxidized or nitrided to increase the hydrogen storage capacity, so that it can function as a favorable hydrogen barrier film. Become.
[Brief description of the drawings]
FIG. 1 is a sectional view of a manufacturing process of a ferroelectric memory device.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of the ferroelectric memory device.
FIG. 3 is a plan view of a ferroelectric memory device.
FIG. 4 is a plan view of a ferroelectric memory device.
[Explanation of symbols]
REFERENCE SIGNS LIST 100 ferroelectric memory device 101 memory cell array 21 bit line driver 22 word line driver 10 ferroelectric capacitor 11 lower electrode 12 ferroelectric film 13 upper electrode 41 interlayer insulating film 51 wiring layer 52: hydrogen barrier film 51a, 52a: oxide layer or nitride layer

Claims (10)

A stripe-shaped upper electrode and a lower electrode are formed in a direction intersecting each other, and ferroelectric capacitors each including a ferroelectric film interposed at least in a region where the upper electrode and the lower electrode intersect are arranged in a matrix. A ferroelectric memory device, comprising: a memory cell array; and a hydrogen barrier film formed on the ferroelectric capacitor. 2. The ferroelectric memory device according to claim 1, wherein the hydrogen barrier film is formed so as to cover the entire memory cell array. A peripheral circuit for writing or reading data to or from the ferroelectric capacitor; and a wiring layer connecting the ferroelectric capacitor and the peripheral circuit, wherein the wiring layer and the hydrogen barrier film are on the same layer. 3. The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device is formed by film formation. 4. The ferroelectric memory device according to claim 3, wherein said wiring layer and said hydrogen barrier film are separated so as not to be electrically connected. 5. The ferroelectric memory device according to claim 3, wherein the wiring layer and the hydrogen barrier film are metal thin films formed in the same step. The ferroelectric memory device according to claim 1, wherein a surface of the hydrogen barrier film is formed of a metal oxide or a metal nitride. A stripe-shaped upper electrode and a lower electrode are formed in a direction intersecting with each other, and ferroelectric capacitors each including a ferroelectric film interposed at least in a region where the upper electrode and the lower electrode intersect are arranged in a matrix. A method of manufacturing a ferroelectric memory device including a memory cell array,
Forming the memory cell array;
Forming an interlayer insulating film covering the memory cell array;
Opening a contact hole in the interlayer insulating film for making a connection between the ferroelectric capacitor and a peripheral circuit;
A method of manufacturing a ferroelectric memory device, comprising a step of forming a metal layer in a desired region on the interlayer insulating film so as to cover at least the contact hole. The method of manufacturing a ferroelectric memory device according to claim 7, wherein in the step of forming the metal layer, the metal layer is formed so as to cover at least the entire area of the memory cell array. By patterning the metal layer formed on the interlayer insulating film, a part of the metal layer is used as a wiring layer connecting the ferroelectric capacitor and the peripheral circuit, and a part of the remaining metal layer 9. The method of manufacturing a ferroelectric memory device according to claim 8, further comprising the step of: forming a hydrogen barrier film covering the entire memory cell array. 10. The method of manufacturing a ferroelectric memory device according to claim 9, further comprising a step of oxidizing or nitriding the surface of the hydrogen barrier film.

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