JP2004296008A - Synchronous memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous memory in which wasteful power consumption is suppressed, concerning the synchronous memory for performing write and read of data in synchronization with a clock frequency. <P>SOLUTION: In this synchronous memory, address signals A10, A11, A12 inputted to flip-flops 12_11, 12_12, 12_13 immediately before are compared with address signals A20, A21, A22 inputted this time from flip-flops 11_1, 11_2, 11_3 , by exclusive OR gates 12_21, 12_22, 12_23, and in the case of coincidence, a control part 60 inhibits reading of data by setting the potential of a node<SB>atran</SB>to a level 'H'. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a synchronous memory that writes and reads data in synchronization with a clock.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a cache memory mounted on a CPU or the like, or a memory mounted on an ASIC (Application Specific Integrated Circuit) such as a gate array, a standard cell, or an embedded array, a synchronous memory that can easily handle timing is widely used. It is used. As such a synchronous memory, for example, a synchronous memory has been proposed in which a read time delay due to crosstalk between bit lines is prevented (see Patent Document 1).
[0003]
[Patent Document 1]
JP-A-10-269779
[Problems to be solved by the invention]
A conventional synchronous memory uses the synchronous memory so that a new address is not input from the outside when in a data read mode in which data written to an address is read in synchronization with a clock. Even if the power supply is not in operation, power is wasted because charge / discharge of the bit line pair consisting of the main components, the bit line bar, and activation of the word line are performed in synchronization with the clock. There is a problem that is.
[0005]
The present invention has been made in view of the above circumstances, and has as its object to provide a synchronous memory in which useless power consumption is suppressed.
[0006]
[Means for Solving the Problems]
A synchronous memory of the present invention that achieves the above object is a synchronous memory that writes and reads data in synchronization with a clock.
An address match determination unit that determines whether or not the previously input address signal matches the currently input address signal;
A data read permission / non-permission control unit for prohibiting or permitting data reading depending on whether the immediately preceding address signal and the current address signal match in the data read mode in the data read mode; It is characterized by having.
[0007]
The synchronous memory of the present invention inhibits data reading when the immediately preceding address signal and the current address signal match in the data reading mode. Does not change, the charging / discharging of the bit line pair and the activation of the word line are not performed in synchronization with the clock, so that wasteful power consumption is prevented.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0009]
FIG. 1 is a block diagram showing a configuration of a synchronous memory according to an embodiment of the present invention.
[0010]
The synchronous memory 1 shown in FIG. 1 is a synchronous memory to which an address signal A is variably input and which writes data to an address A or reads data written to the address A in synchronization with a clock CLK. The synchronous memory 1 includes an address latch unit 10, a predecoder unit 20, a word drive unit 30, a memory cell array unit 40, a sense amplifier & write drive unit 50, and a control unit 60. Have been.
[0011]
The address latch unit 10 captures the input address signal A at the rising edge of the clock CLK and outputs it to the predecoder unit 20. As will be described in detail later, the address latch unit 10 includes an address match determination unit that determines whether the address signal A input immediately before matches the address signal A input this time. ing.
[0012]
The predecoder 20 receives and decodes the address signal A from the address latch 10 and outputs the decoded signal to the word driver 30.
[0013]
The word driver 30 activates the selected word line based on the signal decoded by the predecoder 20.
[0014]
The memory cell array section 40 is provided with each memory cell at each intersection between each word line and each bit line pair (not shown).
[0015]
The sense amplifier & write driving unit 50 detects a potential difference appearing on the bit line pair according to the storage content of the memory cell corresponding to the activated word line, and reads the storage content of the memory cell as output data DO. A sense amplifier; and a write driver for writing a storage content to a memory cell corresponding to the activated word line by placing a signal corresponding to the logic of input data DI input from the outside on a bit line pair. I have.
[0016]
The control unit 60 corresponds to an example of a data read permission / refusal control unit according to the present invention. When in a data read mode, an address match determination unit described later matches the immediately preceding address signal A with the current address signal A. Depending on whether the data is read or not, the data reading is prohibited or permitted, respectively.
[0017]
FIG. 2 is a diagram illustrating an example of a circuit of the address latch unit illustrated in FIG.
[0018]
The address latch unit 10 illustrated in FIG. 2 includes flip-flops 11_1, 11_2, and 11_3, and an address match determination unit 12. The address match determination unit 12 includes flip-flops 12_11, 12_12, 12_13, exclusive OR gates 12_21, 12_22, 12_23, NMOS transistors 12_31, 12_32, 12_33, and a PMOS transistor 12_41.
[0019]
The address latch unit 10 first receives a signal A10, a signal A (0), a first bit signal A (1), and a second bit signal A (2) constituting the address signal A. A11 and A12 (corresponding to the address signal input immediately before according to the present invention) are input, and then signals A20, A21 and A22 (corresponding to the address signal input at this time according to the present invention) are input. .
[0020]
First, signals A10, A11, and A12 are input as signals A (0), A (1), and A (2), respectively. The flip-flops 11_1, 11_2, and 11_3 take in these signals A10, A11, and A12 at the rising edge of the first clock CLK, and send the signals to the flip-flops 12_11, 12_12, 12_13 and the exclusive OR gates 12_21, 12_22, and 12_23. Output.
[0021]
Next, signals A20, A21, and A22 are input as signals A (0), A (1), and A (2). The flip-flops 11_1, 11_2, and 11_3 take in these signals A20, A21, and A22 at the rising edge of the second clock CLK, and send the signals to the flip-flops 12_11, 12_12, 12_13 and the exclusive OR gates 12_21, 12_22, and 12_23. Output. On the other hand, since the signals A10, A11, and A12 are input to the flip-flops 12_11, 12_12, and 12_13, these flip-flops capture the signals A10, A11, and A12 at the rising edge of the second clock CLK. Output to the exclusive OR gates 12_21, 12_22, and 12_23.
[0022]
As described above, the exclusive OR gates 12_21, 12_22, and 12_23 receive the address signals A10, A11, and A12 input immediately before and the address signals A20, A21, and A22 input this time. The exclusive OR gates 12_21, 12_22, and 12_23 compare the signals A10, A11, and A12 with the signals A20, A21, and A22, respectively, and output an "H" level signal when they do not match, and output an "H" level signal when they match. An "L" level signal is output. The “H” level or “L” level signal is input to the gates of the NMOS transistors 12_31, 12_32, and 12_33. The drains of the NMOS transistors 12_31, 12_32, and 12_33 are commonly connected to the drain of the PMOS transistor 12_41 and the node atran which is the input side of the control unit 60. The source of the PMOS transistor 12_41 is connected to the power supply Vdd. The clock CLK is input to the gate of the PMOS transistor 12_41.
[0023]
FIG. 3 is a timing chart showing the operation of the address latch unit shown in FIG.
[0024]
As shown in FIG. 3, at the first time, the clock CLK is at the “L” level, and in the section at the “L” level, the PMOS transistor 12_41 is in the ON state. As the address signal A, an address signal A0 composed of the signals A10, A11, and A12 input immediately before is input. Here, it is assumed that the logics of these signals A10, A11, A12 are all “0”. At the initial time, it is assumed that a signal of logic “0” is output from each of the flip-flops 11_1, 11_2, and 11_3 and each of the flip-flops 12_11, 12_12, and 12_13. Therefore, all of the exclusive OR gates 12_21, 12_22, and 12_23 output an “L” level signal indicating that they match. Therefore, the NMOS transistors 12_31, 12_32, and 12_33 are all in the off state. Therefore, the node atran is precharged on the path from the power supply Vdd to the PMOS transistor 12_41 and is at the “H” level.
[0025]
Here, the address signal A changes from A0 to A1. The address signal A1 is an address signal including the signals A20, A21, and A22 input this time. The logic of these signals A20, A21, A22 is "1", "0", "0". Next, at the rising edge of the first clock CLK, these signals A20, A21, A22 are taken into the flip-flops 11_1, 11_2, 11_3. Then, since the signal A20 of logic “1” and the signal A10 of logic “0” are input to the exclusive OR gate 12_21, an “H” level signal indicating that they do not match is output from the exclusive OR gate 12_21. Is done. Therefore, the NMOS transistor 12_31 is turned on, and the electric charge precharged to the node atran is discharged to the ground GND via the NMOS transistor 12_31. As a result, the potential of the node atlan becomes the “L” level, and in response to the “L” level, the control unit 60 outputs the “H” level enable signal ENB. The “H” level enable signal ENB is input to the word drive unit 30 (see FIG. 1), and the word line WL selected by the predecoder unit 20 is activated to be set to the “H” level. The storage content of the memory cell or word corresponding to A1 is read. The flip-flops 12_11, 12_12, and 12_13 are configured to capture input data at both the rising edge and the falling edge of the clock CLK. Therefore, at the falling edge of the first clock CLK, the logic of the signals A20, A21, and A22 is captured by the flip-flops 12_11, 12_12, and 12_13, whereby the NMOS transistor 12_31 is turned off, and the clock signal 'L In the “level” section, the PMOS transistor 12_41 is turned on, and the node atran becomes “H” level. Then, the control unit 60 outputs an “L” level enable signal ENB. The “L” level enable signal ENB is input to the word drive unit 30, and the word line WL selected by the predecoder unit 20 is deactivated and set to the “L” level.
[0026]
Next, a second clock CLK is input. Here, the address A1 remains. Therefore, the signals A20, A21, and A22 which are taken into the flip-flops 11_1, 11_2, and 11_3 at one rising edge of the second clock CLK and input to one ends of the exclusive OR gates 12_21, 12_22, and 12_23 (the present input according to the present invention). And the signals A20 and A21 which are taken into the flip-flops 12_11, 12_12 and 12_13 at the rising edge of the second clock CLK and input to the other ends of the exclusive OR gates 12_21, 12_22 and 12_23. , A22 (corresponding to the address signal input immediately before in the present invention) are coincident, and thus the exclusive OR gates 12_21, 12_22, and 12_23 output an "L" level signal indicating that they coincide. For this reason, the potential of the node atran is maintained at the “H” level, and the “H” level is continuously input to the control unit 60, and the “L” level enable signal ENB is continuously output from the control unit 60. The “L” level enable signal ENB is input to the word driver 30, and the word line WL selected by the predecoder 20 is kept in an inactive state, that is, at the “L” level. . On the other hand, in the conventional synchronous memory, if the address signal A1 remains unchanged, the enable signal ENB at the “H” level is output as shown by the dotted line in FIG. 3, so that the word line WL is activated. As a result, power is wasted in charging and discharging.
[0027]
As described above, in the synchronous memory 1 of the present embodiment, when in the data read mode, if the immediately preceding address signal A matches the current address signal A, data reading is prohibited. Therefore, in the data read operation, when the address signal A does not change, the activation of the word line is not performed in synchronization with the clock CLK, so that wasteful power consumption is prevented. Further, in the synchronous memory of the present embodiment, the enable signal generated by the control unit 60 is input to the sense amplifier & write driving unit 50, and the bit line is charged and discharged to deactivate the bit line. Since no power is consumed, useless consumption of power is prevented.
[0028]
【The invention's effect】
As described above, according to the synchronous memory of the present invention, wasteful power consumption can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a synchronous memory according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a circuit of an address latch unit illustrated in FIG. 1;
FIG. 3 is a timing chart showing an operation of the address latch unit shown in FIG. 2;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Synchronous memory 10 Address latch part 11_1, 11_2, 11_3, 12_11, 12_12, 12_13 Flip-flop 12 Address match judgment part 12_21, 12_22, 12_23 Exclusive OR gate 12_31, 12_32, 12_33 NMOS transistor 12_41 PMOS transistor 20 Predecoder part 30 word Drive unit 40 Memory cell array unit 50 Sense amplifier & write drive unit 60 Control unit

Claims (1)

In a synchronous memory that writes and reads data in synchronization with a clock,
An address match determination unit that determines whether or not the previously input address signal matches the currently input address signal;
A data read permission / non-permission control unit for prohibiting or permitting data read depending on whether the previous address signal matches the current address signal by the address match determination unit when in the data read mode; Synchronous memory comprising:

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