JPH08314886A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To reduce the power consumption and the price and to speed up the equipment setting by utilizing the initialization pulse outputted from an initialization pulse generation circuit as a precharge control pulse at the rise time of power source voltage. CONSTITUTION: An equipment setting data generation circuit is provided with a precharge type sense amplifier 49 which requires less power consumption and has a smaller number of elements than a current sense type sense amplifier. This precharge type sense amplifier 49 reads the function setting data that a function setting data storage circuit 44 stores. Immediately after a power source was turned on, the power-on reset power outputted from a power-on reset pulse generation circuit 59 is supplied to a precharge circuit 50 via a delay circuit 76 as a precharge control pulse. Therefore, the power consumption is reduced, the chip size is reduced, function setting data is outputted before an external clock is supplied and the change of an operating frequency can be performed by function setting data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit whose function can be changed by rewriting data in a memory cell.

[0002]

2. Description of the Related Art For example, a one-chip microcomputer for development or versatility requires a resistor for receiving the output of an open-drain type output circuit, changing the operating frequency, changing the idling time at the start of operation. Is required to be configured to be able to select whether or not to connect the chip inside the chip.

Therefore, it is assumed that the one-chip microcomputer for development or versatility can change certain functions such as operating speed. Therefore, a function setting data (option data) generating circuit is built in, When the power is turned on, the function is set based on the function setting data output from the function setting data generating circuit.

FIG. 6 is a circuit diagram showing an example of a function setting data generating circuit incorporated in a conventional one-chip microcomputer for development or for which versatility is required.

In FIG. 6, reference numeral 1 denotes an EPRO which is a rewritable nonvolatile memory cell for storing function setting data.
M (Erasable and Programmable Lead Only Menor)
y) Cell and WS are word select signals for reading the function setting data stored in the EPROM cell 1.

Reference numeral 2 is a current sense type sense amplifier for reading the function setting data stored in the EPROM cell 1, VDD is a power supply voltage, 3 to 8 are nMOS transistors, and 9 to 13 are pMOS transistors.

SA and / SA are sense amplifier activation signals, and the sense amplifier activation signal SA is at a high level (hereinafter referred to as H level) when the power is turned on, and when the function setting data is output, It is set to a low level (hereinafter referred to as L level), the sense amplifier activation signal / SA is set to L level when the power is turned on, and is set to H level when the function setting data is output.

Further, 14 is a current sense type sense amplifier 2.
It is a latch circuit for latching the function setting data output from.

In this function setting data generating circuit,
When the power is turned on, the sense amplifier activation signal SA = H level,
Sense amplifier activation signal / SA = L level, nM
The OS transistors 3 and 4 are turned on, the pMOS transistors 9 and 10 are turned on, the current sense type sense amplifier 2 is activated, the word selector signal WS is set to H level, and the EPROM cell 1 is read. It is said that

In this case, when writing is performed to the EPROM cell 1, the EPROM cell 1
Is not turned on, no current flows between the drain and source of the EPROM cell 1, and the level of the node 15 becomes H level.

As a result, in this case, the level of the node 16 = H level, the pMOS transistors 11 and 12 = OFF state, the nMOS transistors 6 and 7 = ON state, the level of the node 17 = L level, the pMOS transistor 13
= ON state, nMOS transistor 8 = OFF state, the current sense type sense amplifier 2 outputs H level as the function setting data, and this is latched by the latch circuit 14.

On the other hand, when the EPROM cell 1 is not written, the EPROM cell 1 is turned on, so that a current flows between the drain and source of the EPROM cell 1 and the node 15 Level = L level.

As a result, in this case, the level of node 16 = L level, pMOS transistors 11 and 12 = on state, nMOS transistors 6 and 7 = off state, level of node 17 = H level, pMOS transistor 13
= OFF state, nMOS transistor 8 = ON state, the current sense type sense amplifier 2 outputs L level as the function setting data, and this is latched by the latch circuit 14.

Here, the function setting data is the latch circuit 14
Is latched to, the sense amplifier activation signal SA = L level, the sense amplifier activation signal / SA = H level, and the nMOS transistors 3 and 4 = off state, pMOS
Transistors 9 and 10 are turned off, current sense type sense amplifier 2 is deactivated, and word selector signal WS is set to L level.

In this function setting data generating circuit,
For example, when writing is not performed in the EPROM cell 1, when the EPROM cell 1 is set in the reading state,
During the read state, the nMOS transistor 3 is always
And, since a through current flows through the EPROM cell 1,
There is a problem that power consumption increases.

Further, in this function setting data generating circuit, the current sense type sense amplifier 2 is provided, but the current sense type sense amplifier 2 requires a large number of elements, and therefore the chip size becomes large. However, there was also a problem that it caused an increase in price.

Therefore, conventionally, a function setting data generating circuit as shown in FIG. 7 has been proposed and is incorporated in a conventional one-chip microcomputer for development or for which versatility is required.

In FIG. 7, 19 is a function setting data storage circuit for storing function setting data, 20 and 21 are EPROM cells, 22 is a word select signal WS supplied to the control gates of the EPROM cells 20 and 21. The word line 23 is a bit line to be precharged to the precharge voltage.

Further, 24 is a function setting data storage circuit 19
Is a precharge type sense amplifier for reading the function setting data stored in the memory, 25 is a precharge circuit for precharging the bit line 23, and 26 is the bit line 23.
Is a sense output circuit that senses the voltage of and outputs the function setting data.

In the precharge circuit 25, 2
7 to 29 are nMOS transistors, and in the sense output circuit 26, 30 is a pMOS transistor, 31,
32 is an nMOS transistor.

Reference numeral 33 is a latch circuit for latching the function setting data output from the precharge type sense amplifier 24.

Reference numeral 34 denotes an internal system for external system, which shapes the external clock CLK _A and outputs an internal system clock CLK _B having a frequency designated by a clock control signal generated from a predetermined internal circuit. It is a clock generation circuit.

Reference numeral 35 denotes an internal system clock CLK output from the internal system clock generation circuit 34.
_It is a clock frequency dividing circuit that divides _B into a frequency designated by a clock control signal to generate a precharge control pulse PC to be supplied to the precharge circuit 25 and a latch control pulse RT to be supplied to the latch circuit 33.

In this example, the clock control signal is
Since the function setting data must be generated before being output, the contents are fixed by the wiring option in the manufacturing process.

In this function setting data generating circuit,
After the power is turned on, when the power supply voltage VDD stabilizes, the external clock CLK _A is supplied from the outside, the internal system clock CLK _B is output from the internal system clock generation circuit 34, and the H level pre-clock is output from the clock divider circuit 35. The charge control pulse PC is output.

As a result, in the precharge circuit 25, the nMOS transistors 27 and 29 are turned on, and the precharge to the bit line 23 is started via the nMOS transistor 27.

After that, the precharge control pulse PC becomes L
At the level, in the precharge circuit 25, n
The MOS transistors 27 and 29 are turned off, and the precharge for the bit line 23 is completed.

Then, the word select signal WS is set to H level, and the EPROM cells 20 and 21 of the function setting data storage circuit 19 are set to the read state.

In this case, the EPROM cell 20,
When writing is performed in 21, the EPROM cells 20 and 21 are not turned on, so the charge accumulated in the bit line 23 is not extracted by the precharge by the precharge circuit 25, and the bit line 23 is Maintain precharge voltage.

As a result, in this case, in the sense output circuit 26, the pMOS transistor 30 is turned off and the nMOS transistors 31 and 32 are turned on, and the sense output circuit 26 outputs the L level as the function setting data. This is latched in the latch circuit 33.

On the other hand, the EPROM cells 20, 21
EPROM cell 2 if not written to
Since 0 and 21 are turned on, the precharge circuit 25
The electric charge accumulated in the bit line 23 is extracted to the ground side through the EPROM cells 20 and 21 by the precharge by, and the voltage of the bit line 23 is reduced to the ground voltage.

As a result, in this case, in the sense output circuit 26, the pMOS transistor 30 is turned on and the nMOS transistors 31 and 32 are turned off, and the sense output circuit 26 outputs the H level as the function setting data. This is latched in the latch circuit 33.

Here, the precharge type sense amplifier 24
Precharges the bit line 23 to generate EPRO
Since the data stored in the M cells 20 and 21 are read out, the current consumption is smaller than that of the current sense type sense amplifier 2 shown in FIG. 6, and therefore, when the function setting data generating circuit is incorporated, the consumption current is reduced. It is possible to reduce power consumption.

Since the precharge type sense amplifier 24 requires a smaller number of elements than the current sense type sense amplifier 2 shown in FIG. 6, when the function setting data generating circuit is built in, the chip size is reduced. And the price can be reduced.

[0035]

However, in this function setting data generating circuit, the internal system clock CLK _B generated by the external clock CLK _A is generated.
However, the external clock CLK _A is not supplied until the power supply voltage VDD stabilizes after the power is turned on.

Therefore, when the function setting data generating circuit is incorporated, the function setting data is generated immediately after the power is turned on, and the function setting based on the function setting data is performed before the external clock CLK _A is supplied. There was a problem that I could not do it.

Further, in this function setting data generating circuit, the content of the clock control signal for instructing the frequency of the internal system clock CLK _B is fixed by the wiring option in the manufacturing process, so that the internal system clock CLK _B is fixed. There was also a problem that the frequency of could not be changed.

In view of the above points, the present invention reduces the power consumption by reducing the current consumption in the function setting data generation circuit, reduces the price by reducing the chip size, and reduces the function setting after the power is turned on. An object of the present invention is to provide a semiconductor integrated circuit capable of achieving both speeding up and enabling change of operating frequency by function setting data.

[0039]

FIG. 1 is a diagram for explaining the principle of the present invention. A semiconductor integrated circuit according to the present invention includes an initialization pulse generation circuit 37 and a precharge control pulse supply path 38.
A function setting data generating circuit 42 including a sense amplifier 39, a predetermined wiring 40, and a memory cell 41.

Here, the initialization pulse generation circuit 37 generates an initialization pulse for initialization when the power supply voltage rises, and this initialization pulse is supplied to an internal circuit that requires initialization. It

Further, the precharge control pulse supply path 38
Senses the initialization pulse output from the initialization pulse generation circuit 37 as a precharge control pulse.
Is to be supplied to

The sense amplifier 39 is controlled by an initialization pulse supplied as a precharge control pulse to precharge a predetermined wiring 40, and at the same time, detects the potential of the predetermined wiring 40. The function setting data for setting the function is output.

When the memory cell 41 is in the read state and is being written, the predetermined wiring 4 is formed by precharging by the sense amplifier 39.
The charge accumulated in 0 is not extracted, and when writing is not performed, the charge accumulated in the predetermined wiring 40 is extracted by the precharge by the sense amplifier 39.

[0044]

In the present invention, the function setting data generating circuit 4
Reference numeral 2 denotes a so-called precharge-type sense amplifier which is controlled by a precharge control pulse to precharge a predetermined wiring 40 and outputs function setting data by detecting the potential of the predetermined wiring 40. Since it is provided, the current consumption can be reduced and the chip size can be reduced.

Further, the function setting data generating circuit 42 supplies the initialization pulse output from the initialization pulse generating circuit 37 to the sense amplifier 39 as a precharge control pulse when the power supply voltage rises.
The function setting data can be output before the external clock is supplied from the outside, and the operating frequency can be changed by the function setting data.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
The embodiment and the second embodiment will be described by taking the case where the present invention is applied to a one-chip microcomputer as an example.

First Embodiment FIG. 2 to FIG. 4 FIG. 2 is a circuit diagram showing an essential part of the first embodiment of the present invention.
3 shows a function setting data generating circuit incorporated in the first embodiment.

In FIG. 2, 44 is a function setting data storage circuit for storing function setting data, 45 and 46 are EPROM cells, and 47 is a word select signal WS supplied to the control gates of the EPROM cells 45 and 46. Is a word line, and 48 is a bit line to be precharged to a precharge voltage.

Further, 49 is a function setting data storage circuit 44.
Is a precharge type sense amplifier for reading out the function setting data stored by, a precharge circuit 50 for precharging the bit line 48, and 51 a bit line 48.
Is a sense output circuit that senses the voltage of and outputs the function setting data.

In the precharge circuit 50, 5
2 to 54 are nMOS transistors, and in the sense output circuit 51, 55 is a pMOS transistor, 56,
57 is an nMOS transistor.

Reference numeral 58 is a latch circuit for latching the function setting data output from the precharge type sense amplifier 49.

Reference numeral 59 is an initialization pulse generation circuit for generating an initialization pulse for setting the initial state of the internal circuit, that is, a power-on reset pulse generation circuit for generating a power-on reset pulse PO.

This power-on reset pulse generation circuit 5
In FIG. 9, 60 is a pulse generation circuit unit, and 61, 6
2 is a pMOS transistor, and 63 and 64 are nMOS transistors.

Reference numeral 65 denotes a delay circuit section for delaying the pulse output from the pulse generation circuit section 60, and 66 to 6
Reference numeral 8 is a pMOS transistor, 69 to 71 are nMOS transistors, and 72 to 74 are capacitors.

Reference numeral 75 denotes a power-on reset pulse PO which waveform-shapes the pulse output from the delay circuit section 65.
Is a Schmitt trigger inverter that outputs

Reference numeral 76 is a delay circuit for delaying the power-on reset pulse PO so that the precharge voltage of the bit line 48 becomes a sufficient value, and 77 and 78 are inverters.

FIGS. 3 and 4 are voltage waveform diagrams showing the operation of the function setting data generating circuit. In particular, FIG.
Shows the case where the EPROM cells 45 and 46 are written, and FIG. 4 shows the case where the EPROM cells 45 and 46 are not written.

3 and 4, the solid line 80 indicates the waveform of the power supply voltage VDD, and the short broken line 81 indicates the node 8 of the pulse generation circuit section 60 of the power-on reset pulse generation circuit 59.
2, a one-dot chain line 83 is a voltage waveform at the output end of the delay circuit 76, a two-dot chain line 84 is a voltage waveform of the bit line 48, and a long broken line 85 is a node 86 of the sense output circuit 51 of the precharge type sense amplifier 49. The voltage waveform is shown.

That is, in this function setting data generating circuit, when the power is turned on, the power supply voltage VDD starts to rise from the ground voltage toward the operating voltage, and as a result, the power-on reset pulse generating circuit 59. The voltage of the node 82 of the pulse generation circuit section 60 is the same as that of the pMOS transistor 6
It rises due to the coupling effect of the capacitor composed of 1 and generates a pulse of a predetermined voltage.

This pulse is delayed by the delay circuit section 65, further waveform shaped by the Schmitt trigger inverter 75, output from the power-on reset pulse generation circuit 59 as the power-on reset pulse PO, and the initial state is set. Are supplied to the internal circuits requiring the signal, are delayed by the delay circuit 76, and are supplied to the nMOS transistors 52 and 54 of the precharge circuit 50 of the precharge type sense amplifier 49.

As a result, in the precharge circuit 50, the nMOS transistors 52 and 54 are turned on, and the precharge of the bit line 48 of the function setting data storage circuit 44 is started via the nMOS transistor 52.

Thereafter, the power-on reset pulse PO becomes L level, and in the precharge circuit 50, n
The MOS transistors 52 and 54 are turned off, and the precharge for the bit line 48 is completed.

Then, the word select signal WS is set to the H level, and the EPROM cells 45 and 46 of the function setting data storage circuit 44 are set to the read state.

In this case, the EPROM cell 45,
Since the EPROM cells 45 and 46 are not turned on when writing is performed in 46, the charge accumulated in the bit line 48 is not extracted by the precharge by the precharge circuit 50, and the bit line 48 is Maintain precharge voltage.

As a result, in this case, in the sense output circuit 51, the pMOS transistor 55 is turned off and the nMOS transistors 56 and 57 are turned on, and the sense output circuit 51 outputs the L level as the function setting data. This is latched in the latch circuit 58.

On the other hand, EPROM cells 45 and 46
EPROM cell 4 if not written to
Since 5 and 46 are turned on, the precharge circuit 50
The electric charge accumulated in the bit line 48 is extracted to the ground side through the EPROM cells 45 and 46 by the precharging by, and the voltage of the bit line 48 is lowered to the ground voltage.

As a result, in this case, in the sense output circuit 51, the pMOS transistor 55 is turned on and the nMOS transistors 56 and 57 are turned off, and the sense output circuit 51 outputs the H level as the function setting data. This is latched in the latch circuit 58.

Here, according to the first embodiment, the function setting data generating circuit consumes less current and requires fewer elements than the current sense type sense amplifier 2 shown in FIG. 6, and is a precharge type. Since the sense amplifier 49 is provided, it is possible to reduce the current consumption in the function setting data generation circuit and the chip size.

Further, in the first embodiment, the power-on reset pulse PO output from the power-on reset pulse generation circuit 59 immediately after the power is turned on is used as the precharge control pulse, and the precharge circuit is passed through the delay circuit 76. Since it is supplied to 50, the function setting data can be output before the external clock is supplied from the outside, and the operating frequency can be changed by the function setting data.

That is, according to the first embodiment, the power consumption is reduced by reducing the current consumption in the function setting data generating circuit, the price is reduced by reducing the chip size, and the function after the power is turned on is reduced. It is possible to increase the setting speed and change the operating frequency based on the function setting data.

Second Embodiment FIG. 5 FIG. 5 is a circuit diagram showing an essential part of the second embodiment of the present invention.
9 shows a function setting data generating circuit incorporated in the second embodiment.

In FIG. 5, reference numeral 88 denotes an internal circuit which shapes the external clock CLK _A supplied from the outside and outputs an internal system clock CLK _B having a frequency designated by a clock control signal generated from a predetermined internal circuit. It is a system clock generation circuit.

89 is an internal system clock CLK output from the internal system clock generation circuit 88.
_The precharge circuit 50 of the precharge type sense amplifier 49 is divided by dividing the frequency of _B into the frequency designated by the clock control signal.
Is a clock frequency dividing circuit for generating a precharge control pulse PC to be supplied to and a latch control pulse RT to be supplied to the latch circuit 58.

In this function setting data generating circuit,
Due to its configuration, the contents of the clock control signal can be changed by the function setting data.

After the power is turned on, 90 is first passed through the power-on reset pulse PO output from the power-on reset pulse generation circuit 59, and then the precharge control pulse PC output from the clock frequency dividing circuit 89.
Is a used pulse switching circuit configured to pass through.

That is, in the second embodiment, the clock frequency dividing circuit 89 and the use pulse switching circuit 90 are added to the first embodiment, and after the power is turned on, first, the power-on reset pulse generating circuit 59 outputs. Power-on reset pulse P
O is supplied to the precharge circuit 50 as a precharge control pulse via the delay circuit 76, and then the precharge control pulse PC output from the clock frequency dividing circuit 89.
Is supplied to the precharge circuit 50 via the delay circuit 76, and the rest is configured similarly to the first embodiment.

In the second embodiment, when the power is turned on, the function setting data is output from the precharge type sense amplifier 49 and latched in the latch circuit 58 as in the case of the first embodiment. It

In this case, even if the function setting data other than the function setting data for setting the contents of the clock control signal is not normally output because the precharge voltage of the bit line 48 is low, the clock is not output thereafter. Since the precharge control pulse PC output from the frequency dividing circuit 89 is supplied to the precharge circuit 50 via the use pulse switching circuit 90 and the delay circuit 76, the power-on reset pulse PO can be output normally. Function setting data that could not be output can be output normally.

According to the second embodiment, as in the case of the first embodiment, the function setting data generating circuit consumes less current than the current sense type sense amplifier 2 shown in FIG. Since the precharge type sense amplifier 49 that requires less power consumption is provided, it is possible to reduce the current consumption and the chip size in the function setting data generation circuit.

Further, according to the second embodiment, as in the case of the first embodiment, the power-on reset pulse PO output from the power-on reset pulse generation circuit 59 immediately after the power is turned on is used as the precharge control pulse. Since it is supplied to the precharge circuit 50 via the delay circuit 76, the function setting data can be output before the external clock CLK _A is supplied from the outside, and the operating frequency can be changed by the function setting data. It can be performed.

That is, according to the second embodiment, as in the case of the first embodiment, the power consumption is reduced by reducing the current consumption in the function setting data generating circuit, and the price is reduced by reducing the chip size. Can be reduced, the function setting can be speeded up after the power is turned on, and the operating frequency can be changed by the function setting data.

Further, in particular, according to the second embodiment, the power-on reset pulse PO and the precharge control pulse PC are sequentially supplied as the necessary precharge control pulse to the precharge circuit 50. The function setting data can be output more reliably than in the case of the first embodiment, and the operation can be stabilized.

[0083]

As described above, according to the present invention, the function setting data generating circuit is provided with the precharge type sense amplifier as the sense amplifier, and the initialization pulse output circuit outputs the initialization pulse generation circuit at the rising of the power supply voltage. Since the pulse is used as a precharge control pulse, the power consumption is reduced by reducing the current consumption in the function setting data generation circuit, the price is reduced by reducing the chip size, and the function setting after power is turned on. Speeding up
It is possible to change the operating frequency based on the function setting data.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 3 is a voltage waveform diagram showing an operation of a function setting data generating circuit incorporated in the first embodiment of the present invention.

FIG. 4 is a voltage waveform diagram showing an operation of a function setting data generating circuit incorporated in the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a function setting data generation circuit incorporated in a conventional one-chip microcomputer for development or for which versatility is required.

FIG. 7 is a circuit diagram showing another example of a function setting data generating circuit incorporated in a conventional one-chip microcomputer for development or for which versatility is required.

[Explanation of symbols]

PO Power-on reset pulse WS Word select signal CLK _A External clock CLK _B Internal system clock PC Precharge control pulse RT Latch control pulse

Claims (3)

[Claims] 1. An initialization pulse generating circuit for generating an initialization pulse for initialization at the time of rising of a power supply voltage, a precharge control pulse to precharge a predetermined wiring, and a potential of the predetermined wiring. Sense amplifier that outputs the function setting data for setting the selectable function by detecting, and the precharge by the sense amplifier when writing is performed in the read state. The memory cell configured to draw out the charge stored in the predetermined wiring by the precharge by the sense amplifier when the writing is not performed without extracting the charge stored in the predetermined wiring. And the initialization pulse output from the initialization pulse generation circuit as the precharge control pulse. The semiconductor integrated circuit, characterized in that a built-in function setting data generating circuit comprising a precharge control pulse supply path for supplying to the amplifier. 2. The precharge control pulse supply path includes:
The delay circuit for delaying the initialization pulse output from the initialization pulse generation circuit so that the precharge voltage of the predetermined wiring becomes a sufficient value is interposed. Semiconductor integrated circuit. 3. A second pulse for generating a second pulse based on an external clock supplied from the outside, wherein the initialization pulse is a first pulse, the initialization pulse generation circuit is a first pulse generation circuit. A pulse generating circuit, wherein the first pulse output from the first pulse generating circuit is used as the precharge control pulse, and then the second pulse output from the second pulse generating circuit is used. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is adapted to be used as the precharge control pulse.