JP2004289369A - Frame synchronization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frame synchronization circuit whose equalizing capability is optimized by operating a decision feedback type transversal equalizer at an optimum timing. <P>SOLUTION: The frame synchronization circuit is provided with: a data correlation unit 1 for obtaining a correlation between received and demodulated input data and a reference synchronization pattern within a range of ±N bits with respect to a present frame synchronization timing; a comparator 2 for comparing a correlation output signal from the data correlation unit 1 with a criterion threshold value; and also an optimum value selection circuit 4 for controlling a timing of equalization processing in the decision feedback type transversal equalizer by selecting the timing for a succeeding frame synchronization timing when a maximum value of integrating or applying moving average to values of output signals within the range of ±N bits with respect to the present frame synchronization timing over a plurality of frame periods is a single and by selecting the timing corresponding to the maximum values temporally earlier coming for the succeeding frame synchronization timing when the maximum values are plural. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frame synchronization circuit in a receiving apparatus having a decision feedback transversal equalizer for performing waveform equalization.
[0002]
[Prior art]
In the frame synchronous transmission system, a frame synchronous bit or a frame in which a frame synchronous pattern of a plurality of bits is added to the front end of data of a predetermined length is transmitted for each frame period. Alternatively, data reception processing is performed by detecting a frame synchronization pattern and establishing frame synchronization.
[0003]
In addition, since a mobile station in a mobile communication system performs communication even while moving, the mobile station is greatly affected by the Doppler effect and multipath fading, and receives signals at different timings such as a main wave, a delayed wave, and a preceding wave. It is difficult to distinguish which is the main wave from the radio wave. Therefore, it is a common practice to consider the received wave having the highest received power as the main wave and take frame synchronization. A configuration is also known in which rake combining is performed in which each of the waves received by the multipath is demodulated, and delay correction is performed to combine the waves. In this case, a plurality of demodulators are used, which increases the hardware scale and power consumption. Is an issue.
[0004]
FIG. 6 shows a main part of a conventional frame synchronization circuit. Reference numeral 51 denotes a data correlator, 52 denotes a comparator, 53 denotes a frame counter, and the data correlator 51 is a demodulator (not shown). The correlation output signal is compared with a judgment threshold in a comparator 52, and a correlation output signal exceeding the judgment threshold is used as a reception frame timing output signal. When the count is continuously counted by the frame counter 53 and becomes a predetermined number or more, a frame synchronization signal is output to establish frame synchronization.
[0005]
The data correlator 51 has, for example, a configuration including a shift register 61 having a configuration corresponding to the number of bits of the frame synchronization pattern and an exclusive OR circuit 62 as shown in FIG. A case of a frame synchronization pattern having a bit configuration is shown. For example, in the case of a frame synchronization pattern having an 8-bit configuration, the shift register 61 shifts input data by 8 bits and outputs the data in parallel, and outputs eight exclusive OR circuits. 62.
[0006]
Then, when the bit of the input data matches the bit of the reference synchronization pattern, the output signal of the exclusive OR circuit 62 corresponding to that bit becomes "0", so that the output signal of "0" is counted. If all bits match the reference synchronization pattern, the count value becomes maximum. Then, the count value is input to the comparator 52 in FIG. 5 and is compared with the determination threshold. For example, in the case of the data correlator shown in FIG. 7, if the maximum count value is 4, and if the determination threshold value is 3, the timing at which the maximum count value becomes 4 is defined as the reception frame timing. The signal is input to the frame counter 53.
[0007]
When the same bit pattern as the synchronization pattern is included in addition to the synchronization pattern of the input data, a reception frame timing output signal may be obtained in addition to the normal reception frame timing output signal. For this purpose, the received frame timing output signal is counted by the above-described frame counter 53, and when the received frame timing output signal is obtained continuously for a predetermined number or more, that is, continuously for the number of forward protection stages or more, the frame is output. It determines that synchronization has been established and outputs a frame synchronization signal. When the received frame timing output signal is not continuously obtained for a predetermined number or more, that is, when the frame synchronization pattern cannot be continuously detected for the number of back protection stages or more, the frame synchronization is lost.
[0008]
Further, as a conventional frame synchronization circuit, when the phases of the system clock and the reception clock are different, by performing control to advance or delay the timing of the frame synchronization signal in accordance with the system clock, the frame synchronization is prevented from being lost. A configuration for controlling has been proposed (for example, see Patent Document 1).
[0009]
For example, as shown in FIG. 7, the input data and the frame synchronization bit from the frame synchronization bit generation circuit are compared in a bit correspondence manner, and for each bit, the continuity of coincidence and non-coincidence is determined. A configuration for determining whether to establish or lose frame synchronization has also been proposed (for example, see Patent Document 2).
[0010]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-270783 [Patent Document 2]
JP 2001-339360 A
[Problems to be solved by the invention]
A receiving apparatus in a frame synchronous transmission system generally has a configuration for performing data equalization by performing waveform equalization in order to eliminate intersymbol interference. As a means for performing the waveform equalization, a decision feedback is used. Type transversal equalizers are used relatively frequently. The decision feedback transversal equalizer performs waveform equalization so as to suppress inter-symbol interference by feeding back the result of discriminating and determining the waveform-equalized data waveform.
[0012]
Further, as described above, the preceding wave, the main wave, and the delayed wave having different timings are received due to fading, multipath, and the like, and the timing at which the correlation value by the data correlator shown in FIG. As the synchronization timing, the timing of the decision feedback transversal equalizer is controlled. However, the above-mentioned correlation value for the main wave is not always the maximum, and a plurality of timings at which the correlation value becomes the maximum may occur. In such a case, the timing at which the correlation value becomes maximum first in time is generally used as the frame synchronization timing.
[0013]
However, when the above-described correlation values corresponding to the leading wave, the main wave, and the delayed wave are large, respectively, the correlation value corresponding to the leading wave is temporally larger than the correlation value corresponding to the main wave. The timing is set as the frame synchronization timing, and waveform equalization in the decision feedback transversal equalizer is performed according to this timing. Therefore, waveform equalization processing is performed on the preceding wave, and processing that is regarded as an interference wave is performed on the main wave. However, since the received wave of the preceding wave or the delayed wave generally has a larger fluctuation in the received power than the main wave, the timing of the received frame timing output signal obtained by the conventional comparator 52 shown in FIG. There is a problem that does not occur.
[0014]
Further, as described above, the decision feedback type transversal equalizer controls the tap coefficient by feedback control so as to mainly suppress interference by a waveform preceding the waveform at the determination timing. In addition, as described above, when performing the waveform equalization processing at the timing of the preceding wave, there is a problem that the equalizer capability cannot be sufficiently used. Conventionally, no frame synchronization circuit has been proposed in consideration of such a decision feedback type transversal equalizer and frame synchronization timing.
[0015]
SUMMARY OF THE INVENTION It is an object of the present invention to maximize the waveform equalization capability of a decision feedback transversal equalizer using the result of frame synchronization detection.
[0016]
[Means for Solving the Problems]
A frame synchronization circuit according to the present invention will be described with reference to FIG. 1. In a frame synchronization circuit in a receiving apparatus having a decision feedback type transversal equalizer, ± N bits with respect to the current frame synchronization timing , A comparator 2 for comparing a correlation output signal of the data correlator 1 with a determination threshold, and a current correlator of the comparator 2. If the maximum value of the integrated value obtained by integrating the output signal within the range of ± N bits over a plurality of frame periods with respect to the frame synchronization timing of a single frame is single, the timing of this maximum value is taken as the next frame synchronization timing. In this case, the timing corresponding to the earlier maximum value is set as the next frame synchronization And an optimum value selection circuit 4 for controlling the input timing of the received data to the decision feedback type transversal equalizer based on the signal of the switching signal.
[0017]
A frame synchronization circuit in a receiving apparatus provided with a decision feedback type transversal equalizer, wherein a correlation between received data and a reference synchronization pattern in a range of ± N bits with respect to a current frame synchronization timing is obtained. A data correlator, a comparator for comparing a correlation output signal of the data correlator with a determination threshold, and an output signal having a different timing within a range of ± N bits with respect to the current frame synchronization timing of the comparator. A plurality of moving average calculators each for calculating a moving average over a plurality of frame periods, and when the maximum value of the moving average by the plurality of moving average calculators is single, the timing corresponding to the maximum is The frame synchronization timing shall be the frame synchronization timing. An optimum value selecting circuit for controlling the input timing of input data to the decision feedback transversal equalizer is provided as the timing.
[0018]
A frame synchronization circuit in a receiving apparatus provided with a decision feedback type transversal equalizer, wherein a correlation between received data and a reference synchronization pattern in a range of ± N bits with respect to a current frame synchronization timing is obtained. A data correlator, a plurality of integrators for respectively integrating a correlation output signal of the data correlator at different timings within a range of ± N bits with respect to the current frame synchronization timing, and an integration by the plurality of integrators When the maximum value is a single value, the timing corresponding to this maximum value is taken as the next frame synchronization timing, and in the case of multiple values, the timing corresponding to the earlier maximum value is taken as the next frame synchronization timing. , Input timing of input data to decision feedback type transversal equalizer And an optimum value selection circuit for controlling the
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Figure 1 is an explanatory view of a first embodiment of the present invention, 1 is a data correlator, 2 comparators, 3 frame counter, the 4 optimum value selection circuit, 5 ₁ to 5 ₅ counter, 6 Denotes a mask circuit, and the data correlator 1 has, for example, a configuration including a shift register and an exclusive-OR circuit as shown in FIG. 6, and performs a correlation between input data (demodulated received data) and a reference synchronization pattern. Find the correlation. Then, in the comparator 2 compares the correlation value with the determination threshold, the correlation value exceeds the determination threshold value and the reception frame timing output signal is input to the mask circuit 6 a plurality of counters 5 ₁ to 5 _5.
[0020]
The mask circuit 6 inputs the reception frame timing output signal from the comparator 2 to the frame counter 3 according to the control signal from the optimum value selection circuit 4 input to the control terminal ct, and outputs the signal to the comparator 2 other than the timing based on the control signal. This masks the received frame timing output signal from the. The number of counters 5 ₁ to 5 ₅ to enter the received frame timing output signals, the range of ± N bits for the current frame synchronization timing, shows the case of the N = 2, N is an arbitrary integer It can be.
[0021]
The decision feedback type transversal equalizer (not shown) has excellent equalization capability for interference that is delayed with respect to the main wave due to multipath or the like. In the case where it is located before, it has the same characteristics as a normal transversal equalizer. Therefore, the frame synchronization circuit of the present invention has a configuration capable of selecting a reception frame timing that maximizes the equalization capability of the decision feedback type transversal equalizer.
[0022]
That is, the plurality of counters 5 ₁ to 5 ₅ described above, resetting the initial state and a reset signal every predetermined time period, from the timing generator, not shown, of ± N bits for the current frame synchronization timing Assuming that the current frame synchronization timing is t within the range, t-n, t- (n-1), t, t + (n-1), and t + n timing signals are input and received from the comparator 2. It counts up when it matches the timing of the frame timing output signal. Therefore, the count contents of the counter ₅ 1 to 5 _5, the timing signal t-n, t- (n- 1), t, t + (n-1), a predetermined period received frame timing output signal of the timing coincident with t + n Will be equivalent to the content integrated over.
[0023]
The optimum value selection circuit 4 determines the count contents of the counter 5 _{1-5 5} at predetermined time intervals (every predetermined number of frames). Then, reset by a reset signal to the counter ₅ 1 to 5 _5. For example, when the count contents of the counter ₃ in the counter 5 _{1-5 5} shows the maximum value, the optimum value selection circuit 4, the timing of the timing signal t corresponding to the current frame of the synchronization timing, the mask circuit 6, a control signal for continuously passing the reception frame timing signal from the comparator 2 is input.
[0024]
In this case, the current state is maintained, and the frame counter 3 continuously counts the reception frame timing signal output via the mask circuit 6. The frame counter 3 outputs a received frame timing output signal and outputs a frame synchronization signal indicating that frame synchronization has been established when the number of frames corresponding to the number of forward protection stages is continuously counted in the same manner as in the prior art. I do. Various known configurations can be applied to the configuration for controlling the number of rear protection stages for detecting the loss of frame synchronization.
[0025]
The subsequent decision feedback transversal equalizer, not shown, which performs equalization processing on the received demodulated signal, the timing of the equalization processing performed by the current frame synchronization timing, the counter 5 ₁ to 5 _The timing at which the count value of ₅ becomes the maximum is determined by the optimum value selection circuit 4 and is set as the next frame synchronization timing.
[0026]
In addition, in the above-mentioned timing signals t- (n-1), t, t + (n-1), if n = 2 and the current frame timing is 0, the timing signals of -1, 0, +1 are counted. The three counters count received frame timing output signals whose respective timings match. The determination process of the optimum value selection circuit 4 in that case is shown in FIGS.
[0027]
For example, FIG. 2A shows the case where only one counter can obtain the maximum value, and when the count content of the counter that counts the timing signal 0 indicates the maximum value, the current state (current frame) When the count value of the counter that counts the timing signal -1 is maintained at the maximum value while maintaining the synchronization timing), the count content of the counter that counts the timing signal +1 is advanced by one bit from the current position (current frame synchronization timing). Indicates the maximum value, it is determined that the current position is delayed by one bit. As described above, when the count content of one of the plurality of counters has the maximum value, the timing corresponding to the maximum value is set as the next frame synchronization timing in the decision feedback transversal equalizer. Perform an equalization process.
[0028]
As shown in FIG. 2B, when the count contents of the two counters indicate the maximum value at the same time, for example, the count contents of the counters that count the timing signal -1 and the timing signal 0 are both the maximum value. If the value of the counter becomes 1 bit higher than the current value, the contents of the counters for counting the timing signal -1 and the timing signal +1 are both the maximum value. If this happens, the current position is maintained, and if the counts of the counters that count the timing signal 0 and the timing signal +1 both reach the maximum value, the current position is delayed by one bit.
[0029]
Accordingly, for a plurality of reception waves due to multipath or the like, a reception frame timing output signal corresponding to the main wave or the main wave + delayed wave is selected as the next frame synchronization timing. The equalization processing in the versal equalizer is performed, and the equalization ability can be optimized. For the timing signal selected by the optimum value selection circuit 4, frame synchronization is determined by the frame counter 3, and the frame synchronization signal based on the frame synchronization is compared with the timing of the equalization process in the decision feedback transversal equalizer. can do.
[0030]
FIG. 3 is an explanatory diagram of a main part of the receiving apparatus. Reference numeral 10 denotes a frame synchronization circuit, 11 denotes a demodulator (detector), 12 denotes a variable delay unit, and 13 denotes a decision feedback type transversal equalizer. The signal demodulated by the demodulator 11 is input to the variable delay unit 12 and the frame synchronization circuit 10. The frame synchronization circuit 10 has, for example, the configuration shown in FIG. 1, and corresponds to at least the reception timing of the main wave or the delayed wave in the demodulated signal corresponding to the preceding wave, the main wave, or the delayed wave by the demodulator 11. The demodulation signal can be input by controlling the variable delay unit 12 in accordance with the frame synchronization timing so that the optimal timing of the equalization processing in the decision feedback transversal equalizer 13 is obtained.
[0031]
Figure 4 is an explanatory view of a second embodiment of the present invention, FIG. 1 designate the same functional parts, 21 ₁ to 21 ₅ is the moving average calculating unit, the optimum value selection circuit 22, 23 A selector (SEL) is shown, and ct is a control terminal of the selector 23.
[0032]
Moving average calculating unit 21 ₁ to 21 _5, the initial state or a predetermined period at and reset by a reset signal, the timing signal t-n to match the received frame timing output signal and the timing from the comparator 2, t-(n- 1), t, t + (n-1), and t + n are added every predetermined time to obtain a time average over a plurality of frame periods.
[0033]
The optimum value selection circuit 22 determines maximum value of the time average value from the time average calculator 21 ₁ to 21 _5. In this case, as in the case of using the counter 5 ₁ to 5 ₅ shown in FIG. 1, the optimum value selection circuit 22, a timing signal corresponding to the maximum value of the time average value so as to select the output by the selector 23, the selector A control signal is input to the control terminal ct of the control unit 23. The selector 23 selects one of the timing signals t−n, t− (n−1), t, t + (n−1), and t + n according to the control signal input to the control terminal ct, and selects the frame. Input to the counter 3.
[0034]
When the time average value obtained by the plurality of time average calculation units is maximized, as in the case described with reference to FIGS. 1 and 2, the main signal having the excellent equalization ability in the decision feedback transversal equalizer One of a plurality of timing signals t-n, t- (n-1), t, t + (n-1), and t + n so that the interference wave enters the delay side with respect to The selector 23 is controlled by the optimum value selection circuit 22 so as to select a signal.
[0035]
Figure 5 is an explanatory view of a third embodiment of the present invention, FIG. 1 designate the same functional parts, 31 _{1-31 5} integrator 32 is the optimum value selection circuit, 33 denotes a selector ( SEL) and ct indicate control terminals. Data correlator 1 is the correlation of the bit correspondence between the input data and the reference synchronization pattern, is input to the integrator 31 _{1-31 5.} At the integrator ₃₁ 1-31 _5, resets the initial state and a reset signal every predetermined period, the timing signal t-n, t- (n- 1), t, t + (n-1), the timing of t + n Integrate the correlation output.
[0036]
The optimum value selection circuit 32, integrator 31 _1-31 determines the maximum value of the integrated output by _5, the control signal an integrator corresponding timing signal becomes the maximum value to the control terminal ct to selected by the selector 33 Enter Therefore, the functions of the optimum value selection circuit 32 and the selector 33 are the same as those of the optimum value selection circuit 22 and the selector 23 in FIG.
[0037]
Then, the timing signal selected and output from the selector 33 is input to the frame counter 3 as a received frame timing output signal, and when the count content corresponding to the number of forward protection stages is reached, a frame synchronization signal is output to establish frame synchronization. It should be noted that a known configuration can be applied to the configuration for determining out-of-synchronization and the like, and is not illustrated.
[0038]
When the integrated outputs of the plurality of integrators are maximized, as in the case described with reference to FIGS. 1 and 2, the decision feedback transversal equalizer is used for a main wave having an excellent equalizing ability. The optimum value selection circuit 32 controls the selector 33 so that the timing signal at which the interference wave enters the delay side is set to a plurality of timing signals t−n, t− (n−1), t, t + (n−). 1), one timing signal is selected from t + n, and that timing is used as the next frame synchronization timing.
[0039]
Therefore, the decision feedback transversal equalizer that performs the equalization processing of the received demodulated signal performs the equalization processing on a plurality of reception waves due to multipath or the like at a timing excellent in the equalization ability, Even in a state where the environment of the propagation path is not good, reception processing with few errors can be performed.
[0040]
【The invention's effect】
As described above, according to the present invention, the correlation between the received demodulated input data and the reference synchronization pattern is obtained, the maximum value of the correlation value in a predetermined bit range with respect to the current frame synchronization timing is obtained, and the correlation value is calculated. The maximum timing is used as the next frame synchronization timing to perform the equalization processing of the received demodulation signal in the decision feedback transversal equalizer, and the maximum value of the correlation value within a predetermined bit range is plural. When it is obtained, it controls so that the earlier timing in time becomes the next frame synchronization timing, and maximizes the equalization capability of the decision feedback type transversal equalizer with respect to the received wave by multipath. In addition, there is an advantage that equalization processing of a received demodulated signal can be performed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of optimal value selection.
FIG. 3 is an explanatory diagram of a receiving device.
FIG. 4 is an explanatory diagram of a second embodiment of the present invention.
FIG. 5 is an explanatory diagram of a third embodiment of the present invention.
FIG. 6 is an explanatory diagram of a main part of a conventional frame synchronization circuit.
FIG. 7 is an explanatory diagram of a data correlator.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Data correlator 2 Comparator 3 Frame counter 4 Optimum value selection circuit 5 _{1 to} 5 ₅ Counter 6 Mask circuit t-n, t- (n-1), t, t + (n-1), t + n Timing signal

Claims (3)

In a frame synchronization circuit in a receiving apparatus having a decision feedback type transversal equalizer,
A data correlator for obtaining a correlation between received data and a reference synchronization pattern within a range of ± N bits with respect to the current frame synchronization timing;
A comparator for comparing a correlation output signal of the data correlator with a determination threshold,
When the maximum value of the integrated value obtained by integrating the output signal in the range of ± N bits with respect to the current frame synchronization timing of the comparator over a plurality of frame periods is single, the timing of the maximum value is set to the next frame. An optimum value for controlling the input timing of the reception data to the decision feedback transversal equalizer, with the synchronization timing being the timing corresponding to the earlier maximum value in the case of a plurality of times as the next frame synchronization timing. A frame synchronization circuit comprising: a selection circuit. In a frame synchronization circuit in a receiving apparatus having a decision feedback type transversal equalizer,
A data correlator for obtaining a correlation between received data and a reference synchronization pattern within a range of ± N bits with respect to the current frame synchronization timing;
A comparator for comparing a correlation output signal of the data correlator with a determination threshold,
A plurality of moving average calculators each for calculating a moving average value over a plurality of frame periods for output signals at different timings within a range of ± N bits with respect to the current frame synchronization timing of the comparator;
When the maximum value of the moving average values by the plurality of moving average calculation units is single, the timing corresponding to the maximum value is taken as the next frame synchronization timing, and in the case of a plurality of moving average values, the timing corresponds to the earlier maximum value. A frame synchronization circuit comprising: an optimum value selection circuit for controlling the input timing of the input data to the decision feedback transversal equalizer, using the timing as the next frame synchronization timing. In a frame synchronization circuit in a receiving apparatus having a decision feedback type transversal equalizer,
A data correlator for obtaining a correlation between received data and a reference synchronization pattern within a range of ± N bits with respect to the current frame synchronization timing;
A plurality of integrators respectively integrating the correlation output signal of the data correlator at different timings within a range of ± N bits with respect to the current frame synchronization timing;
When the maximum value of the integration values by the plurality of integrators is single, the timing corresponding to the maximum value is set as the next frame synchronization timing, and when the integration value is multiple, the timing corresponding to the earlier maximum value in time And an optimum value selection circuit for controlling the input timing of the input data to the decision feedback transversal equalizer as the next frame synchronization timing.

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