JP2004289322A - Oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit for oscillating a desired frequency, regardless of the surrounding conditions, by which a stable oscillation frequency can be obtained in a satisfactory condition. <P>SOLUTION: This circuit has an oscillation circuit (11) for oscillating at a frequency corresponding to a control voltage, a correcting means (12) for generating a correction signal for correcting the control voltage so that the oscillation frequency of the oscillation means becomes a predetermined frequency, and a hold circuit (13) for holding the correcting signal generated in the correcting means at a predetermined frequency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an oscillation circuit, and more particularly, to an oscillation circuit that oscillates at a desired frequency regardless of surrounding conditions.
[0002]
[Prior art]
In recent years, the frequency band of usable radio waves has been narrowed with the development of communication technology. For this reason, high precision is required for the frequency of the oscillation output of the oscillation circuit mounted on the communication device or the like. However, a vibrator used in an oscillation circuit has a so-called temperature characteristic in which the characteristic of vibration changes according to temperature.
[0003]
For this reason, in the oscillation circuit, correction is performed so that the oscillation frequency does not change due to the change in the oscillation frequency of the vibrator (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP-A-10-290118 (FIG. 1, paragraphs 0040 to 0054)
[0005]
[Problems to be solved by the invention]
However, in the conventional oscillation circuit, the output analog signal of the temperature sensor is converted into digital data, and the converted digital data is subjected to arithmetic processing to remove noise and the like, so that the circuit configuration becomes complicated. With it, it becomes expensive. In addition, since the arithmetic processing is performed, there is a problem that a response to a rise at the time of startup is poor, and further, it is not possible to rapidly respond to a sudden change in an analog signal from a sensor.
[0006]
The present invention has been made in view of the above points, and has as its object to provide an oscillation circuit capable of obtaining a stable oscillation frequency in a state of good responsiveness.
[0007]
[Means for Solving the Problems]
The present invention provides an oscillating means for oscillating at a frequency corresponding to a control voltage, and a correcting means for generating a correction signal for correcting the control voltage so that the oscillating frequency of the oscillating means becomes a predetermined frequency. And a holding means (13) for holding the correction signal generated by the correction means at a predetermined frequency.
[0008]
The holding means (13) includes an analog-digital conversion means (41) for converting the correction signal generated by the correction means (12) into digital data, and a digital data converted by the analog-digital conversion means (41). And a digital-analog conversion means (43) for converting digital data held in the hold circuits (42, 44) into analog signals. I do.
[0009]
According to the present invention, when a correction signal for correcting the oscillation frequency of the oscillation unit (11) to be a predetermined frequency is supplied as a control voltage of the oscillation unit that oscillates at a frequency corresponding to the control voltage, By holding the correction signal at a frequency capable of removing noise included in the correction signal based on the oscillation frequency of the oscillating means, noise included in the correction signal can be removed. Further, at this time, in the present invention, the timing for holding the correction signal is determined based on the oscillation frequency of the oscillating means (11), so that an oscillation circuit for determining the timing for holding is unnecessary, and the correction can be performed with a simple configuration. Noise can be removed from the signal, and power can be saved. Furthermore, since processing such as calculation is not performed, noise can be removed with good responsiveness.
[0010]
Further, according to the present invention, since the operation control such as hold and update can be easily performed by converting the correction signal into digital data, it is possible to quickly reach a desired frequency at the time of startup with a simple configuration. Further, according to the present invention, it is possible to quickly respond to a steep change in the correction signal.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a circuit configuration diagram of an embodiment of the present invention.
[0012]
The oscillating circuit 1 of this embodiment is configured to include a voltage-controlled oscillating circuit 11, a correction circuit 12, and a sampling circuit 13.
[0013]
The voltage-controlled oscillation circuit 11 is configured by, for example, a voltage-controlled crystal oscillation circuit, and has a configuration in which the output oscillation frequency changes according to the control voltage.
[0014]
FIG. 2 is a block diagram showing the configuration of the voltage controlled oscillation circuit 11.
[0015]
The voltage controlled oscillation circuit 11 includes an oscillator 21, an inverter 22, a feedback resistor Rf, DC cut capacitors C1, C2, variable capacitance diodes Cv1, Cv2, and a buffer amplifier 23.
[0016]
The oscillator 21 is composed of, for example, a crystal oscillator, and is connected to the inverter 22 in parallel. The feedback resistor Rf is connected to the inverter 22 in parallel. A variable capacitance diode Cv1 is connected to one end of a parallel circuit composed of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf via a capacitor C1 with a reverse polarity. Further, a variable capacitance diode Cv2 is connected to the other end of the parallel circuit including the crystal oscillator 21, the inverter 22, and the feedback resistor Rf via the capacitor C2 with the opposite polarity. The control voltage Vcnt is applied to the anode of the variable capacitance diode Cv1 via the input resistance Rin1, and the control voltage Vcnt is applied to the anode of the variable capacitance diode Cv2 via the input resistance Rin2. The capacitance of the variable capacitance diodes Cv1 and Cv2 changes according to the control voltage Vcnt. As a result, the capacitance component on the oscillation circuit side as viewed from the crystal oscillator 21 changes, and oscillation occurs at an oscillation frequency corresponding to the control voltage.
[0017]
The other end of the parallel circuit of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf is connected to the output terminal Tout via the buffer amplifier 23. The buffer amplifier 23 amplifies an oscillation signal generated at the other end of the parallel circuit of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf, and supplies the amplified signal to the output terminal Tout.
[0018]
At this time, the oscillation frequency of the voltage controlled oscillation circuit 11 has a so-called temperature characteristic that changes according to the temperature. Generally, the oscillation frequency f is
f = αT ＾ 3 + βT + γ (1)
It is known to have a temperature characteristic approximated by
[0019]
The correction circuit 12 is a circuit for correcting the temperature characteristics of the oscillation frequency, reducing the temperature dependence of the oscillation frequency, and outputting a constant oscillation frequency.
[0020]
The correction circuit 12 includes a reference voltage generation circuit 31, a temperature sensor 32, a cubic function generation circuit 33, conductance amplifiers 34 to 36, and an adder 37. The reference voltage generation circuit 31 is a circuit that generates a reference voltage Vref. The γ component of equation (1) is adjusted by the reference voltage generation circuit 31.
[0021]
The temperature sensor 32 is a circuit that is driven by a reference voltage Vref that is stable with respect to the temperature generated by the reference voltage generation circuit 31 and that generates an output that is a linear function with respect to temperature. The β component of equation (1) is adjusted by the output of the temperature sensor 32.
[0022]
Further, the cubic function generating circuit 33 is a circuit that changes the output of the temperature sensor 32 into a cubic function and outputs the result. The α component of equation (1) is adjusted by the output of the cubic function generation circuit 33.
[0023]
The reference voltage Vref generated by the reference voltage generation circuit 31 is supplied to the adder 37 after gain adjustment by the conductance amplifier 34. The output of the temperature sensor 35 is supplied to the adder 37 after the gain is adjusted by the conductance amplifier 35. The output of the cubic function generation circuit 33 is supplied to an adder 37 after gain adjustment by a conductance amplifier 35.
[0024]
The adder 37 adds the output of the conductance amplifier 34, the output of the conductance amplifier 35, and the output of the conductance amplifier 36, and outputs the sum. The output of the adder 37 is a signal that corrects the frequency variation according to the temperature in the equation (1). The output of the adder 37 is supplied to the hold circuit 13.
[0025]
FIG. 3 shows a block diagram of the hold circuit 13.
[0026]
The hold circuit 13 is a circuit for reducing low-frequency noise, and includes an analog-digital conversion circuit 41, a memory 42, a digital-analog conversion circuit 43, and a hold control circuit 44.
[0027]
The analog-digital conversion circuit 41 converts the analog output of the adder 37 into digital data. The digital data converted by the analog-digital conversion circuit 41 is supplied to a memory 42 and a hold control circuit 44.
[0028]
The hold control circuit 44 is configured to include comparators 51 and 52, an OR gate 53, a frequency dividing circuit 54, and a register 55. The comparator 51 outputs digital data ΔD according to the difference between the output digital data Di of the analog-digital conversion circuit 41 and the digital data Di−1 stored in the memory 42.
[0029]
The output digital data ΔD of the comparator 51 is supplied to the comparator 52. The comparator 52 is supplied with reference digital data ΔD0 from a register 55 in addition to the output digital data ΔD of the comparator 51. The comparator 52 sets the output to a high level when the output digital data ΔD is larger than the reference digital data ΔD0, and sets the output to a low level when the output digital data ΔD is smaller. The output of the comparator 52 is supplied to an OR gate 53. The OR gate 53 is supplied with a clock from a frequency dividing circuit 54 in addition to the output of the comparator 52.
[0030]
FIG. 4 shows a block diagram of the frequency dividing circuit section 54.
[0031]
The frequency dividing circuit section 54 is a circuit for speeding up the startup. The frequency dividing section 54 divides the oscillation output from the voltage controlled oscillation circuit 11 to a frequency lower than the frequency of the low-frequency noise component, and stores the memory at the time of startup. This is a circuit unit for controlling the circuit 42 to be always updated, and includes an inverter 61, a frequency divider 62, an OR gate 63, a NAND gate 64, and a T-flip-flop 65.
[0032]
The oscillation output of the voltage controlled oscillation circuit 11 is supplied to the inverter 61. The inverter 61 inverts the oscillation output of the voltage controlled oscillation circuit 11 and supplies the inverted output to the frequency divider 62 and the NAND gate 64. The frequency divider 62 divides the frequency of the output of the inverter 61 to a preset frequency, for example, a frequency lower than low frequency noise of about several tens Hz. The output of the frequency divider 62 is supplied to an OR gate 63.
[0033]
On the other hand, the output of the T-flip-flop 65 is supplied to the NAND gate 64 in addition to the output of the inverter 61. NAND gate 64 outputs NAND logic of the output of inverter 61 and T-flip-flop 65. A power-on reset signal is supplied to a reset terminal of the T-flip-flop 65. The power-on reset signal is a signal that is set to a high level when the power is turned on. When the power is turned on, the T-flip-flop 65 is reset by the power-on reset signal, and the output / Q is set to a high level.
[0034]
The OR gate 63 outputs an OR logic of the output of the frequency divider 62 and the output of the NAND gate 65. The output of the OR gate 63 is supplied to the OR gate 53.
[0035]
The OR gate 53 outputs an OR logic of the output of the comparator 52 and the output of the frequency divider 54. The output of the OR gate 53 is supplied to the memory 42.
[0036]
The memory 42 is constituted by a FIFO (first-in-first-out) memory or the like, and sequentially stores and holds digital data from the analog-digital conversion circuit 41 while the hold signal from the hold control circuit 44 is at a high level. . The digital data held in the memory 42 is supplied to a digital-analog conversion circuit 43.
[0037]
The digital-analog conversion circuit 43 converts the digital data held in the memory 42 into an analog signal. The analog signal converted by the digital-analog conversion circuit 43 is applied to the voltage control oscillation circuit 11 as a control voltage. At this time, the analog signal supplied from the digital-analog conversion circuit 43 is a frequency correction voltage corresponding to the temperature. Therefore, the oscillation frequency of the voltage controlled oscillation circuit 11 is controlled by the analog signal from the digital-analog conversion circuit 43 so that the oscillation frequency becomes constant regardless of the temperature.
[0038]
Next, the operation of the circuit will be described. First, the operation when the power is turned on will be described.
[0039]
FIG. 5 is a diagram illustrating the operation of the embodiment of the present invention when the power is turned on. 5A shows the oscillation output of the voltage controlled oscillator circuit 11, FIG. 5B shows the power-on reset signal, FIG. 5C shows the output of the inverter 61, and FIG. 5D shows the output of the T-flip-flop 65. Is shown.
[0040]
When the power is turned on and the power-on reset signal goes high at time t0 as shown in FIG. 5B, the output of the T-flip-flop 65 goes high as shown in FIG. 5D. At this time, if the output of the voltage controlled oscillation circuit 11 has not risen, the inputs of the NAND gate 65 are both at the high level, and the output of the NAND gate 64 is at the low level. Therefore, the output of the T-flip-flop 65 is maintained at a high level as shown in FIG. When the output of the T-flip-flop 65 is maintained at a high level, the output of the OR gate 63 is maintained at a high level, whereby the output of the OR gate 53 is also maintained at a high level. When the output of the OR gate 53 is at a high level, the memory 42 is constantly updated and supplied to the voltage controlled oscillation circuit 11 via the digital-analog converter 43. Therefore, the output of the correction circuit 12 directly affects the voltage-controlled oscillation circuit 11, and the control voltage of the voltage-controlled oscillation circuit 11 can be rapidly changed to a voltage for correcting a target frequency. Therefore, when the voltage controlled oscillation circuit 11 is activated and the oscillation output becomes the operation level Vth, an oscillation output of a desired frequency can be output.
[0041]
When the voltage-controlled oscillation circuit 11 starts operating and the oscillation output rises as shown in FIG. 5A, the input of the NAND gate 64 is inverted to a low level. Therefore, the output of the NAND gate 64 becomes high level. When the output of the NAND gate 64 goes high, the output of the T-flip-flop 65 is inverted to low. When the output of the T-flip-flop 65 is inverted to a low level, the output of the frequency divider 62 is output from the OR gate 63. As a result, the output of the OR gate 53 is the output of either the frequency divider 62 or the comparator 52.
[0042]
When the output of the T flip-flop 65 is inverted to a low level, one input of the NAND gate 64 is set to a low level. Therefore, the output of the NAND gate 64 is at a high level regardless of the output level of the inverter 61. Therefore, the output of the T-flip-flop 65 is maintained at a low level. Therefore, after the activation of the voltage controlled oscillation circuit 11, the output of the OR gate 63 is not affected by the output of the T-flip-flop 65, and the output of the frequency divider 62 is output from the OR gate 63.
[0043]
Therefore, after the power control oscillation circuit 11 rises, the output of the frequency divider 62 is supplied to the OR gate 53. The OR gate 53 supplies one of the output of the frequency divider 62 and the output of the comparison circuit 52 to the memory 42, and the memory 42 updates when the output of the OR gate 53 is at a high level. Therefore, when the temperature is relatively stable, the output of the divider 62 is updated at a frequency lower than the low-frequency noise, the output of the correction circuit 12 changes rapidly, and the input / output data of the memory 42 is Is larger than the reference value, the memory 42 is updated irrespective of the output of the frequency divider 62, and the correction can be performed rapidly.
[0044]
In the present embodiment, the output of the correction circuit 12 for performing temperature correction is held by the hold circuit 13 at a frequency lower than the frequency of the low-frequency noise, and the low-frequency noise to be updated is removed. However, the present invention is not limited to the temperature correction, and can be applied to a case where correction is performed by other factors.
[0045]
In the present embodiment, the digital data converted by the analog-digital conversion circuit 41 is held in the memory 42 at a frequency lower than the frequency of the low-frequency noise. However, the present invention is not limited to this. The output stage of the digital conversion circuit 41 may be latched by the output of the frequency dividing circuit 54.
[0046]
【The invention's effect】
As described above, according to the present invention, when a correction signal for correcting the oscillation frequency of the oscillation unit to be a predetermined frequency is supplied as a control voltage of the oscillation unit that oscillates at a frequency corresponding to the control voltage. By holding the correction signal at a frequency capable of removing noise included in the correction signal based on the oscillation frequency of the oscillating means, noise included in the correction signal can be removed. Further, at this time, in the present invention, the timing for holding the correction signal is determined based on the oscillation frequency of the oscillating means, and an oscillation circuit for determining the timing for holding is unnecessary, and the correction signal in the correction signal can be simply configured. Noise can be removed, and power can be saved. Further, since processing such as calculation is not performed, noise can be removed with good responsiveness.
[0047]
Further, according to the present invention, since the operation control such as hold and update can be easily performed by converting the correction signal into digital data, it is possible to quickly reach a desired frequency at the time of startup with a simple configuration. Further, according to the present invention, it is possible to quickly respond to a steep change in the correction signal.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 2 is a block diagram of a voltage controlled oscillation circuit 11;
FIG. 3 is a block diagram of a hold circuit 13;
FIG. 4 is a block diagram of a frequency dividing circuit unit 54;
FIG. 5 is an explanatory diagram of an operation when power is turned on according to an embodiment of the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 oscillation circuit 11 voltage-controlled oscillation circuit, 12 correction circuit, 13 hold circuit 21 oscillator, 22 inverter, 23 output amplifier 31 reference voltage generation circuit, 32 temperature sensor, 33 cubic function generation circuit 34, 35, 36 amplifier, 37 Adder 41 analog-digital conversion circuit, 42 memory 43 digital-analog conversion circuit, 44 hold circuits 51, 52 comparator, 53 OR gate, 54 frequency dividing circuit section 61 inverter, 62 frequency divider, 63 OR gate, 64 NAND Gate 65 T-flip-flop

Claims (6)

Oscillating means for oscillating at a frequency according to the control voltage;
Correction means for generating a correction signal for correcting the control voltage so that the oscillation frequency of the oscillation means is a predetermined frequency,
Holding means for holding the correction signal generated by the correction means at a frequency corresponding to an oscillation frequency corresponding to the oscillation means. An analog-digital converter for converting the correction signal generated by the correction unit into digital data,
A hold circuit that holds digital data converted by the analog-digital conversion means at a frequency corresponding to an oscillation frequency corresponding to the oscillation means;
3. The oscillation circuit according to claim 1, further comprising digital-analog conversion means for converting the digital data held by said hold circuit into an analog signal. 3. The oscillation circuit according to claim 1, wherein said holding means has frequency dividing means for dividing the oscillation frequency of said oscillation means to generate said predetermined frequency. The oscillation circuit according to claim 1, wherein the predetermined frequency is a frequency corresponding to an oscillation frequency of the oscillation unit. The oscillation circuit according to any one of claims 1 to 4, wherein the predetermined frequency is set to a frequency lower than a frequency of a noise component. 6. The oscillation circuit according to claim 1, wherein the correction unit generates a correction signal for correcting a change in an oscillation frequency of the oscillation unit according to an ambient temperature.

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