JP2004282616A - Multi-channel d/a converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-channel D/A converter in which the power consumption can be reduced for every channel while suppressing increase of circuit area. <P>SOLUTION: Currents which flow to current cell transistors 11_11, 11_12, ...; 12_11, 12_12, ...; 13_11, 13_12, ...; constituting current cell type D/A converters 11, 12, 13 for first, second, third channels are cut off by turning off PMOS (P-channel metal oxide semiconductor) transistors 11_31, 12_31, 13_31 by applying voltages Vdd from switching elements 21_1, 22_1, 23_1 constituting power down circuits 21, 22, 23 thereto. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multi-channel D / A converter including a plurality of current cell D / A converters for generating an analog signal corresponding to digital data.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a plurality of current cell transistors are provided, and among the plurality of current cell transistors, currents flowing through a number of current cell transistors corresponding to digital data are merged to generate an analog signal corresponding to the digital data. A multi-channel D / A converter having a plurality of current cell D / A converters is known.
[0003]
FIG. 2 is a diagram showing a circuit of a conventional multi-channel DA converter.
[0004]
The multi-channel DA converter 100 shown in FIG. 2 is a multi-channel DA converter having three channels. The multi-channel DA converter 100 includes a current control circuit 10 and a first channel A current cell type DA converter 11, a current cell type DA converter 12 for the second channel, and a current cell type DA converter 13 for the third channel are provided.
[0005]
The current control circuit 10 has a terminal 10_1 to which the reference voltage VREF is input, an operational amplifier 10_2 having the terminal 10_1 connected to the negative-phase input side (-), a gate connected to the output of the operational amplifier 10_2, and a source. A PMOS transistor 10_3 connected to the power supply Vdd, and a terminal 10_4 for an external resistor connected to the drain of the PMOS transistor 10_3 and the positive-phase input side (+) of the operational amplifier 10_2. A resistor 10_5 is connected between the terminal 10_4 and the ground GND.
[0006]
The first channel current cell type DA converter 11 includes a plurality of current cell transistors 11_11, 11_12,... And a PMOS transistor 11_21 (actually, a plurality of PMOS transistors 11_21) arranged between the current cell transistor 11_11 and the ground GND. A plurality of PMOS transistors are arranged corresponding to the current cell transistors 11_11, 11_12,..., But one PMOS transistor 11_21 is shown here by way of example) and a connection point between the current cell transistor 11_11 and the PMOS transistor 11_21. The connected PMOS transistors 11_31 (actually, a plurality of PMOS transistors are arranged corresponding to the plurality of current cell transistors 11_11, 11_12,. 31 and are shown) and terminal 11_32 for current output, are provided a resistor 11_33 deployed between its terminals 11_32 and ground GND. The gate voltage VG from the operational amplifier 10_2 is input to the gates of the plurality of current cell transistors 11_11, 11_12,..., The digital data DATA is input to the gate of the PMOS transistor 11_21, and the gate of the PMOS transistor 11_31 is referred to. Voltage VREF is input.
[0007]
The current cell type DA converter 12 for the second channel includes a plurality of current cell transistors 12_11, 12_12,..., A PMOS transistor 12_21 disposed between the current cell transistor 12_11 and the ground GND, and a current cell transistor. A PMOS transistor 12_31 connected to a connection point between the PMOS transistor 12_11 and the PMOS transistor 12_21, a current output terminal 12_32, and a resistor 12_33 provided between the terminal 12_32 and the ground GND are provided. The gate voltage VG from the operational amplifier 10_2 is input to the gates of the plurality of current cell transistors 12_11, 12_12,..., The digital data DATA is input to the gate of the PMOS transistor 12_21, and the gate of the PMOS transistor 12_31 is referred to. Voltage VREF is input.
[0008]
Further, the current cell type DA converter 13 for the third channel includes a plurality of current cell transistors 13_11, 13_12,..., A PMOS transistor 13_21 disposed between the current cell transistor 13_11 and the ground GND, and a current cell transistor. A PMOS transistor 13_31 connected to a connection point of the PMOS transistor 13_11 and the PMOS transistor 13_21, a current output terminal 13_32, and a resistor 13_33 provided between the terminal 13_32 and the ground GND are provided. The gate voltage VG from the operational amplifier 10_2 is input to the gates of the plurality of current cell transistors 13_11, 13_12,..., The digital data DATA is input to the gate of the PMOS transistor 13_21, and the gate of the PMOS transistor 13_31 is referred to. Voltage VREF is input.
[0009]
The multi-channel DA converter 100 includes an external capacitor terminal 31 for stabilizing the gate voltage VG, and an external capacitor 32 is connected between the terminal 31 and the power supply Vdd. ing.
[0010]
In the multi-channel DA converter 100 configured as described above, the current flowing through the PMOS transistor 10_3 included in the current control circuit 10 is converted into a monitor voltage by the resistor 10_5 and input to the positive-phase input side (+) of the operational amplifier 10_2. Is done. The operational amplifier 10_2 controls the gate voltage VG of the PMOS transistor 10_3 such that the monitor voltage input to the positive-phase input side (+) becomes equal to the reference voltage VREF input to the negative-phase input side (−). Here, the PMOS transistor 11_21 corresponding to the first channel current cell transistor 11_11 is turned on / off according to the logic of the digital data DATA, whereby the current IOUT1 corresponding to the digital data DATA is changed to the PMOS transistor 11_31, the terminal 11_32, It flows to the ground GND via the resistor 11_33. In practice, of the plurality of current cell transistors 11_11, 11_12,..., The currents flowing through the number of current cell transistors corresponding to the digital data DATA are combined via the PMOS transistor 11_31, and I · V It is converted and output as an analog signal voltage. Thus, DA conversion in the first channel is performed. DA conversion in the second and third channels is also performed in the same manner as in the first channel.
[0011]
In the above-described multi-channel DA converter 100, measures are taken to reduce power consumption when not in use.
[0012]
FIG. 3 is a diagram showing a circuit for reducing power consumption when the multi-channel DA converter shown in FIG. 2 is not used.
[0013]
FIG. 3 shows a PMOS transistor 10_2a, an NMOS transistor 10_2b, and an output terminal 10_2c, which constitute an output section of the operational amplifier 10_2 shown in FIG. Further, a terminal 101 to which the power down signal PD is input and a PMOS transistor 102 provided between the power supply Vdd and the output terminal 10_2c are shown.
[0014]
In the normal operation state in which DA conversion is performed in the multi-channel DA converter 100, an “H” level is applied to the terminal 101 as the power-down signal PD. Therefore, the PMOS transistor 102 is turned off, and the above-described voltage VG is output from the output terminal 10_2c of the operational amplifier 10_2.
[0015]
Here, in order to reduce the power consumption of the multi-channel DA converter 100, the power down signal PD changes from “H” level to “L” level. Then, the PMOS transistor 102 is turned on, and the output terminal 10_2c of the operational amplifier 10_2 is pulled up to the power supply Vdd. Thereby, all the current cell transistors 11_11, 11_12,...; 12_11, 12_12,...; 13_11, 13_12,. Therefore, the power consumption of the multi-channel DA converter 100 can be reduced.
[0016]
In addition, a current cell type DA converter which has an operation standby state in which power consumption is reduced and a normal operation state, and can immediately return from the operation standby state to a normal operation state has been proposed (Japanese Patent Application Laid-Open No. H10-163,086). Reference 1). A multi-channel DA converter can be configured by providing a plurality of such current cell DA converters.
[0017]
[Patent Document 1]
JP-A-11-243338
[Problems to be solved by the invention]
In general, in a multi-channel DA converter, only a specific one of a plurality of channels may operate. In such a case, it is preferable to reduce the power consumption in the remaining inactive channels except for the specific channel. However, since the above-described multi-channel DA converter 100 realizes low power consumption by pulling up the output of the operational amplifier 10_2, the operation stops for all channels, and the specific channel It is difficult to reduce the power consumption in the remaining non-operating channels except for.
[0019]
Further, even when a multi-channel D / A converter is provided with a plurality of current cell D / A converters proposed in Patent Document 1, the output of one operational amplifier common to the plurality of channels is controlled. Since the power consumption is reduced, the operation of all the channels is stopped, and it is difficult to reduce the power consumption of the remaining non-operating channels except for the specific channel. Therefore, there is a problem that the power consumption of the multi-channel DA converter is not reduced.
[0020]
In order to solve this problem, it is conceivable to provide a plurality of operational amplifiers corresponding to a plurality of channels. However, providing a plurality of operational amplifiers causes a problem that the circuit area increases.
[0021]
In view of the above circumstances, it is an object of the present invention to provide a multi-channel DA converter that can reduce power consumption for each channel while suppressing an increase in circuit area.
[0022]
[Means for Solving the Problems]
A multi-channel DA converter according to the present invention that achieves the above object has a plurality of current cell transistors, and, of the plurality of current cell transistors, merges currents flowing through a number of current cell transistors corresponding to digital data. Thereby, in a multi-channel DA converter having a plurality of channels of a current cell type DA converter for generating an analog signal corresponding to the digital data,
A power down circuit for each channel is provided, which independently interrupts a current flowing through a current cell transistor constituting each channel for each channel.
[0023]
The multi-channel DA converter according to the present invention includes the power down circuit for each channel that independently blocks the current flowing through the current cell transistor constituting each channel for each channel. Even when only a specific channel operates, the power consumption in the remaining channels is reduced by cutting off the current flowing through the current cell transistors constituting the remaining channels excluding the specific channel. be able to. Therefore, it is not necessary to provide a plurality of operational amplifiers corresponding to a plurality of channels, and it is possible to reduce power consumption while suppressing an increase in circuit area.
[0024]
Here, corresponding to each current cell transistor, a first transistor that conducts or cuts off a current flowing through the current cell transistor according to digital data, and a current that flows through the current cell transistor by cutting off the first transistor A second transistor that allows current to flow to the output side,
The power down circuit for each channel may be configured to cut off the second transistor corresponding to the current cell transistor forming each channel when interrupting the current flowing through the current cell transistor forming each channel. preferable.
[0025]
In this case, the current flowing through the current cell transistors constituting each channel can be easily and independently cut off for each channel.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0027]
FIG. 1 is a diagram showing a circuit of a multi-channel DA converter according to one embodiment of the present invention.
[0028]
The same components as those of the above-described multi-channel DA converter 100 shown in FIG. 2 are denoted by the same reference numerals.
[0029]
The multi-channel DA converter 1 shown in FIG. 1 is different from the multi-channel DA converter 100 having the channels shown in FIG. 2 in that a power down circuit 21, 22, 23 for each channel is added. I have. The power down circuits 21, 22, 23 for each channel are circuits that independently cut off the current flowing through the current cell transistors constituting each channel for each channel. Specifically, the power-down circuit 21 cuts off the current flowing through the current cell transistors 11_11, 11_12,... Constituting the current cell type DA converter 11 for the first channel. Further, the power down circuit 22 cuts off the current flowing through the current cell transistors 12_11, 12_12,... Constituting the second channel current cell type DA converter 12. Further, the power-down circuit 23 cuts off the current flowing through the current cell transistors 13_11, 13_12,... Constituting the current cell type DA converter 13 for the third channel.
[0030]
Here, the PMOS transistor 11_31 constituting the current cell type DA converter 11 corresponds to an example of the second transistor according to the present invention, and the PMOS transistor 11_31 outputs a current flowing through the current cell transistors 11_11, 11_12,. It plays the role of flowing to the side. Further, the PMOS transistor 11_21 provided in parallel with the PMOS transistor 11_31 corresponds to an example of the first transistor according to the present invention, and the PMOS transistor 11_21 converts a current flowing through the current cell transistors 11_11, 11_12,. It plays a role of conducting or blocking according to DATA.
[0031]
The PMOS transistor 12_31 constituting the current cell type DA converter 12 corresponds to another example of the second transistor according to the present invention, and the PMOS transistor 12_31 transmits a current flowing through the current cell transistors 12_11, 12_12,. It plays the role of flowing to the output side. The PMOS transistor 12_21 provided in parallel with the PMOS transistor 12_31 corresponds to another example of the first transistor according to the present invention. The PMOS transistor 12_21 generates a current flowing through the current cell transistors 12_11, 12_12,. It plays a role of conducting or blocking according to the digital data DATA.
[0032]
Further, the PMOS transistor 13_31 constituting the current cell type DA converter 13 corresponds to still another example of the second transistor according to the present invention, and the PMOS transistor 13_31 has a current flowing through the current cell transistors 13_11, 13_12,. To the output side. Further, the PMOS transistor 13_21 provided in parallel with the PMOS transistor 13_31 corresponds to still another example of the first transistor according to the present invention, and the PMOS transistor 13_21 has a current flowing through the current cell transistors 13_11, 13_12,. In accordance with the digital data DATA.
[0033]
The power-down circuit 21 includes switching elements 21_1, 21_3, an inverter 21_2, and a terminal 21_4 to which a first power-down signal PD1 is input, and interrupts a current flowing through the current cell transistors 11_11, 11_12,. In this case, the PMOS transistors 11_31 corresponding to the current cell transistors 11_11, 11_12,... Constituting the first channel are turned off.
[0034]
The power-down circuit 22 includes switching elements 22_1, 22_3, an inverter 22_2, and a terminal 22_4 to which a second power-down signal PD2 is input, and interrupts current flowing through the current cell transistors 12_11, 12_12,. In this case, the PMOS transistors 12_31 corresponding to the current cell transistors 12_11, 12_12,... Constituting the second channel are turned off.
[0035]
The power-down circuit 23 includes switching elements 23_1, 23_3, an inverter 23_2, and a terminal 23_4 to which a third power-down signal PD3 is input, and interrupts a current flowing through the current cell transistors 13_11, 13_12,. In this case, the PMOS transistors 13_31 corresponding to the current cell transistors 13_11, 13_12,... Constituting the third channel are turned off.
[0036]
Next, the operation of the multi-channel DA converter 1 configured as described above will be described. First, a normal operation state in which power consumption is not reduced will be described.
[0037]
In a normal operation state, the “L” level is input to the terminals 21_4, 22_4, and 23_4 constituting the power-down circuits 21, 22, and 23 as the power-down signals PD1, PD2, and PD3.
[0038]
An “L” level power-down signal PD1 is input to the positive-phase control terminal of the switching element 21_1, the negative-phase control terminal of the switching element 21_3, and the inverter 21_2 that constitute the power-down circuit 21. An “H” level signal is output from the inverter 21_2 and input to the negative phase control terminal of the switching element 21_1 and the positive phase control terminal of the switching element 21_3. Therefore, the switching elements 21_1 and 21_3 are turned off and on, respectively, and the reference voltage VREF is applied to the PMOS transistor 11_31 included in the current cell type DA converter 11 via the switching element 21_3. Similarly, the reference voltage VREF is applied to the PMOS transistor 12_31 forming the current cell type DA converter 12 via the switching element 22_3 forming the power down circuit 22. Further, the reference voltage VREF is applied to the PMOS transistor 13_31 forming the current cell type DA converter 13 via the switching element 23_3 forming the power down circuit 23.
[0039]
In the multi-channel DA converter 1, the currents flowing through the current cell transistors of the number corresponding to the digital data DATA among the plurality of current cell transistors 11_11, 11_12,... , The DA conversion in the first channel is performed. Also, among the plurality of current cell transistors 12_11, 12_12,... Constituting the current cell type DA converter 12, the currents flowing through the number of current cell transistors corresponding to the digital data DATA are combined, and the DA conversion in the second channel is performed. Is performed. Further, of the plurality of current cell transistors 13_11, 13_12,... Constituting the current cell type DA converter 13, currents flowing through the number of current cell transistors corresponding to the digital data DATA are combined, and DA conversion in the third channel is performed. Is performed.
[0040]
Next, a case will be described in which DA conversion is performed only on the first channel and power consumption is reduced in the remaining second and third channels. DA conversion in the first channel is performed as described above. To the terminals 22_4 and 23_4 constituting the power down circuits 22 and 23, the “H” level is input as the power down signals PD2 and PD3 instead of the “L” level. Then, an “H” level power-down signal PD2 is input to the positive-phase control terminal of the switching element 22_1, the negative-phase control terminal of 22_3, and the inverter 22_2 that constitute the power-down circuit 22. An “L” level signal is output from the inverter 22_2 and input to the negative phase control terminal of the switching element 22_1 and the positive phase control terminal of the switching element 22_3. Therefore, the switching elements 22_1 and 22_3 are turned on and off, respectively, and the switching element 22_1 outputs the power supply voltage Vdd. Since the power supply voltage Vdd is applied to the PMOS transistor 12_31 included in the current cell type DA converter 12, the PMOS transistor 12_31 is turned off. Then, the current IOUT2 of the plurality of current cell transistors 12_11, 12_12,... According to the digital data DATA is cut off by the PMOS transistor 12_31.
[0041]
Similarly, the power supply voltage Vdd is output from the switching element 23_1 and applied to the PMOS transistor 13_31 included in the current cell type DA converter 13, so that the PMOS transistor 13_31 is turned off. Thereby, the current IOUT3 of the plurality of current cell transistors 13_11, 13_12,... According to the digital data DATA is cut off by the PMOS transistor 13_31. Therefore, the multi-channel DA converter 1 performs DA conversion in the first channel and reduces power consumption in the second and third channels.
[0042]
As described above, the multi-channel DA converter 1 of the present embodiment outputs the current flowing through the current cell transistors 11_11, 11_12, ...; 12_11, 12_12, ...; 13_11, 13_12, Is provided with a channel-specific power-down circuit 21; 22; 23 that independently shuts off even if only a specific one of the three channels operates. By cutting off the current flowing through the current cell transistors constituting the remaining channels, power consumption in the remaining channels can be reduced. Accordingly, there is no need to provide a plurality of operational amplifiers corresponding to a plurality of channels, and power consumption can be reduced while suppressing an increase in circuit area.
[0043]
Note that, in the present embodiment, an example of a multi-channel DA converter having three channels has been described. However, the present invention is not limited to this, and the present invention only needs to have a plurality of channels.
[0044]
【The invention's effect】
As described above, according to the multi-channel DA converter of the present invention, it is possible to reduce power consumption for each channel while suppressing an increase in circuit area.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit of a multi-channel DA converter according to an embodiment of the present invention.
FIG. 2 is a diagram showing a circuit of a conventional multi-channel DA converter.
FIG. 3 is a diagram showing a circuit for reducing power consumption of the multi-channel DA converter shown in FIG. 2;
[Explanation of symbols]
1 Multi-channel DA converter 10 Reference current generating circuits 10_1, 10_4, 31, 11_32, 12_32, 13_32, 21_4, 22_4, 23_4 Terminal 10_2 Operational amplifiers 10_3, 11_21, 11_31, 12_21, 12_31, 13_21, 13_31 PMOS transistors 10_5, 11_33 , 12_33, 13_33 Resistors 11, 12, 13 Current cell type DA converters 11_11, 11_12, ..., 12_11, 12_12, ..., 13_11, 13_12, ... Current cell transistors (PMOS transistors)
21, 22, 23 Power down circuits 21_1, 21_3, 22_1, 22_3, 23_1, 23_3 Switching elements 21_2, 22_2, 23_2 Inverter 32 Capacitor

Claims (2)

A current cell having a plurality of current cell transistors and generating an analog signal according to the digital data by combining currents flowing through a number of current cell transistors corresponding to the digital data among the plurality of current cell transistors Multi-channel D / A converter with multiple channels
A multi-channel D / A converter comprising a power down circuit for each channel for independently blocking a current flowing through a current cell transistor constituting each channel for each channel. A first transistor corresponding to each current cell transistor for conducting or interrupting a current flowing through the current cell transistor in accordance with digital data; and outputting a current flowing through the current cell transistor by interrupting the first transistor. A second transistor flowing to the side,
The power down circuit for each channel, when interrupting a current flowing through a current cell transistor configuring each channel, shuts off the second transistor corresponding to the current cell transistor configuring each channel. 2. The multi-channel DA converter according to claim 1, wherein:

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