JP2004282521A - Vertical deflection circuit and video display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical deflection circuit capable of accurately canceling a current component induced in a vertical deflection coil by a horizontal deflection magnetic field and accurately making forward and return scanning lines in parallel without the need for adjustment and to provide a video display apparatus employing the same. <P>SOLUTION: A crosstalk/step wave dividing circuit 7 divides a vertical deflection current waveform SVI into a crosstalk component CR and a step wave component ST. A parallel processing correction circuit 30 superimposes a second sawtooth wave current HI obtained by a parallel processing correction gain control circuit 9 and a D/A converter 10 onto a vertical deflection current SI on the basis of the step wave component ST. A crosstalk correction circuit 20 superimposes a cross cancel current CI2 obtained by a cross cancel phase gain control circuit 8, a waveform processing section 18, and a D/A converter 19 on the basis of the crosstalk component CR onto the vertical deflection current SI. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a horizontal reciprocating deflection type vertical deflection circuit for reciprocally scanning an electron beam and an image display device.
[0002]
[Prior art]
In the field of display devices such as television receivers, horizontal reciprocating deflection type deflection devices that reciprocally scan an electron beam in order to perform high-resolution display have been proposed.
[0003]
FIG. 11 is a diagram showing a reciprocating deflection system. In FIG. 11, the forward scan lines are indicated by solid lines, and the return scan lines are indicated by broken lines. At the time of forward scanning, the electron beam is scanned from the left side to the right side of the screen, and at the time of backward scanning, the electron beam is scanned from the right side to the left side of the screen.
[0004]
When vertical deflection is performed using the vertical deflection current of the sawtooth wave synchronized with the vertical synchronization signal, the forward scanning line is slightly obliquely downward from the left side to the right side of the screen as shown in FIG. The return scanning line is formed slightly obliquely downward from the right side to the left side of the screen. In this case, in order to improve the image quality, it is necessary to make the forward scan line and the backward scan line parallel as shown in FIG.
[0005]
FIG. 12 is a waveform diagram illustrating a vertical deflection current for parallelizing the forward scan line and the backward scan line. FIG. 12A shows a first sawtooth current that changes in a vertical scanning cycle, FIG. 12B shows a second sawtooth current that changes in a horizontal scanning cycle, and FIG. 5 shows a vertical deflection current. In FIG. 12, 1V indicates one vertical scanning period, and 1H indicates one horizontal scanning period.
[0006]
FIG. 12C is obtained by superimposing the first sawtooth current of FIG. 12A changing in the vertical scanning cycle and the second sawtooth current of FIG. 12B changing in the horizontal scanning cycle. The vertical deflection current shown is obtained. The vertical deflection current in FIG. 12C changes stepwise in the horizontal scanning cycle.
[0007]
In this way, by superimposing the second sawtooth current of FIG. 12B on the first sawtooth current of FIG. 12A, the forward scan line and the return scan as shown in FIG. Are corrected horizontally (for example, see Patent Document 1).
[0008]
However, when the vertical deflection current shown in FIG. 12C is supplied to the vertical deflection coil and the horizontal deflection current is supplied to the horizontal deflection coil, the scanning line may be distorted. This is because a current component due to the horizontal deflection current is induced from the horizontal deflection coil to the vertical deflection coil. When this current component is superimposed on the vertical deflection current, the scanning line is distorted, and the displayed image is distorted.
[0009]
In a conventional deflecting device, the following method has been proposed in order to cancel a current component induced to flow from a horizontal deflection coil to a vertical deflection coil by a horizontal deflection current (for example, see Patent Document 2). A transformer is connected in series with the vertical deflection coil, and a cancellation current 180 degrees out of phase with respect to the horizontal deflection current flowing through the horizontal deflection coil is supplied to the vertical deflection coil via the transformer. Thus, the current component induced in the vertical deflection coil is canceled.
[0010]
[Patent Document 1]
JP-A-3-145378
[Patent Document 2]
JP 2001-026866 A
[0011]
[Problems to be solved by the invention]
However, since the characteristics are different for each video display device, it is necessary to accurately adjust the waveform of the cancel current for each video display device in order to accurately cancel the current component induced in the vertical deflection coil by the horizontal deflection magnetic field. In addition, it is necessary to precisely adjust the amplitude of the sawtooth wave current that changes in the horizontal scanning cycle for each video display device so that the forward and backward scanning lines are exactly parallel. Therefore, time and labor are required for the adjustment work when manufacturing the video display device.
[0012]
SUMMARY OF THE INVENTION An object of the present invention is to make it possible to accurately cancel a current component induced in a vertical deflection coil by a horizontal deflection magnetic field without performing an adjustment operation and to make scanning lines in the forward path and the return path exactly parallel. An object of the present invention is to provide a vertical deflection circuit and a video display device using the same.
[0013]
[Means for Solving the Problems]
A vertical deflection circuit according to the present invention is a vertical deflection circuit that deflects an electron beam in a vertical direction when the electron beam is reciprocated in a horizontal direction by a horizontal deflection coil. A vertical deflection current supply means for generating a vertical deflection current that changes in a wavy manner and changes stepwise in a horizontal scanning cycle and supplies the vertical deflection current to a vertical deflection coil; and a vertical deflection current waveform as a vertical deflection current waveform flowing in the vertical deflection coil. A current waveform detecting means for detecting, a staircase wave component having a step corresponding to a horizontal scanning period in a vertical deflection current waveform detected by the current waveform detecting means, and a crosstalk component superimposed by a horizontal deflection magnetic field from a horizontal deflection coil. And a vertical deflection current supply unit so that a crosstalk component obtained by the waveform division unit is equal to or less than a predetermined value. Correcting means for correcting the generated vertical deflection current, and correcting the vertical deflection current generated by the vertical deflection current supply means such that the substantially horizontal portion of each step of the staircase wave component obtained by the waveform dividing means becomes horizontal. Correction means.
[0014]
In the vertical deflection circuit according to the present invention, the vertical deflection current generated by the vertical deflection current supply means and changing substantially in a sawtooth waveform in the vertical scanning cycle and changing stepwise in the horizontal scanning cycle is supplied to the vertical deflection coil. You. Thereby, a deflecting magnetic field for deflecting the electron beam in the vertical direction is generated. The vertical deflection current supplied to the vertical deflection coil is detected as a vertical deflection current waveform by current waveform detection means. Thereafter, the detected vertical deflection current waveform is divided by the waveform dividing means into a staircase wave component having a step corresponding to the horizontal scanning period and a crosstalk component superimposed by the horizontal deflection magnetic field. The correction means corrects the vertical deflection current generated by the vertical deflection current supply means so that the crosstalk component becomes equal to or less than a predetermined value. On the other hand, the correction means corrects the vertical deflection current generated by the vertical deflection current supply means so that the substantially horizontal portion of each step of the staircase wave component becomes horizontal.
[0015]
Therefore, the current component induced in the vertical deflection coil by the horizontal deflection magnetic field can be accurately canceled without performing the adjustment operation, and the forward and backward scan lines can be accurately parallelized.
[0016]
The waveform division means delays the vertical deflection current waveform obtained by the waveform detection means by one horizontal scanning cycle and two horizontal scanning cycles, and the vertical deflection current waveform obtained by the waveform detection means and one horizontal scan by the delay means. Extraction means for extracting the staircase wave component and the crosstalk component using the vertical deflection current waveform delayed by the period and two horizontal scanning periods.
[0017]
In this case, the vertical deflection current waveform is divided into a staircase component and a crosstalk component using the vertical deflection current waveform delayed by one horizontal scanning period and two horizontal scanning periods by the delay unit, and extracted by the extraction unit. You. Therefore, the vertical deflection current generated by the vertical deflection current supply means can be corrected or corrected based on the staircase wave component and the crosstalk component.
[0018]
The correction means generates a correction current for canceling the crosstalk component so that the crosstalk component obtained by the waveform dividing means becomes a predetermined value or less, and superimposes the correction current on the vertical deflection current supplied by the vertical deflection current supply means. Modified current generating means may be included.
[0019]
In this case, the vertical deflection current is corrected such that the crosstalk component becomes equal to or less than a predetermined value by superimposing the correction current generated by the correction current generating means. Therefore, the current component induced in the vertical deflection coil by the horizontal deflection magnetic field is canceled without performing the adjustment operation.
[0020]
Correction current generation means, a magnetic field waveform detection means for detecting a waveform of a horizontal deflection magnetic field generated from the horizontal deflection coil, a correction waveform generation means for generating a correction waveform based on the waveform detected by the magnetic field waveform detection means, A correction current superimposing means for superimposing a correction current corresponding to the correction waveform generated by the correction waveform generating means on the vertical deflection current may be included.
[0021]
In this case, the waveform of the horizontal deflection magnetic field is detected by the magnetic field waveform detection means, the correction waveform is generated by the correction waveform generation means, and the correction current corresponding to the correction waveform is superimposed on the vertical deflection current. Therefore, it is possible to easily generate a current component that cancels the current component induced in the vertical deflection coil by the horizontal deflection magnetic field.
[0022]
The correction current generator may further include an amplitude and phase adjuster for adjusting the amplitude and phase of the correction waveform generated by the correction waveform generator so that the crosstalk component obtained by the waveform divider is equal to or less than a predetermined value.
[0023]
In this case, the amplitude and phase of the corrected waveform are adjusted by the amplitude and phase adjusting means so that the crosstalk component becomes equal to or less than a predetermined value. Therefore, the current component induced in the vertical deflection coil by the horizontal deflection magnetic field is canceled without performing the adjustment operation.
[0024]
The amplitude and phase adjusting means calculates a difference between the corrected waveform generated by the corrected waveform generating means and the crosstalk component obtained by the waveform dividing means, and calculates the phase at which the amplitude value of the corrected waveform becomes 0 and the absolute value of the amplitude of the corrected waveform. The amplitude and the phase of the correction waveform generated by the correction waveform generating means may be adjusted so that the difference at the phase at which the value becomes the maximum is equal to or less than a predetermined value.
[0025]
In this case, the amplitude / phase adjusting means calculates a difference between the corrected waveform and the crosstalk component, and determines a difference between the phase at which the amplitude value of the corrected waveform becomes 0 and the phase at which the absolute value of the amplitude of the corrected waveform becomes maximum. Adjust the amplitude and phase of the correction waveform so that they are less than or equal to the value. Therefore, the current component induced in the vertical deflection coil by the horizontal deflection magnetic field is canceled without performing the adjustment operation.
[0026]
The vertical deflection current supply means includes a first current supply means for supplying a first sawtooth current that changes in the vertical scanning cycle to the vertical deflection coil, and a horizontal scanning cycle in order to parallelize the forward and return scan lines. And a second current supplying means for supplying a changing second sawtooth current to the vertical deflection coil, wherein the correcting means is arranged such that a substantially horizontal portion of each step of the staircase wave component obtained by the waveform dividing means is horizontal. May further include amplitude correction means for correcting the amplitude of the second sawtooth wave supplied by the second current supply means.
[0027]
In this case, a first sawtooth current that changes in a vertical scanning cycle by the first current supply means and a second sawtooth current that changes in the horizontal scanning cycle are supplied to the vertical deflection coil by the second current supply means. You. Further, the amplitude of the second sawtooth wave is corrected by the amplitude correction means so that the substantially horizontal portion of each step of the staircase wave component becomes horizontal. Therefore, it is possible to make the scanning lines on the forward path and the return path exactly parallel.
[0028]
The amplitude correction means uses the value of the substantially horizontal portion of each step of the staircase wave component at a position corresponding to the predetermined position of the scanning line on the outward path and the return path to determine whether the substantially horizontal portion of each step of the staircase wave component is horizontal. It may be determined whether or not the amplitude of the second sawtooth wave supplied by the second current supply means is determined based on the determination result.
[0029]
In this case, in accordance with the value of the substantially horizontal portion of each step of the staircase wave component at a position corresponding to the predetermined position of the scanning line on the outward path and the return path, the substantially horizontal portion of each step of the staircase wave component is made horizontal. The amplitude of the second sawtooth wave is corrected. Therefore, it is possible to accurately make the scanning lines on the outward path and the returning path parallel without performing an adjustment operation.
[0030]
An image display device according to the present invention is an image display device that displays an image by reciprocally deflecting an electron beam in a horizontal direction, and displays an image on the screen by irradiating the screen with an electron beam based on an image signal. A horizontal deflection circuit including a display means and a horizontal deflection coil for supplying a horizontal deflection current varying in a cycle twice as long as the horizontal scanning cycle to the horizontal deflection coil for reciprocally deflecting the electron beam in the horizontal direction; A vertical deflection circuit that deflects in the vertical direction, a vertical deflection coil, and a vertical deflection that generates a vertical deflection current that changes substantially in a sawtooth waveform in the vertical scanning cycle and changes stepwise in the horizontal scanning cycle and supplies the vertical deflection current to the vertical deflection coil. Current supply means, current waveform detection means for detecting the waveform of the vertical deflection current flowing through the vertical deflection coil as a vertical deflection current waveform, and current waveform detection means. Waveform dividing means for dividing the vertical deflection current waveform into a staircase wave component having a step corresponding to a horizontal scanning period and a crosstalk component superimposed by a horizontal deflection magnetic field from a horizontal deflection coil, and a cross obtained by the waveform dividing means. Correction means for correcting the vertical deflection current generated by the horizontal deflection current supply means so that the talk component is equal to or less than a predetermined value; and a substantially horizontal portion of each step of the staircase wave component obtained by the waveform dividing means so as to be horizontal. Correction means for correcting the vertical deflection current generated by the horizontal deflection current supply means.
[0031]
In the video display device according to the present invention, the vertical deflection current generated by the vertical deflection current supply means and changing substantially in a sawtooth waveform in the vertical scanning cycle and changing stepwise in the horizontal scanning cycle is supplied to the vertical deflection coil. Is detected as a vertical current waveform by the current waveform detection means. Thereafter, the detected vertical current waveform is divided by the waveform dividing means into a staircase wave component having a step corresponding to the horizontal scanning period and a crosstalk component superimposed by the horizontal deflection magnetic field. The correction means corrects the vertical deflection current so that the crosstalk component is equal to or less than a predetermined value. On the other hand, the correction means corrects the vertical deflection current so that the substantially horizontal portion of each step of the staircase wave component becomes horizontal. Therefore, the current component induced in the vertical deflection coil by the horizontal deflection magnetic field can be accurately canceled without performing the adjustment operation, and the forward and backward scan lines can be accurately parallelized.
[0032]
The corrected and corrected vertical deflection current is supplied to a vertical deflection coil, and the electron beam is deflected in the vertical direction. The horizontal deflection circuit supplies a horizontal deflection current that changes in a cycle twice as long as the horizontal scanning cycle to the horizontal deflection coil, and the electron beam is reciprocated in the horizontal direction. Thereby, the screen of the display means is irradiated with the electron beam, and an image is displayed. Therefore, a high-quality image without distortion is displayed on the screen of the display means.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram illustrating a configuration of a video display device including a vertical deflection circuit according to an embodiment of the present invention.
[0034]
1 includes a video signal processing circuit 100, a horizontal deflection circuit 200, a vertical deflection circuit 300, and a CRT (cathode ray tube) 400. The horizontal deflection coil 25 and the vertical deflection coil 3 are attached to the CRT 400. The video signal processing circuit 100 supplies the display signal CS to the CRT 400 based on the video signal VD, supplies the horizontal synchronization signal HS to the horizontal deflection circuit 200 and the vertical deflection circuit 300, and supplies the vertical synchronization signal VS to the vertical deflection circuit 300.
[0035]
The horizontal deflection circuit 200 supplies a horizontal deflection current WI to the horizontal deflection coil 25 to deflect the electron beam in the horizontal direction in the CRT 400 in synchronization with the horizontal synchronization signal HS given from the video signal processing circuit 100.
[0036]
The vertical deflection circuit 300 synchronizes with a horizontal synchronization signal HS and a vertical synchronization signal VS given from the video signal processing circuit 100 and vertically deflects a vertical deflection current SI, which will be described later, to deflect the electron beam in the CRT 400 in the vertical direction. Supply 3
[0037]
FIG. 2 is a block diagram showing a detailed configuration of the vertical deflection circuit 300 according to the embodiment of the present invention. FIG. 3 is a waveform chart of each part for explaining the operation of the vertical deflection circuit 300 of FIG. In FIG. 3, H represents a horizontal scanning period, and V represents a vertical scanning period.
[0038]
As shown in FIG. 2, the vertical deflection circuit 300 includes a sawtooth voltage generator 1, an amplifier 2, a vertical deflection coil 3, a vertical current detection sensor 4, a sample fold circuit 5, an A / D converter (analog / digital converter). 6, crosstalk / staircase wave dividing circuit 7, cross-cancel phase gain control circuit 8, parallelization correction gain control circuit 9, D / A converter (digital / analog converter) 10, horizontal current detection sensor 15, integration circuit 16, A / D converter (analog / digital converter) 17, waveform processing unit 18, D / A converter (digital / analog converter) 19, crosstalk correction circuit 20, parallelization correction circuit 30, feedback circuit 26 And the resistor 27.
[0039]
The sawtooth voltage generating circuit 1 generates a sawtooth vertical deflection voltage VA in synchronization with the vertical synchronization signal VS shown in FIG. 3A, and supplies the vertical deflection voltage VA to one input terminal of the amplifier 2. . The amplifier 2 supplies the first sawtooth current VI shown in FIG. 3B to the vertical deflection coil 3 according to the applied vertical deflection voltage VA.
[0040]
The output terminal of the amplifier 2 is connected to the node N1 via the vertical deflection coil 3, the secondary winding of the transformer 11, and the secondary winding of the transformer 21. The node N1 is connected to the ground terminal via the resistor 27. The node N1 is connected to the other input terminal of the amplifier 2 via the feedback circuit 26.
[0041]
On the other hand, the parallelization correction circuit 30 includes a transformer 11, a drive transistor 12, a damper diode 13, a resonance capacitor 14, and a drive pulse generation circuit 28.
[0042]
The drive pulse generation circuit 28 generates a drive pulse HD shown in FIG. 3C in synchronization with the horizontal synchronization signal HS. Drive transistor 12 turns on and off in response to drive pulse HD shown in FIG. This drive pulse HD changes in the horizontal scanning cycle H. As a result, a current varying in the horizontal scanning synchronization H flows in the primary winding of the transformer 11, and a second sawtooth current HI shown in FIG. 3D varying in the horizontal scanning cycle H is induced in the secondary winding. Is done.
[0043]
As a result, the vertical deflection current SI shown in FIG. 3E in which the second sawtooth current HI is superimposed on the first sawtooth current VI is supplied to the vertical deflection coil 3, and the vertical scanning period is determined according to the vertical deflection current SI. A vertical deflection magnetic field that changes in a sawtooth waveform at V and changes stepwise at a horizontal scanning period H is generated.
[0044]
On the other hand, the horizontal deflection current WI shown in FIG. 3F flows through the horizontal deflection coil 25 in FIG. The horizontal deflection current WI has a cycle twice as long as the horizontal scanning cycle H. The horizontal deflection coil 25 generates a horizontal deflection magnetic field by the horizontal deflection current WI, and deflects the electron beam reciprocally in the horizontal direction. At this time, a current component (hereinafter, referred to as a crosstalk component) is induced in the vertical deflection coil 3 by the horizontal deflection magnetic field flowing through the horizontal deflection coil 25. As a result, the vertical deflection current SI shown in FIG. 3E is distorted as shown by a broken line.
[0045]
On the other hand, a current (hereinafter, referred to as a detection current) DVI proportional to the vertical deflection current SI is detected by the vertical current detection sensor 4 in FIG. 2 and supplied to the sample fold circuit 5. Details of the sample fold circuit 5 will be described later. The sample fold circuit 5 samples the input voltage V1 based on the detection current DVI, and supplies the output voltage V2 to the A / D converter 6. The A / D converter 6 converts the applied output voltage V2 into a digital signal, and supplies the digital signal to the crosstalk / staircase wave dividing circuit 7 as a vertical deflection current waveform SVI.
[0046]
The crosstalk / staircase wave dividing circuit 7 divides the vertical deflection current waveform SVI into a crosstalk component CR and a staircase wave component ST, and supplies the crosstalk component CR to the cross-cancel phase gain control circuit 8 and converts the staircase wave component ST. It is given to the parallelization correction gain control circuit 9. Detailed operations of the cross cancel phase gain control circuit 8 and the parallelization correction gain control circuit 9 will be described later.
[0047]
The parallelization correction gain control circuit 9 supplies the parallelization correction digital signal PL to the D / A converter 10 based on the staircase wave component ST provided from the crosstalk / staircase wave division circuit 7. The D / A converter 10 converts the applied parallelization correction digital signal PL into an analog voltage PA and supplies the analog voltage PA to one end of a primary winding of the transformer 11. Thereby, the amplitude of the second sawtooth current HI induced in the secondary winding of the transformer 11 is corrected.
[0048]
The horizontal current detection sensor 15 detects a current DEI proportional to the horizontal deflection current WI (hereinafter, referred to as a detection current) and supplies the current DEI to the integration circuit 16. The integration circuit 16 converts the detection current DEI into a detection voltage, and supplies the detection voltage to the A / D converter 17. The A / D converter 17 converts the detection voltage into a digital signal and supplies the digital signal to the waveform processing unit 18 as a horizontal deflection current waveform DEH.
[0049]
The cross cancel phase gain control circuit 8 supplies the phase control signal PC and the gain control signal GC to the waveform processing section 18 based on the crosstalk component CR provided by the crosstalk / staircase wave dividing circuit 7.
[0050]
The waveform processing unit 18 includes a memory and a CPU (Central Processing Unit). The memory stores a horizontal deflection current waveform DEH given from the A / D converter 17. The CPU uses the horizontal deflection current waveform DEH stored in the memory to cancel the crosstalk component CR based on the phase control signal PC and the gain control signal CG given from the cross cancellation phase gain control circuit 8. CA is generated and given to the D / A converter 19.
[0051]
The D / A converter 19 converts the cross cancel component CA into an analog cross cancel voltage CV and supplies the analog cross cancel voltage CV to the crosstalk correction circuit 20. The crosstalk correction circuit 20 includes a transformer 21, an amplifier 22, a feedback circuit 23, and a resistor 24.
[0052]
The amplifier 22 of the crosstalk correction circuit 20 amplifies the cross cancel voltage CV provided from the D / A converter 19 and supplies the cross cancel current CI1 to the primary winding of the transformer 21. As a result, the cross cancel current CI2 is superimposed on the distorted vertical deflection current SI indicated by the broken line in FIG. 3E flowing through the secondary winding of the transformer 21. As a result, the distortion of the vertical deflection current SI shown by the broken line is canceled, and the waveform becomes the one shown by the solid line.
[0053]
FIG. 4 is a diagram illustrating the configuration and operation of the sample fold circuit 5. 4A is a circuit diagram showing the configuration of the sample fold circuit 5, FIG. 4B is a waveform diagram of the input voltage V1 of the sample fold circuit 5, and FIG. FIG. 4A is a waveform diagram of the control signal CS supplied to the switch 5a, and FIG. 4D is a waveform diagram of the output voltage V2 of the sample fold circuit 5.
[0054]
As shown in FIG. 4A, the sample fall circuit 5 includes a switch 5a, a capacitor 5b, and a subtractor 5c. The node N2 is connected to one input terminal of the subtractor 5c, and is connected to the node N3 via the switch 5a. The node N3 is connected to the ground terminal via the capacitor 5b and to the other input terminal of the subtractor 5c. Control signal CS is applied to switch 5a.
[0055]
The input voltage V1 of the node N1 of the sample fold circuit 5 changes stepwise as shown in FIG. 4B by the detection current DVI supplied from the vertical current detection sensor 4 of FIG. The switch 5a in FIG. 4A is turned on for a fixed time every four horizontal scanning periods (4H) in response to the control signal CS shown in FIG. 4C. Thereby, the capacitor 5b of FIG. 4A holds the input voltage V1 of the node N2 every four horizontal scanning periods.
[0056]
A stepwise voltage at the node N2 is applied to one input terminal of the subtractor 5c. When the switch 5a is turned on for a certain time at the time point t1 shown in FIG. 4B, the capacitor 5b holds the input voltage Va at the time point t1 and supplies it to the other input terminal of the subtractor 5c. The subtractor 5c subtracts the voltage Va given by the capacitor 5b from the stepped voltage Sa for four horizontal scanning periods from the time point t1, and outputs the result. Next, when the switch 5a is turned on for a predetermined time at time t2 after four horizontal scanning cycles, the capacitor 5b holds the input voltage Vb at time t2 and supplies the same to the other input terminal of the subtractor 5c. The subtractor 5c subtracts the voltage Vb provided by the capacitor 5b from the stepped voltage Sb for four horizontal scanning periods from the time point t2 and outputs the result. As a result, as shown in FIG. 4D, the A / D converter 6 is provided with a stepped output voltage V2 divided every four horizontal scanning periods.
[0057]
Next, the configuration and operation of the crosstalk / staircase wave dividing circuit 7 will be described with reference to FIGS. FIG. 5 is a block diagram showing a detailed configuration of the crosstalk / staircase wave dividing circuit 7. As shown in FIG. FIG. 6 is a waveform diagram of each part showing the operation of the crosstalk / staircase wave dividing circuit 7 of FIG. In FIG. 6, the horizontal axis represents time, and the vertical axis represents current. The numbers on the vertical axis correspond to raster (scanning line) numbers.
[0058]
5, a first delay circuit 35 receives a vertical deflection current waveform SVI from the A / D converter 6 in FIG. The vertical deflection current waveform SVI is obtained by superposing the crosstalk component CR shown in FIG. 6C on the staircase wave component ST shown in FIG. 6B.
[0059]
The first delay circuit 35 delays the vertical deflection current waveform SVI by one horizontal scanning cycle, and supplies the one horizontal delay vertical deflection current waveform SVI1 shown in FIG. 6D to the second delay circuit 36 and the difference circuit 39. . The one horizontal delay vertical deflection current waveform SVI1 is obtained by superposing the crosstalk component CR1 shown in FIG. 6F on the staircase wave component ST1 shown in FIG. 6E.
[0060]
On the other hand, the difference circuit 39 subtracts one horizontal delay vertical deflection current waveform SVI1 from the vertical deflection current waveform SVI supplied from the A / D converter 6, and subtracts the vertical deflection current waveform SVI3 shown in FIG. It is given to the circuit 40. The vertical deflection current waveform SVI3 is obtained by superimposing a crosstalk component CR3 shown in FIG. 6 (l) on a current component waveform corresponding to -1 raster shown in FIG. 6 (k).
[0061]
The second delay circuit 36 further delays the one horizontal delay vertical deflection current waveform SVI1 given from the first delay circuit by one horizontal scanning period, and the two horizontal delay vertical deflection current waveform SVI2 shown in FIG. To the difference circuit 37. The two horizontal delay vertical deflection current waveform SVI2 is obtained by superposing the crosstalk component CR2 shown in FIG. 6 (i) on the staircase component ST2 shown in FIG. 6 (h).
[0062]
The difference circuit 37 subtracts the two horizontal delay vertical deflection current waveforms SVI2 from the vertical deflection current waveform SVI, and supplies a current component waveform SVI4 corresponding to the -2 raster shown in FIG. The current component waveform SVI4 corresponding to -2 rasters is obtained by superimposing the 0-level current component waveform CR4 shown in FIG. 6 (o) on the current component waveform ST4 corresponding to -2 rasters shown in FIG. 6 (n). is there.
[0063]
The arithmetic circuit 38 attenuates the amplitude of the current component waveform SVI4 by half, and supplies the difference circuit 40 with a current component waveform SVI5 corresponding to -1 raster similar to the current component waveform ST3 in FIG.
[0064]
The difference circuit 40 subtracts the current component waveform SVI5 from the vertical deflection current waveform SVI3, and provides a double crosstalk component CR5 similar to the current component waveform CR3 of FIG. The arithmetic circuit 41 attenuates the amplitude of the double crosstalk component CR5 by half, and outputs the crosstalk component CR of the vertical deflection current SVI. Further, the difference circuit 42 subtracts the crosstalk component CR from the vertical deflection current waveform SVI, and outputs a staircase wave component ST of the vertical deflection current waveform SVI.
[0065]
FIG. 7 is a waveform diagram of each section for explaining the operation of the cross cancellation phase gain control circuit 8. FIG. 7A shows a crosstalk component CR output from the crosstalk / staircase wave dividing circuit 7, and FIG. 7B shows a cross cancel component CA output from the waveform processing unit 18, and FIG. ) Is a residual crosstalk component RC. The horizontal axis in FIG. 7 is the phase, and the vertical axis is the amplitude.
[0066]
The cross cancel component CA is output from the waveform processing unit 18 in FIG. 2 to cancel the crosstalk component CR. The residual crosstalk component RC is a component remaining after adding the cross cancel component CA to the crosstalk component CR.
[0067]
If the crosstalk component CR is completely canceled by the cross cancellation component CA, the residual crosstalk component RC becomes 0, but if the phase or amplitude of the cross cancellation component CA is different from the crosstalk component CR, a residual crosstalk component RC is generated. .
[0068]
Here, as shown in FIG. 7, the phases at which the value of the crosstalk component CR becomes 0 are called zero cross points P1 and P3, and the phase P2 at which the amplitude of the crosstalk component CR becomes maximum is called a max point.
[0069]
FIG. 8 is a flowchart showing the operation of the cross cancel phase gain control circuit 8. The operation of the cross-cancel phase gain control circuit 8 will be described with reference to FIGS.
[0070]
First, the cross cancel phase gain control circuit 8 sets a threshold value THR1 for the amplitude of the residual crosstalk component RC in FIG. 7 (step S1). Here, the threshold value THR1 is an allowable value of the amplitude of the residual crosstalk component RC at which the crosstalk component CR is considered to be removed at the zero cross points P1 and P3 and the maximum point P2 of the crosstalk component CR. Therefore, when the absolute value of the amplitude of the residual crosstalk component RC at the zero cross points P1 and P3 of the crosstalk component CR and the absolute value of the amplitude of the residual crosstalk component RC at the maximum point P2 are smaller than the threshold value THR1, It is considered that the crosstalk component CR has been removed.
[0071]
Next, the cross cancellation phase gain control circuit 8 detects the zero cross points P1 and P3 and the maximum point P2 of the crosstalk component CR (Step S2).
[0072]
Next, the cross cancellation phase gain control circuit 8 determines whether or not the absolute value of the amplitude of the residual crosstalk component RC at the zero cross points P1 and P3 of the crosstalk component CR is equal to or larger than the threshold value THR1 (step S3). .
[0073]
When the absolute value of the amplitude of the residual crosstalk component RC at the zero cross points P1 and P3 of the crosstalk component CR is equal to or larger than the threshold value THR1, the cross cancel phase gain control circuit 8 sets the phase of the cross cancel component CA for one clock. The phase control signal PC to be shifted is provided to the waveform processing unit 18 in FIG. 2 (step S5), and the process returns to step S3. Here, one clock refers to a phase corresponding to one pulse of a clock signal.
[0074]
In step S3, when the absolute value of the amplitude of the residual crosstalk component RC at the zero cross points P1 and P3 of the crosstalk component CR is smaller than the threshold value THR1, the cross cancellation phase gain control circuit 8 sets the maximum value of the crosstalk component CR. It is determined whether or not the absolute value of the amplitude of the residual crosstalk component RC at the point P2 is equal to or larger than the threshold value THR1 (step S4).
[0075]
When the absolute value of the amplitude of the residual crosstalk component RC at the maximum point P2 of the crosstalk component CR is equal to or larger than the threshold value THR1, the cross cancellation phase gain control circuit 8 changes the amplitude of the cross cancellation component CA by one step. The gain control signal GC is provided to the waveform processing unit 18 in FIG. 2 (step S6), and the process returns to step S3.
[0076]
In step S4, if the absolute value of the amplitude of the residual crosstalk component RC at the maximum point P2 of the crosstalk component CR is smaller than the threshold value THR1, the cross-cancel phase gain control circuit 8 returns to step S3, and returns to steps S3 to S3. The processing of S6 is repeated.
[0077]
As described above, the crosstalk component control circuit 8 calculates the absolute value of the amplitude of the residual crosstalk component RC at the zero cross points P1 and P3 of the crosstalk component CR and the absolute value of the amplitude of the residual crosstalk component RC at the maximum point P2. A phase control signal PC and a gain control signal GC for controlling the phase and amplitude of the cross cancel component CA so as to be smaller than the threshold value THR1 are given to the waveform processing unit 18.
[0078]
The waveform processing unit 18 generates a cross cancel component CA based on the horizontal deflection current waveform DEH provided from the D / A converter 17, and generates a phase control signal PC and a gain control signal provided from the cross cancel phase gain control circuit 8. The phase and the amplitude of the cross cancel component CA are controlled based on the GC. Thereby, residual crosstalk component RC becomes smaller than threshold value THR1.
[0079]
FIG. 9 is a diagram for explaining the parallelization correction in the parallelization correction gain control circuit 9 of FIG. FIG. 9A shows a staircase wave component ST provided from the crosstalk / staircase wave dividing circuit 7, and FIGS. 9B to 9D are diagrams showing scanning lines in reciprocal scanning.
[0080]
When the amplitude of the second sawtooth current HI of FIG. 3D generated by the parallelization correction circuit 30 of FIG. 2 is appropriate, the staircase wave component ST is horizontal as shown by the solid line in FIG. As shown in FIG. 9C, the scanning lines on the outward path and the returning path are formed horizontally. When the amplitude of the second sawtooth wave current HI is small, the staircase wave component ST is inclined obliquely downward as shown by the broken line in FIG. 9A, and the forward and backward scanning lines are shown in FIG. 9B. Are formed diagonally below. When the amplitude of the second sawtooth wave current HI is large, the staircase wave component ST tilts obliquely upward as shown by the dashed line in FIG. 9A, and scans the forward and return paths as shown in FIG. 9D. The line is formed diagonally above.
[0081]
Here, as shown in FIGS. 9B to 9D, the determination positions POS1, POS2, and POS3 are set at predetermined positions in the horizontal direction on the forward and backward scanning lines. The values of the staircase wave component ST at the determination positions POS1, POS2, and POS3 are defined as I1, I2, and I3, respectively.
[0082]
When the amplitude of the second sawtooth current HI is appropriate, each scanning line is horizontal and the scanning lines are formed in parallel, as shown in FIG. Therefore, the values I1, I2, and I3 of the staircase wave component ST have a proportional relationship, and twice the value I2 is equal to the value (I1 + I3).
[0083]
When the amplitude of the second sawtooth current HI is small, as shown in FIG. 9B, the scanning lines are inclined downward and not parallel, and the value (I1 + I3) is larger than twice the value I2. growing.
[0084]
When the amplitude of the second sawtooth wave current HI is large, as shown in FIG. 9D, the scanning lines are not parallel because they are inclined obliquely upward, and the value (I1 + I3) is larger than twice the value I2. Become smaller.
[0085]
FIG. 10 is a flowchart showing the operation of the parallelization correction gain control circuit 9 of FIG. The operation of the parallelization correction gain control circuit 9 will be described with reference to FIGS.
[0086]
The parallelization correction gain control circuit 9 in FIG. 2 sets the determination positions POS1, POS2, POS3 and the threshold value THR2 in the horizontal scanning period in the staircase wave component ST given from the crosstalk / staircase wave dividing circuit 7 ( Step S10).
[0087]
Here, the determination positions POS1, POS2, and POS3 are on the left side of each scanning line as shown in FIG. The threshold value THR2 is an allowable value at which the staircase wave component ST is considered to be horizontally corrected. Further, the determination value X is set as in the following equation.
[0088]
X = I2- (I1 + I3) / 2
Next, the parallelization correction gain control circuit 9 determines whether the determination value X is larger than the positive threshold value THR2 based on the values I1, I2, and I3 of the staircase wave component ST at the determination positions POS1, POS2, and POS3. It is determined (step S11).
[0089]
When the determination value X is larger than the positive threshold value THR2, the parallelization correction gain control circuit 9 decreases the value of the parallelization correction digital signal PL (Step S13), and returns to Step S11. In this case, the parallelization correction gain control circuit 9 supplies the parallelization correction digital signal PL to the D / A converter 10 in FIG. The D / A converter 10 converts the given parallelized digital signal PL into an analog voltage PA and supplies the analog voltage PA to the parallelization correction circuit 30. Thereby, the amplitude of the second sawtooth current HI decreases.
[0090]
If the determination value X is equal to or smaller than the positive threshold value THR2 in step S11, the parallelization correction gain control circuit 9 determines whether the determination value X is smaller than the negative threshold value -THR2 (step S12). .
[0091]
If the determination value X is smaller than the negative threshold value -THR2, the parallelization correction gain control circuit 9 increases the value of the parallelization correction digital signal PL (Step S14), and returns to Step S11. In this case, the parallelization correction gain control circuit 9 supplies the parallelization correction digital signal PL to the D / A converter 10. The D / A converter 10 converts the applied parallelization correction digital signal PL into an analog voltage PA and supplies the analog voltage PA to the parallelization correction circuit 30. Thereby, the amplitude of the second sawtooth current HI increases.
[0092]
If the determination value X is equal to or greater than the negative threshold value -THR2 in step S12, the parallelization correction gain control circuit 9 returns to step S11.
[0093]
In this way, the staircase wave component ST can be corrected horizontally as shown by the solid line in FIG. 9A, and the scanning lines can be made parallel as shown in FIG. 9C.
[0094]
In the present embodiment, the determination positions POS1, POS2, and POS3 are set on the left side of each scanning line. However, if they are the same in the horizontal direction of each scanning line, they can be set at any positions except the center point. . When the determination positions POS1, POS2, and POS3 are set on the right side of the center point of each scanning line, the value of the parallelization correction digital signal PL is increased in step S13 in FIG. Decrease the value of PL.
[0095]
In the present embodiment, the sawtooth voltage generating circuit 1 and the parallelizing correction circuit 30 correspond to a vertical deflection current supply unit, the vertical current detection sensor 4 corresponds to a current waveform detection unit, and a crosstalk / staircase wave dividing circuit. 7 corresponds to the waveform dividing means, the cross cancel phase gain control circuit 8 corresponds to the correcting means, the parallelization correction gain control circuit 9 corresponds to the correcting means, and the first delay circuit 35 and the second delay circuit 36 Corresponds to the delay means, the cross-cancel phase gain control circuit 8 and the parallelization correction gain control circuit 9 correspond to the extraction means, and the horizontal current detection sensor 15, the integration circuit 16, the A / D converter 17, and the waveform processing section 18 Corresponds to the correction current generation means, the horizontal current detection sensor 15 corresponds to the magnetic field waveform detection means, the waveform processing section 18 corresponds to the correction waveform generation means, and The circuit 20 corresponds to a correction current superimposing unit, the waveform processing unit 18 corresponds to an amplitude / phase adjusting unit, the amplifier 2 corresponds to a first current supplying unit, the amplifier 22 corresponds to a second current supplying unit, The parallelization correction gain control circuit 9 corresponds to an amplitude correction unit.
[0096]
【The invention's effect】
In the vertical deflection circuit according to the present invention, the vertical deflection current generated by the vertical deflection current supply means and changing in a substantially sawtooth manner in the vertical scanning cycle and changing stepwise in the horizontal scanning cycle is supplied to the vertical deflection coil. Is detected as a vertical deflection current waveform by the current waveform detection means. Thereafter, the detected vertical deflection current waveform is divided by the waveform dividing means into a staircase wave component having a step corresponding to the horizontal scanning period and a crosstalk component superimposed by the horizontal deflection magnetic field. The correction means corrects the vertical deflection current generated by the vertical deflection current supply means so that the crosstalk component becomes equal to or less than a predetermined value. On the other hand, the correction means corrects the vertical deflection current generated by the vertical deflection current supply means so that the substantially horizontal portion of each step of the staircase wave component becomes horizontal.
[0097]
Therefore, the current component induced in the vertical deflection coil by the horizontal deflection magnetic field can be accurately canceled without performing the adjustment operation, and the forward and backward scan lines can be accurately parallelized.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a video display device including a vertical deflection circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed configuration of a vertical deflection circuit according to the embodiment of the present invention.
FIG. 3 is a waveform chart of each part for explaining the operation of the vertical deflection circuit of FIG. 2;
FIG. 4 illustrates a configuration and operation of a sample fold circuit.
FIG. 5 is a block diagram showing a detailed configuration of a crosstalk / staircase wave dividing circuit.
FIG. 6 is a waveform chart of each part showing the operation of the crosstalk / staircase wave dividing circuit of FIG. 5;
FIG. 7 is a waveform chart of each part for explaining the operation of the cross cancel phase gain control circuit.
FIG. 8 is a flowchart showing the operation of the cross cancellation phase gain control circuit.
9 is a diagram for explaining correction of parallelization in the parallelization correction gain control circuit of FIG. 2;
FIG. 10 is a flowchart showing the operation of the parallelization correction gain control circuit 9 of FIG. 2;
FIG. 11 is a diagram showing a reciprocating deflection system.
FIG. 12 is a waveform diagram illustrating a vertical deflection current for parallelizing a forward scan line and a backward scan line.
[Explanation of symbols]
1. Sawtooth voltage generator
2,22 amplifier
3 Vertical deflection coil
4 Vertical current detection sensor
5 Sample fold circuit
6,17 A / D converter
7 Crosstalk / staircase wave division circuit
8 Cross cancel phase gain control circuit
9 Parallelization correction gain control circuit
10,19 D / A converter
15 Horizontal current detection sensor
16 Integrator
18 Waveform processing unit
20 Crosstalk correction circuit
25 Horizontal deflection coil
30 Parallelization correction circuit
35. First delay circuit
36 Second delay circuit
100 Video signal processing circuit
200 horizontal deflection circuit
300 vertical deflection circuit
CA Cross cancel component
CR crosstalk component
GC gain control signal
PC phase control signal
RC residual crosstalk component
ST Step wave component

Claims (9)

A vertical deflection circuit that deflects the electron beam in the vertical direction when the electron beam is reciprocated in the horizontal direction by the horizontal deflection coil,
A vertical deflection coil,
Vertical deflection current supply means for generating a vertical deflection current that changes substantially in a sawtooth waveform in a vertical scanning cycle and changes stepwise in a horizontal scanning cycle and supplies the vertical deflection current to the vertical deflection coil;
Current waveform detecting means for detecting a waveform of a vertical deflection current flowing through the vertical deflection coil as a vertical deflection current waveform,
Waveform dividing means for dividing the vertical deflection current waveform detected by the current waveform detection means into a staircase wave component having a step corresponding to a horizontal scanning period and a crosstalk component superimposed by a horizontal deflection magnetic field from the horizontal deflection coil. When,
Correction means for correcting the vertical deflection current generated by the vertical deflection current supply means so that the crosstalk component obtained by the waveform dividing means is equal to or less than a predetermined value;
Correction means for correcting the vertical deflection current generated by the vertical deflection current supply means so that the substantially horizontal portion of each step of the staircase wave component obtained by the waveform dividing means is horizontal. Vertical deflection circuit. The waveform dividing means,
Delay means for delaying the vertical deflection current waveform obtained by the waveform detection means by one horizontal scanning cycle and two horizontal scanning cycles;
Extraction of extracting the staircase wave component and the crosstalk component using a vertical deflection current waveform obtained by the waveform detection means and a vertical deflection current waveform delayed by one horizontal scanning cycle and two horizontal scanning cycles by the delay means. 2. The vertical deflection circuit according to claim 1, further comprising: The correcting means includes:
A correction current for canceling the crosstalk component is generated so that the crosstalk component obtained by the waveform dividing means is equal to or less than a predetermined value, and the correction current is superimposed on the vertical deflection current supplied by the vertical deflection current supply means. 3. The vertical deflection circuit according to claim 1, further comprising a current generating means. The correction current generating means includes:
Magnetic field waveform detection means for detecting the waveform of a horizontal deflection magnetic field generated from the horizontal deflection coil,
Correction waveform generation means for generating a correction waveform based on the waveform detected by the magnetic field waveform detection means,
4. The vertical deflection circuit according to claim 3, further comprising correction current superimposing means for superimposing the correction current corresponding to the correction waveform generated by the correction waveform generation means on the vertical deflection current. The correction current generating means includes:
2. The apparatus according to claim 1, further comprising an amplitude / phase adjusting unit configured to adjust an amplitude and a phase of the corrected waveform generated by the corrected waveform generating unit such that a crosstalk component obtained by the waveform dividing unit is equal to or less than a predetermined value. 5. The vertical deflection circuit according to 4. The amplitude and phase adjustment means,
The difference between the corrected waveform generated by the corrected waveform generating means and the crosstalk component obtained by the waveform dividing means is calculated, and the phase at which the amplitude value of the corrected waveform becomes 0 and the absolute value of the amplitude of the corrected waveform are calculated. 6. The vertical deflection circuit according to claim 5, wherein the amplitude and the phase of the correction waveform generated by the correction waveform generating means are adjusted so that the difference at the phase with the maximum value is equal to or less than a predetermined value. The vertical deflection current supply means,
First current supply means for supplying a first sawtooth current varying in a vertical scanning cycle to the vertical deflection coil;
Second current supply means for supplying a second sawtooth current that changes in a horizontal scanning cycle to the vertical deflection coil in order to parallelize a forward scan line and a return scan line,
The correction means,
An amplitude correction unit for correcting the amplitude of the second sawtooth wave supplied by the second current supply unit so that a substantially horizontal portion of each step of the staircase wave component obtained by the waveform division unit becomes horizontal. The vertical deflection circuit according to claim 1, wherein: The amplitude correction means,
Using the value of the substantially horizontal portion of each step of the staircase wave component at a position corresponding to the predetermined position of the scanning line on the outward path and the return path, it is determined whether or not the substantially horizontal portion of each step of the staircase wave component is horizontal. 8. The vertical deflection circuit according to claim 7, wherein the determination is performed, and the amplitude of the second sawtooth wave supplied by the second current supply unit is corrected based on the determination result. An image display device for displaying an image by reciprocally deflecting the electron beam in a horizontal direction,
Display means for displaying an image on the screen by irradiating the screen with an electron beam based on the image signal,
A horizontal deflection circuit that includes a horizontal deflection coil, and supplies a horizontal deflection current that changes in a cycle twice as long as a horizontal scanning cycle to the horizontal deflection coil in order to deflect the electron beam in a horizontal direction;
A vertical deflection circuit that deflects the electron beam in a vertical direction,
A vertical deflection coil,
Vertical deflection current supply means for generating a vertical deflection current that changes substantially in a sawtooth waveform in a vertical scanning cycle and changes stepwise in a horizontal scanning cycle and supplies the vertical deflection current to the vertical deflection coil;
Current waveform detecting means for detecting a waveform of a vertical deflection current flowing through the vertical deflection coil as a vertical deflection current waveform,
Waveform dividing means for dividing the vertical deflection current waveform detected by the current waveform detection means into a staircase wave component having a step corresponding to a horizontal scanning period and a crosstalk component superimposed by a horizontal deflection magnetic field from the horizontal deflection coil. When,
Correction means for correcting the vertical deflection current generated by the horizontal deflection current supply means so that the crosstalk component obtained by the waveform division means is equal to or less than a predetermined value;
A correction means for correcting a vertical deflection current generated by the horizontal deflection current supply means so that a substantially horizontal portion of each step of the staircase wave component obtained by the waveform dividing means is horizontal. Display device.

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