JP2004273771A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
JP2004273771A
JP2004273771A JP2003062622A JP2003062622A JP2004273771A JP 2004273771 A JP2004273771 A JP 2004273771A JP 2003062622 A JP2003062622 A JP 2003062622A JP 2003062622 A JP2003062622 A JP 2003062622A JP 2004273771 A JP2004273771 A JP 2004273771A
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Japan
Prior art keywords
opening
film
semiconductor device
laser
substrate
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JP2003062622A
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Japanese (ja)
Inventor
Akira Amano
彰 天野
Hideki Kino
秀樹 喜納
Hiroshi Machida
浩 町田
Tsutomu Kato
勉 加藤
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Priority to JP2003062622A priority Critical patent/JP2004273771A/en
Publication of JP2004273771A publication Critical patent/JP2004273771A/en
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Drying Of Semiconductors (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of more simplifying the process of a photolithography than a conventional method at a low cost, decreasing a defective damage such as a crack or the like of the semiconductor device using a thin substrate, and decreasing an occurrence of exfoliation or the like of an Al wire by further satisfactorily removing the residue left at an opening surface after a laser abrasion. <P>SOLUTION: The method for manufacturing the semiconductor device has an opening formed on a surface protecting film of a metal wiring electrode film by a laser abrasion after the surface protecting film consisting primarily of a resin is coated on the metal wiring electrode film of the semiconductor substrate. After the opening is formed by the laser abrasion under decompressed atmospheres through a pattern mask corresponding to the opening, a cleaning treatment including a plasma ashing treatment is processed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は半導体基板や多層配線基板上に形成される各種半導体素子、各種抵抗素子、各種コイル素子等の電子電気機能要素を接続するように形成されたアルミニウム（Ａｌ）等の配線電極膜を保護するために被覆される樹脂を主成分とした保護膜にレーザー光ビームのアブレーションにより、直接、開口部をパターン形成して良好な電極端子取り出し部を形成するように改良された半導体装置の製造方法に関する。
【０００２】
【従来の技術】
前記各種電子電気機能要素の形成された半導体装置基板の表面は、ポリイミド樹脂やエポキシ樹脂等の有機樹脂を主成分とする表面保護膜により覆われた後、電極端子取り出し部を形成するために、当該部に対応する金属電極膜上の表面保護膜を除去して開口部（電極露出部）を形成する必要がある。
従来、このような開口部の形成は前記表面保護膜にフォトリソグラフィ加工や印刷応用加工等のパターン形成技術を用いて行っている。さらにはレーザーアブレーション法によりポリイミド（保護）膜に直接開口部を形成することも知られている（下記特許文献１参照）。この開口部は外部と接続するためのＡｌ線をワイヤボンディングする必要があるので、樹脂膜除去後の開口部表面のＡｌ面に樹脂膜の残さ等があると、ボンディング強度に及ぼす悪影響が大きい。
【０００３】
ポリイミド樹脂を用いた表面保護膜の場合にフォトリソグラフィ加工により前記開口部を形成する場合、感光性のポリイミド樹脂を保護膜として用いる場合と、非感光性のポリイミド（保護）膜上にさらに感光性樹脂膜を被覆して開口する二つの方法がある。
前者では、ポリイミド（保護）膜にフォトマスクパターンを露光機で投影して、保護膜上に所定のパターンの潜像を形成し、アルカリ性現像液（ＴＭＡＨ：テトラメチルアンモニウムハイドロオキサイドの２．３８％）で現像エッチングして開口部を形成する。このような感光性ポリイミド樹脂にはネガ現像型、ポジ現像型の２種類がある。前者の有機溶剤可溶性のネガ現像型より、後者のアルカリ可溶性でポジ現像型である感光性樹脂（フォトレジスト）の方が利便性、パターン精度共に良好なので、実施例も多い。
【０００４】
後者では、非感光性ポリイミド（保護）膜上にポジ型フォトレジスト膜を被覆し、パターニングされたフォトレジスト膜をマスクにしてポリイミド（保護）膜をエッチングして開口部を形成する。この際、前記フォトレジストの現像液はポリイミド（保護）膜のエッチング液も兼ねるので、連続して処理可能である。
前記印刷応用加工では、スクリーン印刷機を用いて、パターニングされたＳＵＳメッシュあるいはＳＵＳ箔をマスクにして、エポキシ系樹脂保護膜やポリイミド系樹脂保護膜に所定のパターンを印刷した後、エッチングして保護膜の開口部を形成する。
【０００５】
前記レーザーアブレーション法によるポリイミド（保護）膜の直接開口技術は、高エネルギー密度のレーザー光をポリイミド（保護）膜の所定の開口部に直接照射し、照射部分を瞬間的に蒸発させて開口する方法である。レーザーアブレーション法はレーザービーム径が数十μｍ位以下と小さいので、それに見合った高精度が得られるという利点がある。しかも、開口すべきポリイミド（保護）膜の下側にあるＡｌ等のレーザー光に対する高反射率の金属電極膜が、レーザー光エネルギーによる発生熱の下部への伝達を阻止するので、半導体装置の機能低下や破損を確実に防止することができる点も優れている（特許文献１の０００３項〜０００７項、００３３項、特許文献３参照）。フェライト基板を用いた多層配線基板上のポリイミド（保護）膜のレーザーアブレーション法についても公知であり、さらにアブレーション後、開口部に残りやすいとされるすす（煤）等の残さについてもプラズマ処理により除去することも知られている（特許文献２参照）
【０００６】
【特許文献１】
特開２００２−１６４５９１号公報
【特許文献２】
特開２００２−２５２２５８号公報
【特許文献３】
特開２０００−１１７４６５号公報
【０００７】
【発明が解決しようとする課題】
しかしながら、前記いずれのパターン形成方法においても、次に述べるような問題がある。
感光性ポリイミド樹脂は感光性を良くするために、増感剤が多量に添加されているので、樹脂をキュアする際にガスが発生し易く、下地との密着性が不充分になり易いという問題がある。また、感光性ポリイミド樹脂自体が高価格という問題もある。
非感光性ポリイミド樹脂では、前記問題点等は少なくなる傾向にあるが、感光性樹脂に比べて、フォトレジストを追加して形成するので、工程が増えるという問題がある。
【０００８】
印刷応用加工法では、印刷マスクにより、比較的廉価な装置で簡単に所定部位に開口を形成した樹脂パターン膜を得ることができるので、低コスト化のためにはよい方法であるが、１００ミクロン以下の微細パターン形成の困難さ、気泡の巻き込み易さ、印刷終了直後の基板離れの悪さ、かすれパターンの発生し易さあるいは印刷時の圧力により破損し易い薄い基板（例えばシリコン基板の場合、厚さ２００μｍ以下）では使いにくいこと等の問題点がある。
また、レーザーアブレーション法の問題点はアブレーション後の開口面に残るすす（煤）等の残さの除去が必ずしも充分とは言えないことである。すす（煤）等の残さの除去が充分でないと、この開口面に超音波ボンディング等により接続されたＡｌワイヤあるいはバンプメッキ等の剥離が起き易くなるという致命的な欠陥に至りやすい。
【０００９】
本発明は、以上述べた問題点に鑑みてなされたものであり、従来のフォトリソグラフィよりも工程を簡略できて安価であり、薄い基板を用いた半導体装置でも割れ等の破損不良を少なくでき、レーザーアブレーション後の開口面に残る残さをいっそう良好に除去でき、この開口面に結合されるＡｌワイヤあるいはバンプメッキ等の外部取り出し電極端子の剥離の発生を少なくする半導体装置の製造方法の提供を目的とする。
【００１０】
【課題を解決するための手段】
請求項１記載の発明によれば、前記目的は、電子または電気機能要素と、該機能要素を接続する金属配線電極膜とを備える基板上に、樹脂を主成分とする表面保護膜を形成した後、レーザーアブレーションにより前記金属配線電極膜上の前記表面保護膜に開口部を形成してなる半導体装置の製造方法において、前記開口部に対応するパターンマスクを介して、減圧雰囲気下でのレーザーアブレーションにより前記開口部を形成した後、前記開口面にプラズマ灰化処理を含むクリーニング処理を施す半導体装置の製造方法とすることにより、達成される。
【００１１】
請求項２記載の発明によれば、基板が半導体基板またはフェライト基板である請求項１記載の半導体装置の製造方法とすることが好ましい。
請求項３記載の発明によれば、半導体基板の厚さが２００μｍ以下であることを特徴とする請求項２記載の半導体装置の製造方法とすることが好ましい。
請求項４記載の発明によれば、クリーニング処理が受光面で０．２Ｊ／ｃｍ２未満のレーザーエネルギー密度のレーザー光ビームによる照射、酸素系プラズマ処理と水素系プラズマ処理を含むプラズマ灰化処理およびアルゴンスパッタリング処理を含む請求項１乃至３のいずれか一項に記載の半導体装置の製造方法とすることも好ましい。
【００１２】
請求項５記載の発明によれば、表面保護膜がポリイミド樹脂またはエポキシ樹脂である請求項１乃至４のいずれか一項に記載の半導体装置の製造方法とすることが望ましい。
請求項６記載の発明によれば、減圧雰囲気が１．３３乃至０．１３３Ｐａ（１０―２乃至１０―３ｔｏｒｒ）の範囲内のいずれかの値である請求項１乃至５のいずれか一項に記載の半導体装置の製造方法とすることも望ましい。
請求項７記載の発明によれば、レーザーアブレーションのレーザー光ビームのレーザーエネルギー密度が受光面で０．２乃至１．０Ｊ／ｃｍ２の範囲のいずれかである請求項１乃至６のいずれか一項に記載の半導体装置の製造方法とすることが好適である。
【００１３】
【発明の実施の形態】
以下、本発明の半導体装置の製造方法に関し、図を用いて詳細に説明する。本発明はその要旨を超えない限り、以下に説明する実施例に限定されるものではない。
図１は本発明にかかる半導体装置の製造方法をＩＣで示すＩＣ基板のプロセス断面図、
図２は本発明にかかる半導体装置の製造方法をＩＧＢＴで示すＩＧＢＴ基板のプロセス断面図、
図３は本発明にかかる半導体装置の製造方法を複合ＩＣで示す複合ＩＣ基板のプロセス断面図、
図４は本発明に使用されるレーザービーム加工装置の概略図、
図５は図４の装置に用いられるレーザー光のエネルギー密度とレーザーショット（パルス）数との関係図、
図６はＥＳＣＡ解析によるレーザー光エネルギー密度と開口面の炭素原子濃度の関係図、
図７は本発明にかかる効果を示すレーザー光エネルギー密度と開口面の炭素原子濃度の関係図、
図８は本発明にかかるＡｌワイヤ剥離率とＡｌワイヤのボンディング用超音波出力との関係図、
図９は本発明にかかる半導体装置の実験ユニットＡの上面図、
図１０は超音波ボンディングしたＡｌワイヤの剥離強度を調べる実験ユニットＢの断面図である。
【００１４】
ここで、本発明にかかるレーザーアブレーションについて、簡単に説明しておく。レーザーアブレーション（ｌａｓｅｒ ａｂｕｌａｔｉｏｎ）とはレーザー光を固体に照射した場合、レーザー光の照射強度がしきい値以上になると、固体表面で電子的、熱的、光化学的および力学（機械）的エネルギーに変換され、その結果、中性原子、分子、正負イオンラジカル、クラスタ、電子、光（光子）が爆発的に放出され、固体表面がエッチングされるプロセス技術である。
レーザーアブレーションによる樹脂膜のパターン加工は、高エネルギー密度を有し、スポット径が数十μｍ以下の紫外線領域のレーザー光を用い、所定のパターンを有する開口部のみに照射露光して、瞬間的に高精度にエッチング加工するので、照射部以外にはほとんど熱が及ばないという特長がある。この際、レーザー光としては光分解反応が主であり、熱の影響の少ないエキシマレーザーが好ましい。エキシマレーザーにはＡｒＦ波長１９２ｎｍ、ＫｒＦ波長２４８ｎｍ、ＸｅＣｌ波長３０８ｎｍがあり、いずれのレーザー光でも本発明に用いることができる。本発明ではＫｒＦ波長２４８ｎｍを用いた。
【００１５】
図４に本発明にかかるレーザーアブレーションのために使用したレーザーアブレーション装置４００を示す。レーザー発振器４０１として、ＫｒＦ波長２４８ｎｍのエキシマレーザーを用い、バリュアブルアッテネータ４０２、ビームエクスパンダ４０３、ビームホモジナイザ４０４等のビーム伝送光学系を経て、マスク４０５として３倍の拡大パターンを有するＳＵＳメタルマスクを使用した。
このＳＵＳメタルマスク４０５と下地パターンとを高精度にパターン合わせをする必要のある時はダイクロイックミラー４０６でスプリットフィールドされた視界をＣＣＤカメラ４０８で、ＸＹＺθステージ４１２をステージコントローラ４１３により微移動させて加工すべき基板４１１上のパターンを、転写レンズ４０９により実寸に縮尺投影されたマスク４０５のパターンにモニタ４０７により合わせ、一パターンづつ順に表面保護膜４１０を開口する。一パターン内の表面保護膜をレーザー光スポットがすべて走査するようにＸＹＺθステージ４１２が微移動する。このＸＹＺθステージ４１２はステージコントローラ４１３によりＸＹＺθ方向の自由な微移動ができるように制御される。
【００１６】
本発明ではレーザーアブレーションを減圧環境下で行う必要があるため、転写レンズ４０９と加工すべき基板４１１とＸＹＺθステージ４１２とのグループが減圧室４１４に置かれている。このレーザーアブレーション加工装置で用いられるレーザー光ビームの加工面におけるスポットの大きさはおおよそ１２μｍ×２５μｍの楕円形である。
加工する樹脂膜としては、エポキシ樹脂、ポリイミド樹脂、シリコーン系樹脂、フッ素系樹脂、アクリル系樹脂、ポリカーボネート樹脂等を用いることができるが、レーザー光の波長に対する吸収効率がよく、加工精度が高く、保護膜としての強靭性、熱膨張係数、耐熱性、絶縁性、耐溶剤性等の観点から、ポリイミド樹脂、エポキシ樹脂が特に好ましい。
【００１７】
本発明にかかるレーザーアブレーションでは、加工される部位の前記樹脂膜が金属配線電極膜上に形成される必要がある。このような構成とした場合、たとえレーザーエネルギーが樹脂膜にすべて吸収されずに金属配線電極膜に達したとしても、前述のような条件下では前記電極膜によりほとんど反射されるかまたは吸収されるので、特にシリコン半導体基板では電極膜下の酸化膜や機能領域の劣化を防止できる。
このような電極膜としては、前記レーザー光に対する高反射率を有するＡｌ電極膜が好ましいが、Ｎｉ膜やその他の合金膜であってもよい。
【００１８】
以下、本発明にかかる半導体装置の製造方法について、レーザーアブレーションの適切な条件および開口後のクリーニング条件について行った実験例を示す。
（実験例）
従来のレーザーアブレーションでは、アブレーション後の開口部に残る煤状の残さの除去が充分とはいえない場合があったので、残さの除去が充分にできるアブレーション方法を見つけ出すことを目的として、アブレーション条件によって煤状の残さの程度がどのように変わるか、およびＡｌワイヤの接合強度との関係を見るためにＡｌワイヤの引っ張り試験を行なった。。
【００１９】
図９に示す実験ユニットＡは開口部にＡｌワイヤを接続する前の半導体基板の上面図であり、アブレーション後の前記開口部の表面状態を調べるためのユニットサンプルである。図１０に示す実験ユニットＢは銅基板にＮｉ―Ａｌ膜とその上にポリイミド膜を形成し、開口部の形成後、Ａｌワイヤをボンディング接続した状態の断面図であり、前記開口部にボンディング接続されたＡｌワイヤの剥離試験を行うためのユニットサンプルである。これらの各実験ユニットの作成方法を以下に示す。前記実験ユニットＡでは表面保護膜として、ポリイミド樹脂膜を用いたが、エポキシ樹脂を用いても、ほぼ同様の結果が得られる。
【００２０】
実験ユニットＡ（図９）−厚さ５５０μｍのＳｉ基板（ベア）９０１上にＡｌ／Ｓｉ膜を厚さ５μｍにスパッタリングにより被覆し、この上にポリイミド膜９０３を１０μｍの厚さに塗布する。前記ポリイミド膜９０３に図４のアブレーション加工装置を用いて、図９に示す所定のパターンで開口部（ワイヤボンディング部）９０４を形成した。このパターン加工で用いるためのマスクとして、一辺７ｍｍ角のユニット基板表面に５×２ｍｍの矩形状のポリイミド膜除去部９０４を２箇所形成するためのパターンが３倍拡大されたＳＵＳマスクを使用した。前記実験ユニットＡでは開口面の清浄度を見るための物なので、厚い基板を用いたが、薄い基板を用いてもよい。
【００２１】
実験ユニットＢ（図１０）−銅板にＮｉメッキ後Ａｌ―Ｓｉ（１％）をスパッタリング被着（１００２）した基板１００１として、その上にエポキシ系接着剤によりポリイミド膜１００３を接着して載置し、前記の各パターニング方法により開口部１００４を形成した後、径３００μｍのＡｌワイヤ１００５を超音波ボンダー（図示せず）によりボンディングした。Ａｌワイヤ１００５は一箇所の開口部（ボンディング部）１００４につき５本ボンディングし、引っ張り試験を行えるように他端を直接基板上にボンディングした。前記超音波ボンディングの条件は、周波数１１０ＫＨｚ、荷重６００グラム、ボンディング時間１５０ｍｓｅｃ、振幅１〜３ｍｍの条件とした。
【００２２】
まず、前記レーザーアブレーション加工装置により、ある基準寸法を有する直接ポリイミド膜の開口部を形成する際に必要な全レーザーエネルギーに対するレーザーエネルギー密度とレーザーショット（パルス）数との関係を調べた。その関係を図５に示す。図５からレーザーエネルギー密度が高い場合はショット（パルス）数は少なく、低い場合はショット（パルス）が多いことがわかる。ただし、図５の横軸に示すレーザーエネルギー密度を１．０Ｊ／ｃｍ２より高くしすぎると開口面のＡｌ電極や場合によってはその下層の酸化膜等に悪影響を及ぼすことがあるので、好ましくない。また０．１Ｊ／ｃｍ２より低いとショット（パルス）数を増やしても開口が充分に行えなくなることがわかった。以降の説明において、レーザーエネルギー密度の値はすべて受光面において測定された値である。
【００２３】
この条件下で、図６に示すレーザーエネルギー密度と開口面の炭素原子濃度（ａｔｍ％）との関係をＥＳＣＡ分析により求めた。図６のプロット線６０１は、縦軸に示すレーザーアブレーション直後（クリーニング無し）の開口面の炭素原子濃度と、横軸に示すレーザーアブレーション時のレーザーエネルギー密度との関係を示す。同様にプロット線６０２は前記同条件のレーザーアブレーション後に市販のフォトレジスト剥離液（東京応化（株）の５０２Ａ）を用いてウェット処理により開口面をクリーニングした後の開口面の炭素原子濃度とレーザーエネルギー密度との関係を示す。
【００２４】
図６において、０．１Ｊ／ｃｍ２を縦軸方向に見ると、レーザーアブレーション加工直後の開口面（Ａｌ−Ｓｉ電極面）は、約９０ａｔｍ％（原子％）の炭素が存在することを示すが（プロット線６０１）、前記アブレーション加工後にウェットクリーニングを追加した場合には炭素原子濃度が約６０ａｔｍ％に減少する（プロット線６０２）ことから、一応前記ウェットクリーニング追加が有効なことがわかる。
しかし、高倍率のＳＥＭにより前記開口面を観察すると、いずれも炭素が微小島状の薄膜状態または粒子状態で点在することが判明した。レーザーエネルギー密度をさらに順次大きくした場合（０．２Ｊ／ｃｍ２、０．４Ｊ／ｃｍ２、０．６Ｊ／ｃｍ２、０．８Ｊ／ｃｍ２、１．０Ｊ／ｃｍ２）における開口面の炭素原子濃度について、０．１Ｊ／ｃｍ２から０．２Ｊ／ｃｍ２へエネルギー密度を上げた場合は炭素原子濃度にそれぞれ変化（減少）が認められるが、ウェットクリーニング後でも、炭素原子濃度は約６０ａｔｍ％からせいぜい約４０ａｔｍ％に減少する程度にすぎない。さらにそれ以上レーザーのエネルギー密度を高くしても開口面の炭層濃度の減少にはあまり影響しないことがわかる。
【００２５】
前記約４０ａｔｍ％程度の炭素原子濃度レベルは、純水に対する濡れ角度が１００度と大きく、Ａｌワイヤの剥離問題を解決するにはまだ不充分であった。すなわち、ウェットクリーニングの追加だけでも炭素原子濃度の減少には一応有効ではあるが、前記剥離問題の解決に対しては限界のあることがわかった。
一方、レーザーアブレーション加工によらないフォトリソグラフィのみによるパターン加工後の開口面の炭素原子濃度は、約２０ａｔｍ％以下の低レベルであり、純水に対する濡れ角度は１０〜２０度と小さく、Ａｌワイヤの剥離についても問題のないこともわかっている（図示せず）。ただし、フォトリソグラフィ加工は高コストという問題がある。レーザーアブレーション加工の場合にも前記Ａｌワイヤの剥離問題を解決するには、レーザーアブレーション加工後の開口面の炭素原子濃度を前記フォトリソグラフィ加工の場合の約２０ａｔｍ％と同レベルにする必要があると思われた。
【００２６】
前述のように炭素原子濃度を約２０ａｔｍ％と同レベルにするために種々の開口部クリーニングの実験を繰り返した結果、レーザーアブレーション加工時に一旦ポリイミド樹脂膜の分解された粒子が吹き飛ばされた後、再付着する煤状の残さが多いことが判明した。この煤状残さが多いと従来のプラズマ処理だけでは充分に除去しきれないことがわかり、プラズマ処理前の段階で煤状残さをできる限り少なくしておくことが重要と考えた。下記に示すように公知のプラズマクリーニング処理を改良した開口部クリーニング方法がレーザーアブレーション後の開口部に残る煤等の残さ除去にきわめて有効であることがわかり、本発明にかかる半導体装置の製造方法に至った。
【００２７】
以下、本発明にかかる半導体装置の製造方法にかかるレーザーアブレーション加工と、その後の、開口部のクリーニング処理を具体的に説明する。
前記図９に示す半導体装置の実験ユニットＡを用い、そのポリイミド保護膜に前記レーザーアブレーション加工を１ｔｏｒｒ＝１３３．３Ｐａ（１０−２〜１０−３ｔｏｒｒ）の減圧下でレーザーエネルギー密度０．１Ｊ／ｃｍ２、０．４Ｊ／ｃｍ２、１．０Ｊ／ｃｍ２でそれぞれ行って開口した後、０．１Ｊ／ｃｍ２の弱いレーザーアブレーション加工を一パターンに対して３回繰り返し行い、その後プラズマ処理を施した。
【００２８】
このように減圧下でのレーザーアブレーション開口処理を行うことが重要であり、必要に応じてさらに、その後に弱いレーザーアブレーションを加えることにより、プラズマ処理の前に前記開口部における残さを少なくしておくことは極めて重要である。減圧条件については、前述の範囲で充分であり、それ以上の減圧にしても、装置が高価になるだけで、効果はそれほど大きくはならない。その後のプラズマ処理の条件を以下に示す。
平行平板型プラズマ装置
周波数 １３．５６ＭＨＺ−最大バイアス出力１０００ワットの装置
処理出力 ５００ワット
雰囲気 Ｏ２：Ｎ２＝４：１（Ｏ２１００ｍｌ／分＋Ｎ２２５ｍｌ／分）
ガス圧 ２０Ｐａ
電極温度 ８０〜８５℃
処理時間 １２０秒
の条件で酸素系プラズマ処理を行い、続いて、同装置で下記のように還元系雰囲気に条件を変えて、処理を加えた。
処理出力 ７５０ワット
雰囲気 Ｈ２：Ｎ２＝４：１（Ｈ２１００ｍｌ／分＋Ｎ２２５ｍｌ／分）
ガス圧 ２０Ｐａ
電極温度 ８０℃
処理時間 ２４０秒
Ａｒ（アルゴン）スパッタリングによるクリーニング
周波数 １３．５６ＭＨＺ
処理出力 ４００ワット
Ａｒ １０ｍｌ／分
ガス圧 １０Ｐａ
処理時間 ３０秒
以上の条件で作製した実験ユニットＡについて、レーザーアブレーション加工直後の場合と、さらに本発明にかかる前記クリーニング処理を追加した場合とのそれぞれについて、開口部の炭素原子濃度をＥＳＣＡ分析により調べた。その結果を図７に示す。
【００２９】
図７のプロット線７０１はレーザーアブレーション加工直後の炭素原子濃度を示し、プロット線７０２は前記レーザーアブレーション加工後、さらに本発明にかかる前記プラズマ装置によるクリーニング処理をした後の炭素原子濃度を示す。前記プロット線７０２はクリーニング処理前のプロット線７０１と比べると開口面に存在する炭素原子濃度が極めて減少していることがわかる。前記図６のプロット線６０２と比較してもさらに炭素原子濃度レベルが低いことがわかる。プロット線７０２の炭素原子濃度レベルはレーザーアブレーションによらない従来のフォトリソグラフィ処理のみの炭素原子濃度レベルに近いか、または、ほぼ同等のレベルであることがわかる。
【００３０】
また、前記図１０に示す実験ユニットＢを用いて、従来のフォトリソグラフィ加工による開口部の形成をしたユニットサンプルと、レーザーエネルギー密度０．２Ｊ／ｃｍ２と、１．０Ｊ／ｃｍ２の各レーザーアブレーション加工＋本発明にかかる前記クリーニング処理により開口部（ワイヤボンディング部）を形成したユニットサンプルをそれぞれ作成し、それぞれ開口部に５本づつＡｌワイヤボンディングをし、他端を直接基板上にボンディングして一本づつ切断するまで引っ張り、切断個所を調べることにより剥離強度を調べた。その結果を図８に示す。
【００３１】
図８は横軸にＡｌワイヤのボンディング時の超音波出力を最大出力１００％に対する出力比率％で示す。縦軸は前記引っ張り試験方法によりワイヤを引っ張ったときのＡｌワイヤの接合界面からの剥離率を示す。Ａｌワイヤの剥離率は図１０におけるＡｌワイヤ１００５が開口面１００４の電極膜１００２との接合界面１００６から剥離したものの割合をいう。Ａｌワイヤ１００５がネック部１００７やワイヤの途中１００８で切断したものは良品とする。
図８のプロット線８０１はフォトリソグラフィのみで開口部を形成した実験ユニットＢの場合の引っ張り試験結果を示し、Ａｌワイヤの超音波ボンディング出力が７０％以上で、剥離率が０％、言い換えれば、すべてＡｌワイヤの接合界面ではなくワイヤの途中で切断することを表している。
【００３２】
本発明にかかるプロット線８０２と８０３は、前記図７においてプロット線７０２で示したように、レーザーアブレーションをそれぞれ０．４Ｊ／ｃｍ２と１．０Ｊ／ｃｍ２のレーザー光エネルギー密度で開口を行い、開口面のクリーニング処理として、０．１Ｊ／ｃｍ２の弱いレーザーアブレーションを３回行った後、前記プラズマ処理と同条件の酸素系プラズマ処理と還元系プラズマ処理をそれぞれ行った実験ユニットＢの場合の引っ張り試験結果を示す。
前記プロット線８０２と８０３では剥離率を０％にするのに超音波出力をそれぞれ７５％、８０％にすればよいことを示している。この超音波出力はプロット線８０１で示すようになるべく低い出力でＡｌワイヤの剥離率が０％となることが好ましく、プロット線８０１の場合の出力７０％が開口面の清浄度を見る一つの目安となる。
【００３３】
例えば前記図６に関して説明したプロット線６０２で示される４０〜６０ａｔｍ％の清浄度を持った開口面では、図示しないが前記超音波出力を１００％にしても前記剥離率は３０％以上となり、剥離問題を解決できないことがわかっている。さらに超音波出力が９０％を超えるとＡｌ電極面やＡｌの下の絶縁膜にクラックが入る等の悪影響が特に顕著になり、耐圧劣化に繋がるので、好ましくない。
前記０．１Ｊ／ｃｍ２の弱いレーザーアブレーションの繰り返し回数は１〜３までは煤等の残さの除去度は上がったが、４回以上ではあまり除去度は上昇しないこともわかった。この弱いレーザーアブレーションが除去する対象の煤は前記開口時に残った残さというよりも、開口時に高熱により吹き飛ばされて舞い上がった煤が開口面に再付着したものと思われる。意外にも、この弱いレーザーアブレーションが開口部の煤の除去に大きな効果があることがわかった。
【００３４】
この後に行われるプラズマ処理によるクリーニングだけでは十分に除去できない場合でも、この弱いレーザーアブレーションと組み合わせると煤の除去効果が大きくなる。この弱いレーザーアブレーションは、繰り返して照射しても開口面に及ぼす悪影響の少ない０．２Ｊ／ｃｍ２以下のレーザーエネルギー密度が好ましく、０．０１Ｊ／ｃｍ２以下では除去効果が小さくなるので、０．０５〜０．２Ｊ／ｃｍ２が最適であることがわかった。
本発明にかかるレーザーアブレーション加工とその後のプラズマクリーニング処理によれば、従来のフォトリソグラフィのみによる加工よりも工程を簡略にすることができて安価でありながら、開口面の煤等の残さが従来のフォトリソグラフィのみによる加工と同程度に少ない製造方法とすることができることがわかる。
【００３５】
前記Ａｒスパッタリングについては、必要に応じて省略することもできる。前述のクリーニング処理では一回おこなっただけであるが、繰り返し行ってもよい。
前記実験ユニットではなく、実際のシリコン半導体基板やフェライト基板の場合は、同一基板内に開口すべきパターンの数が非常に多いので、このような場合は、先に全パターンを開口した後に、前述の弱いレーザーアブレーションを含むクリーニング処理が行われる。
以下、前記実験結果から得られたレーザーアブレーション条件とその後のクリーニング条件を用いて作製した半導体装置の製造方法の実施例について、具体的に図を用いて説明する。
【００３６】
（実施例１）
図１は一般的なＭＯＳ型半導体装置１００を有するＩＣの製造方法を示すプロセス断面図である。ｐ型、比抵抗１０〜１５Ωｃｍで６２５μｍ厚の６インチ半導体基板１０１の一方の面に公知のプロセスにより、８０００オングストローム膜厚のＬＯＣＯＳ絶縁分離膜１０２を形成し、１μｍのゲート長１０５となるように、２５０オングストローム厚のゲート酸化膜１０４を形成し、続いてポリシリコンゲート電極１０３を０．３μｍ厚程度形成し、フォトリソグラフィにより、所定パターンのポリシリコンゲート電極およびゲート膜に加工する。コンタクト層としてｎ＋層１０６を、表面濃度１．０×１０１９ｃｍ−３で、０．２μｍ深さに形成する。
【００３７】
この時、前記ポリシリコン電極にも同時に３１ｐ＋イオンを注入して１０〜２０Ωｃｍの比抵抗に調整することによりゲート電極としての機能を有効にする。次に、層間絶縁膜として酸化膜１０７を形成する。この酸化膜１０７は高温熱酸化膜（ＨＴＯ）１２００オングストロームとＢＰＳＧ（Ｂｏｒｏ Ｐｈｏｓｐｈｏ
Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）の６０００〜８０００オングストロームからなる。この酸化膜１０７にフォトリソグラフィによりコンタクト部位（１０９、１１０、１１１）を開口して、ポリシリコン電極に接するＡｌ電極１０８を形成する。Ａｌ電極１０８はＡｌ：Ｓｉ：Ｃｕ＝９８．９％：１％：０．１％組成の合金からなり、厚みを１μｍとなるように形成した（図１（ａ））。
【００３８】
図１（ｂ）の断面図に示すように、表面保護膜１１２としてポリイミド膜を１０μｍ厚程度に形成する。続いて、図１（ｃ）に示すように、ポリイミド膜１１２の各部位（ソース、ゲート、ドレイン電極の各パッド部位）１１３、１１４、１１５を前述の本発明にかかるレーザーアブレーションにより、Ａｌ電極１０８が露出するように全パターンについて順次開口する。
前記レーザーアブレーションの条件を次に示す。図４のアブレーション装置を用い、ＫｒＦ波長２４８ｎｍのエキシマレーザーをポリイミド膜の開口面で１．０Ｊ／ｃｍ２のレーザーエネルギー密度となるように照射した。全パターンの開口後、直ちに０．１Ｊ／ｃｍ２の弱いレーザーエネルギー密度のレーザーアブレーション照射を３回行い、その後プラズマ処理による開口部のクリーニングを行った。
【００３９】
プラズマ処理条件は図９に示す実験ユニットＡにおけるプラズマ処理条件（Ａｒスパッタリングを含む）と同じにした。実施例１では、ポリイミド保護膜へのボンデイングパッド用開口部の形成に対してレーザーアブレーションを用いて行なったので、Ａｌボンデイングワイヤの剥離問題を解決でき、また工程を簡略化でき、安価になった。
（実施例２）
図２はＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）素子基板２００の製造方法を示すプロセス断面図である。このＩＧＢＴ素子基板は裏面からドレイン側ｐ＋層２０８、ｎ＋バッファ層２１２、エピタキシャル成長により形成されたｎ−伝導度変調層２０１、このｎ−層２０１の表面に形成されたｐウェル層２０６、前記ｎ−層２０１の表面にゲート酸化膜２０３を介して形成されたポリシリコンからなるゲート電極２０４を備え、前記ｐウェル層（エミッタ）２０６内には浅いｎ＋ソース領域２０７が形成され、前記ゲート酸化膜２０３下でｎ＋ソース領域２０７とｎ−層２０１とに挟まれたｐウェル層２０６の表面にチャネル領域２０９を形成する。前記エミッタ２０６とｎ＋ソース領域２０７とに跨ってエミッタ電極２０５−１、ドレイン側ｐ＋層２０８にはドレイン電極層２０５−２、ポリシリコンゲート電極２０４上にはゲート電極２０５−３がそれぞれＡｌ膜により形成される。
【００４０】
定格電圧と定格電流がそれぞれ６００ボルト、１００〜２００アンペアのＩＧＢＴのシリコン基板は、０．０２Ωｃｍのドレイン側ｐ＋層２０８に０．１Ωｃｍのｎ＋バッファ層２１２を１０μｍ深さに形成し、ドレインｐ＋層２０８を３０μｍにしたシリコン基板に、４０Ωｃｍのｎ−層２０１を７０μｍ厚にエピタキシャル成長したもの（全１１０μｍ）を用いる。
このシリコン基板に厚い初期酸化膜２０２を形成し、この酸化膜２０２にｐウェル層２０６形成のために所定のパターンで窓明けを行い、ボロンイオンをイオン注入し、ドープ、ドライブを経てｐウェル層２０６を形成する。ゲート用酸化膜２０３を８００〜１０００オングストローム厚に形成後、このゲート用酸化膜２０３上にポリシリコン膜を５０００オングストローム厚に形成する。
【００４１】
これらの膜を図２（ａ）に示すようにフォトリソグラフィによりパターンエッチングしてゲート酸化膜２０３、ポリシリコンゲート電極２０４とする。形成したゲート酸化膜２０３とポリシリコンゲート電極２０４とをマスクにして、ボロンイオンをイオン注入し、加熱してボロン濃度１×１０１４ｃｍ−３のｐウェル層２０６を３〜４μｍの深さに形成する。続いて、フォトレジスト膜をマスクとしてｎ＋ソース領域２０７をリン濃度５×１０１５ｃｍ−３で１μｍ深さに形成する。
層間絶縁膜として形成した酸化膜２０２をフォトリソグラフィでパターンエッチングし、Ａｌ電極２０５−１（Ａｌ−Ｓｉ（１％））を５μｍの厚さにスパッタで形成し、フォトリソグラフィで所定のパターンに形成する（図２（ａ））。図２（ｂ）に示すように、ポリイミド樹脂を表面保護膜２１０として１０μｍの厚さに被覆する。
【００４２】
その後、図２（ｃ）に示すように、Ａｌ電極膜２０５上の電極端子取り出し部となる電極パッド部２１１上のポリイミド樹脂膜を本発明にかかる前記レーザーアブレーションにより、全パターンについて順次開口する。レーザーアブレーション条件およびその後の開口面のクリーニング処理については前記実施例１と同じとした。
実施例２では１１０μｍの薄いシリコン基板を用いたが、本発明ではポリイミド保護膜へのボンデイングパッド用開口部の形成に対してレーザーアブレーションを用いたので、Ａｌボンデイングワイヤの剥離問題を解決でき、また、非接触で行なったので、シリコン基板の割れの発生が少なく、また、フォトリソグラフィ加工に比べて工程が簡略化され、安価に作製できた。一般的に２００μｍ以下、特に１５０μｍ以下の厚さのシリコン半導体基板を用いると、基板の割れが「発生しやすくなるが、本発明によれば、基板の割れの発生を少なくできる。
【００４３】
（実施例３）
図３（ａ）は複合ＩＣ３００の断面図である。この複合ＩＣは特定用途向けの専用ＩＣチップ（ＩＣ基板）３０１とインダクタ機能を有する薄膜インダクタ３２０とを積層させたものを回路基板３１０上の所定の電極パッド３１８上に接合メタル３１７を介して載置した構成を有する。
図３（ｄ）は前記図３（ａ）の複合ＩＣの電気回路を示し、点線の枠内で示す前記特定用途向けの専用ＩＣチップ３０１と前記薄膜インダクタ３２０とが図示のように接続されていることを示す。図３（ｂ）、図３（ｃ）はそれぞれ前記薄膜インダクタ３２０の上面図、下面図を示す。前記薄膜インダクタ３２０はフェライト基板３０５に形成されたスルーホール３１３を介して基板の両面を使って金属配線３０６、３０７をコイル状にしてインダクタ機能を保有させている。
【００４４】
フェライト基板３０５は、必要な透磁率となるようにＭｎ−Ｚｎ、Ｃｕ−ＺｎあるいはＮｉ−Ｚｎ等の粉末を適正な成分組成で混合し、所定の形状に成形して、１１００℃〜１２００℃の高温で焼結させることにより作られている。このようにして得られた厚さ約５００μｍのＭｎ−Ｚｎ−Ｃｕ−Ｎｉ系フェライト基板３０５の透磁率は１０００程度であった。
このフェライト基板３０５に、直径０．２ｍｍφのスルーホール３１３を図３（ｂ）、（ｃ）に示す配置で、メタルあるいは樹脂等をマスクとして、サンドブラスト、レーザー光、イオンビーム、高圧ジェット水などにより形成し、このスルーホールを介して両面に跨る金属配線３０６、３０７を形成してインダクタを構成した。スルーホール内の導通は両面にＴｉ（０．１μｍ）／Ｃｕ（０．２μｍ）をスパッタリングし、続いて無電解Ｃｕメッキを０．２〜０．４μｍ厚に付けることにより、前記スルーホール３１３内を金属メッキ膜で被覆することにより形成した。
【００４５】
インダクタのコイル部分の形成は図３（ｂ）の上部コイル配線３０６、図３（ｃ）の下部コイル配線３０７、上下接続電極３０９に相当する各部位が露出するように、ドライフィルムで所定パターンを露出、現像して形成した後、ドライフィルムをマスクに電解銅メッキを４０μｍ、Ｎｉメッキ５μｍ、Ａｕメッキ１μｍのように積層して、コイル部分の前記金属配線３０６、３０７を形成した。その後、ポリイミド膜などからなる表面保護膜３０８を５０〜６０μｍの厚さに塗布し、熱処理によりポリイミド膜を乾燥させた後、本発明にかかるレーザーアブレーションにより上下接続電極３０９の開口部３１６を開口する。レーザーアブレーション条件およびその後の開口面のクリーニング処理については前述の実施例１と同じにした。
【００４６】
一方、ＩＣチップ３０１についても、前記実施例１で説明したように、本発明にかかるレーザーアブレーション処理が施され、Ａｌ電極パッド部３０３が開口される。ＩＣチップ３０１と薄膜インダクタ３２０とは前記電極パッド３０３、３１６とで接合メタル３１７を介して接合される。
接合メタル３１７はＩＣチップのＡｌ電極パッド３０３にＺｎ活性化処理を施した後、無電解Ｎｉメッキ２０〜３０μｍ、０．０５μｍ厚のＡｕバンプ電極あるいはＡｕワイヤボンディングによるスタッドバンプまたはＴｉ／Ｃｕシード層（ｓｅｅｄ ｌａｙｅｒ）のスパッタリングによるＮｉ厚さ５μｍなどとハンダ３０〜５０μｍ電解メッキ法のバンプ等により、凸型バンプ電極を形成する。フェライト基板３０５の裏面側（図３（ｃ））には回路基板３１０上の電極パッド３１８に予めはんだクリームをスクリーン印刷により、５０〜６０μｍ厚に形成しておき、はんだリフロー法により接続する。実施例３ではポリイミド保護膜のバンプ電極用パッドの開口形成を本発明にかかるレーザーアブレーションにより行なったので、従来のスクリーン印刷等による開口よりも高精度にできると共に、コスト的にも同程度の安価にすることができた。
【００４７】
【発明の効果】
本発明によれば、電子または電気機能要素と、該機能要素を接続する金属配線電極膜とを備える基板上に、樹脂を主成分とする表面保護膜を形成した後、レーザーアブレーションにより前記金属配線電極膜上の前記表面保護膜に開口部を形成してなる半導体装置の製造方法において、前記開口部に対応するパターンマスクを介して、減圧雰囲気下でのレーザーアブレーションにより前記開口部を形成した後、前記開口面にプラズマ灰化処理を含むクリーニング処理を施す半導体装置の製造方法としたので、フォトリソグラフィよりも工程が簡略で安価であり、薄い基板を用いた半導体装置でも割れ等の破損不良を少なくでき、レーザーアブレーション後の開口面に残る残さをいっそう良好に除去でき、この開口面に結合されるＡｌワイヤあるいはバンプメッキ等よりなる外部取り出し電極端子の剥離の発生を少なくする半導体装置の製造方法を提供できる。
【図面の簡単な説明】
【図１】本発明にかかる半導体装置の製造方法をＩＣで示すＩＣ基板のプロセス断面図
【図２】本発明にかかる半導体装置の製造方法をＩＧＢＴで示すＩＧＢＴ基板のプロセス断面図
【図３】本発明にかかる半導体装置の製造方法を複合ＩＣで示す複合ＩＣ基板のプロセス断面図
【図４】本発明に使用されるレーザーアブレーション加工装置の概略図
【図５】図４の装置に用いられるレーザー光のエネルギー密度とレーザーショット（パルス）数との関係図
【図６】本発明にかかるレーザー光エネルギー密度と開口面の炭素原子濃度の関係図
【図７】本発明にかかるレーザー光エネルギー密度と開口面の炭素原子濃度の関係図
【図８】本発明にかかるＡｌワイヤ剥離率とＡｌワイヤのボンディング用超音波出力との関係図
【図９】本発明にかかる半導体装置の実験ユニットＡの上面図
【図１０】Ａｌワイヤの剥離強度を調べる実験ユニットＢの断面図
【符号の説明】
１００ ＭＯＳ型半導体装置
１０８ Ａｌ電極
１１２ 表面保護膜
１１３ ソース電極パッド（開口部）
１１４ ゲート電極パッド（開口部）
１１５ ドレイン電極パッド（開口部）
２００ ＩＧＢＴ半導体装置
２０５−１ エミッタＡｌ電極
２０５−２ ドレインＡｌ電極
２０５−３ ゲートＡｌ電極
２１０ 表面保護膜
２１１ 電極パッド（開口部）
３００ 複合ＩＣ装置
３０３ ＩＣチップの電極パッド（開口部）
３０８ 表面保護膜
３１６ フェライト基板の電極パッド（開口部）
４００ レーザーアブレーション装置。[0001]
TECHNICAL FIELD OF THE INVENTION
INDUSTRIAL APPLICABILITY The present invention protects a wiring electrode film made of aluminum (Al) or the like formed to connect electronic and electric functional elements such as various semiconductor elements, various resistance elements, and various coil elements formed on a semiconductor substrate or a multilayer wiring board. Method for manufacturing a semiconductor device in which an opening is directly patterned by ablation of a laser beam on a protective film mainly composed of a resin to be coated to form a good electrode terminal extraction portion. About.
[0002]
[Prior art]
After the surface of the semiconductor device substrate on which the various electronic and electrical functional elements are formed is covered with a surface protective film containing an organic resin such as a polyimide resin or an epoxy resin as a main component, in order to form an electrode terminal extraction portion, It is necessary to form an opening (electrode exposed portion) by removing the surface protective film on the metal electrode film corresponding to the portion.
Conventionally, such openings are formed on the surface protective film by using a pattern forming technique such as photolithography or printing. Furthermore, it is also known to form an opening directly in a polyimide (protection) film by a laser ablation method (see Patent Document 1 below). Since the opening needs to be wire-bonded with an Al wire for connection to the outside, a residue of the resin film on the Al surface of the opening after removing the resin film has a large adverse effect on the bonding strength.
[0003]
When the opening is formed by photolithography in the case of a surface protection film using a polyimide resin, a photosensitive polyimide resin is used as a protection film, and a photosensitive film is formed on a non-photosensitive polyimide (protection) film. There are two methods for covering and opening a resin film.
In the former, a photomask pattern is projected on a polyimide (protection) film by an exposure machine to form a latent image of a predetermined pattern on the protection film, and an alkaline developer (TMAH: 2.38% of tetramethylammonium hydroxide) is used. ) To form an opening by development etching. There are two types of such photosensitive polyimide resins, a negative development type and a positive development type. There are many examples of the latter photosensitive resin (photoresist), which is alkali-soluble and positive developing type, which has better convenience and pattern accuracy than the former organic solvent-soluble negative developing type.
[0004]
In the latter, a non-photosensitive polyimide (protective) film is coated with a positive photoresist film, and the polyimide (protective) film is etched using the patterned photoresist film as a mask to form an opening. At this time, since the developing solution of the photoresist also serves as an etching solution of the polyimide (protection) film, it can be processed continuously.
In the printing application processing, using a screen printing machine, using a patterned SUS mesh or SUS foil as a mask, printing a predetermined pattern on an epoxy-based resin protective film or a polyimide-based resin protective film, and then protecting by etching. Form an opening in the film.
[0005]
The direct opening technique of the polyimide (protection) film by the laser ablation method is a method of directly irradiating a predetermined opening of the polyimide (protection) film with a laser beam having a high energy density, and instantaneously evaporating the irradiated portion to open the opening. It is. Since the laser ablation method has a small laser beam diameter of about several tens of μm or less, there is an advantage that a high precision corresponding thereto can be obtained. In addition, the metal electrode film having a high reflectivity to the laser light such as Al under the polyimide (protective) film to be opened prevents transmission of heat generated by the laser light energy to the lower part. It is also excellent in that it is possible to surely prevent the deterioration and breakage (see Patent Document 1, paragraphs 0003 to 0007, paragraph 0033 and Patent Document 3). A laser ablation method of a polyimide (protection) film on a multilayer wiring board using a ferrite substrate is also known, and a residue of soot (soot) which is likely to remain in an opening after ablation is removed by plasma treatment. It is also known (see Patent Document 2)
[0006]
[Patent Document 1]
JP-A-2002-164591
[Patent Document 2]
JP 2002-252258 A
[Patent Document 3]
JP 2000-117465 A
[0007]
[Problems to be solved by the invention]
However, any of the above-described pattern forming methods has the following problems.
Since the photosensitive polyimide resin contains a large amount of a sensitizer in order to improve the photosensitivity, a gas is easily generated when the resin is cured, and the adhesion to the base is likely to be insufficient. There is. There is also a problem that the photosensitive polyimide resin itself is expensive.
In the case of non-photosensitive polyimide resin, the above-mentioned problems and the like tend to be reduced, but there is a problem that the number of steps is increased because a photoresist is additionally formed as compared with the photosensitive resin.
[0008]
In the printing application processing method, since a resin pattern film having an opening formed in a predetermined portion can be easily obtained with a relatively inexpensive device using a printing mask, it is a good method for cost reduction. The following fine patterns are difficult to form, bubbles are easily entangled, poor separation from the substrate immediately after printing is completed, thin patterns are easily generated or thin substrates that are easily damaged by pressure during printing (for example, in the case of a silicon substrate, (200 μm or less), it is difficult to use.
Another problem with the laser ablation method is that it is not always sufficient to remove soot (soot) or the like remaining on the opening surface after ablation. If the residue such as soot (soot) is not sufficiently removed, a fatal defect that an aluminum wire or a bump plating or the like connected to the opening surface by ultrasonic bonding or the like easily occurs is likely to occur.
[0009]
The present invention has been made in view of the above-described problems, and can be simplified and inexpensive compared with conventional photolithography, and can reduce breakage defects such as cracks even in a semiconductor device using a thin substrate, It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a residue remaining on an opening surface after laser ablation can be removed better, and the occurrence of peeling of an external extraction electrode terminal such as an Al wire or a bump plating bonded to the opening surface is reduced. And
[0010]
[Means for Solving the Problems]
According to the first aspect of the present invention, the object is to form a surface protection film mainly composed of a resin on a substrate provided with an electronic or electric functional element and a metal wiring electrode film connecting the functional element. Then, in a method of manufacturing a semiconductor device in which an opening is formed in the surface protective film on the metal wiring electrode film by laser ablation, the laser ablation under reduced pressure atmosphere is performed through a pattern mask corresponding to the opening. This is achieved by a method of manufacturing a semiconductor device in which after the opening is formed, a cleaning process including a plasma ashing process is performed on the opening surface.
[0011]
According to a second aspect of the present invention, it is preferable that the substrate is a semiconductor substrate or a ferrite substrate.
According to a third aspect of the present invention, it is preferable that the semiconductor substrate has a thickness of 200 μm or less.
According to the fourth aspect of the present invention, the cleaning process is performed on the light receiving surface at 0.2 J / cm. 2 4. The method of manufacturing a semiconductor device according to claim 1, comprising irradiation with a laser light beam having a laser energy density of less than 3, plasma ashing including oxygen-based plasma processing and hydrogen-based plasma processing, and argon sputtering processing. 5. It is also preferable to use a method.
[0012]
According to a fifth aspect of the present invention, it is preferable that the method for manufacturing a semiconductor device according to any one of the first to fourth aspects is such that the surface protective film is made of a polyimide resin or an epoxy resin.
According to the sixth aspect of the present invention, the reduced pressure atmosphere is 1.33 to 0.133 Pa (10 -2 To 10 ―3 It is also desirable that the method of manufacturing a semiconductor device according to any one of claims 1 to 5 be a value within a range of (torr).
According to the invention described in claim 7, the laser energy density of the laser beam for laser ablation is 0.2 to 1.0 J / cm on the light receiving surface. 2 It is preferable that the method for manufacturing a semiconductor device according to any one of claims 1 to 6, which is one of the ranges described above.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below unless departing from the gist thereof.
FIG. 1 is a process cross-sectional view of an IC substrate showing a method of manufacturing a semiconductor device according to the present invention by IC.
FIG. 2 is a process cross-sectional view of an IGBT substrate showing the method of manufacturing a semiconductor device according to the present invention by IGBT,
FIG. 3 is a process cross-sectional view of a composite IC substrate showing a method of manufacturing a semiconductor device according to the present invention by a composite IC.
FIG. 4 is a schematic diagram of a laser beam processing apparatus used in the present invention,
FIG. 5 is a diagram showing the relationship between the energy density of laser light used in the apparatus of FIG. 4 and the number of laser shots (pulses);
FIG. 6 is a diagram showing the relationship between the energy density of laser light and the concentration of carbon atoms in the aperture surface by ESCA analysis.
FIG. 7 is a diagram showing the relationship between the laser light energy density and the carbon atom concentration at the opening surface, which show the effects of the present invention;
FIG. 8 is a diagram showing the relationship between the Al wire peeling rate and the ultrasonic output for bonding Al wires according to the present invention,
FIG. 9 is a top view of an experimental unit A of the semiconductor device according to the present invention,
FIG. 10 is a cross-sectional view of an experimental unit B for examining the peel strength of the Al wire subjected to ultrasonic bonding.
[0014]
Here, the laser ablation according to the present invention will be briefly described. What is laser ablation? When a solid is irradiated with laser light, when the irradiation intensity of the laser light exceeds a threshold, it is converted into electronic, thermal, photochemical and mechanical (mechanical) energy on the surface of the solid. As a result, neutral atoms, molecules, positive and negative ion radicals, clusters, electrons, and light (photons) are explosively released, and this is a process technology in which a solid surface is etched.
The pattern processing of the resin film by laser ablation has a high energy density, using a laser beam in the ultraviolet region having a spot diameter of several tens μm or less, irradiating and exposing only the opening having a predetermined pattern, and instantaneously Since it is etched with high precision, it has the feature that heat hardly reaches other than the irradiated part. At this time, as the laser beam, a photolysis reaction is mainly used, and an excimer laser which is less affected by heat is preferable. Excimer lasers have an ArF wavelength of 192 nm, a KrF wavelength of 248 nm, and a XeCl wavelength of 308 nm, and any laser light can be used in the present invention. In the present invention, a KrF wavelength of 248 nm was used.
[0015]
FIG. 4 shows a laser ablation apparatus 400 used for laser ablation according to the present invention. An excimer laser having a KrF wavelength of 248 nm is used as the laser oscillator 401, and a SUS metal mask having a three-fold enlarged pattern is used as the mask 405 through a beam transmission optical system such as a valuable attenuator 402, a beam expander 403, and a beam homogenizer 404. did.
When it is necessary to match the pattern of the SUS metal mask 405 and the underlying pattern with high precision, the field of view split by the dichroic mirror 406 is finely moved by the CCD camera 408 and the XYZθ stage 412 by the stage controller 413 for processing. The pattern on the substrate 411 to be formed is matched with the pattern of the mask 405 projected to the actual size by the transfer lens 409 on the monitor 407, and the surface protective film 410 is opened one by one in order. The XYZθ stage 412 moves slightly so that the laser beam spot scans the surface protection film in one pattern. The XYZθ stage 412 is controlled by the stage controller 413 so that free fine movement in the XYZθ direction is possible.
[0016]
In the present invention, since the laser ablation needs to be performed in a reduced pressure environment, a group of the transfer lens 409, the substrate 411 to be processed, and the XYZθ stage 412 is placed in the reduced pressure chamber 414. The size of the spot on the processing surface of the laser light beam used in this laser ablation processing apparatus is an ellipse of approximately 12 μm × 25 μm.
As the resin film to be processed, an epoxy resin, a polyimide resin, a silicone resin, a fluorine resin, an acrylic resin, a polycarbonate resin, or the like can be used, but the absorption efficiency with respect to the wavelength of laser light is good, and the processing accuracy is high, From the viewpoints of toughness, thermal expansion coefficient, heat resistance, insulation, solvent resistance and the like as the protective film, polyimide resins and epoxy resins are particularly preferred.
[0017]
In the laser ablation according to the present invention, the portion of the resin film to be processed needs to be formed on the metal wiring electrode film. With such a configuration, even if the laser energy reaches the metal wiring electrode film without being completely absorbed by the resin film, it is almost reflected or absorbed by the electrode film under the above-described conditions. Therefore, particularly in a silicon semiconductor substrate, it is possible to prevent the oxide film under the electrode film and the functional region from deteriorating.
As such an electrode film, an Al electrode film having a high reflectance to the laser light is preferable, but a Ni film or another alloy film may be used.
[0018]
Hereinafter, experimental examples in which the method of manufacturing a semiconductor device according to the present invention is performed under appropriate conditions for laser ablation and cleaning conditions after opening will be described.
(Experimental example)
In conventional laser ablation, there was a case where the removal of soot-like residue remaining in the opening after ablation was not sufficient, so in order to find an ablation method that can sufficiently remove the residue, depending on the ablation conditions, A tensile test was performed on the Al wire to see how the degree of soot-like residue changes and its relationship with the bonding strength of the Al wire. .
[0019]
Experimental unit A shown in FIG. 9 is a top view of the semiconductor substrate before connecting an Al wire to the opening, and is a unit sample for examining the surface state of the opening after ablation. Experimental unit B shown in FIG. 10 is a cross-sectional view showing a state in which a Ni—Al film and a polyimide film are formed on a copper substrate, an opening is formed, and an Al wire is connected by bonding. 5 is a unit sample for performing a peeling test of a finished Al wire. The method of creating each of these experimental units is described below. In the experimental unit A, a polyimide resin film was used as the surface protective film, but almost the same result can be obtained by using an epoxy resin.
[0020]
Experimental unit A (FIG. 9) —Al / Si film is coated to a thickness of 5 μm on a 550 μm-thick Si substrate (bare) 901 by sputtering, and a polyimide film 903 is applied thereon to a thickness of 10 μm. Openings (wire bonding portions) 904 were formed in the polyimide film 903 in a predetermined pattern shown in FIG. 9 using the ablation processing apparatus shown in FIG. As a mask to be used in this pattern processing, a SUS mask in which a pattern for forming two 5 × 2 mm rectangular polyimide film removing portions 904 on the surface of a unit substrate having a side of 7 mm square was enlarged three times was used. In the experimental unit A, a thick substrate is used because the purpose is to check the cleanliness of the opening surface. However, a thin substrate may be used.
[0021]
Experimental unit B (FIG. 10) —A substrate 1001 on which a copper plate was Ni-plated and then Al—Si (1%) was sputter-adhered (1002), and a polyimide film 1003 was mounted thereon with an epoxy-based adhesive. After forming the opening 1004 by each of the patterning methods described above, an Al wire 1005 having a diameter of 300 μm was bonded by an ultrasonic bonder (not shown). Five Al wires 1005 were bonded to one opening (bonding portion) 1004, and the other end was directly bonded to the substrate so that a tensile test could be performed. The ultrasonic bonding conditions were a frequency of 110 KHz, a load of 600 g, a bonding time of 150 msec, and an amplitude of 1 to 3 mm.
[0022]
First, the relationship between the laser energy density and the number of laser shots (pulses) with respect to the total laser energy required for forming an opening of a direct polyimide film having a certain reference dimension was examined by the laser ablation processing apparatus. FIG. 5 shows the relationship. It can be seen from FIG. 5 that when the laser energy density is high, the number of shots (pulses) is small, and when the laser energy density is low, the number of shots (pulses) is large. However, the laser energy density shown on the horizontal axis of FIG. 2 If the height is too high, the Al electrode on the opening surface and, in some cases, an oxide film thereunder may be adversely affected, which is not preferable. 0.1 J / cm 2 It was found that if the number of shots (pulses) was increased, the opening could not be sufficiently performed when the number was lower. In the following description, all values of the laser energy density are values measured on the light receiving surface.
[0023]
Under these conditions, the relationship between the laser energy density shown in FIG. 6 and the carbon atom concentration (atm%) on the opening surface was determined by ESCA analysis. A plot line 601 in FIG. 6 shows the relationship between the carbon atom concentration on the opening surface immediately after laser ablation (no cleaning) shown on the vertical axis and the laser energy density during laser ablation shown on the horizontal axis. Similarly, a plot line 602 shows the carbon atom concentration and the laser energy of the opening surface after cleaning the opening surface by wet treatment using a commercially available photoresist stripping solution (502A of Tokyo Ohka Co., Ltd.) after the laser ablation under the same conditions. The relationship with the density is shown.
[0024]
In FIG. 6, 0.1 J / cm 2 When viewed in the direction of the vertical axis, the opening surface (Al-Si electrode surface) immediately after the laser ablation processing indicates that about 90 atm% (atomic%) of carbon is present (plot line 601). When the wet cleaning is added, the carbon atom concentration decreases to about 60 atm% (plot line 602), which indicates that the addition of the wet cleaning is effective.
However, observation of the opening surface with a high-magnification SEM revealed that carbon was scattered in the form of fine island-like thin films or particles. When the laser energy density is further increased (0.2 J / cm 2 , 0.4J / cm 2 , 0.6 J / cm 2 , 0.8J / cm 2 , 1.0 J / cm 2 ) Is 0.1 J / cm 2 From 0.2 J / cm 2 When the energy density is increased, the carbon atom concentration changes (decreases). However, even after the wet cleaning, the carbon atom concentration is reduced only from about 60 atm% to at most about 40 atm%. Further, it is understood that even if the energy density of the laser is further increased, the reduction of the coal bed concentration at the opening surface is not significantly affected.
[0025]
At the carbon atom concentration level of about 40 atm%, the wetting angle to pure water is as large as 100 degrees, and it is still insufficient to solve the problem of peeling of the Al wire. That is, although the addition of wet cleaning alone is effective for reducing the carbon atom concentration, it has been found that there is a limit to the solution of the peeling problem.
On the other hand, the carbon atom concentration on the opening surface after pattern processing only by photolithography without laser ablation processing is a low level of about 20 atm% or less, the wetting angle to pure water is as small as 10 to 20 degrees, and the It is also known that there is no problem in peeling (not shown). However, photolithography processing has a problem of high cost. In order to solve the problem of peeling of the Al wire also in the case of laser ablation processing, it is necessary that the carbon atom concentration of the opening surface after the laser ablation processing be at the same level as about 20 atm% in the case of the photolithography processing. I thought.
[0026]
As described above, various opening cleaning experiments were repeated to keep the carbon atom concentration at the same level as about 20 atm%. As a result, once the decomposed particles of the polyimide resin film were blown off during laser ablation processing, they were re-used. It turned out that there is much soot-like residue attached. It was found that if this soot residue was large, it could not be sufficiently removed by the conventional plasma treatment alone, and it was considered important to reduce the soot residue as much as possible before the plasma treatment. As shown below, it has been found that the method of cleaning the opening, which is an improvement of the known plasma cleaning process, is extremely effective in removing soot and the like remaining in the opening after laser ablation, and the method of manufacturing a semiconductor device according to the present invention. Reached.
[0027]
Hereinafter, the laser ablation processing according to the method of manufacturing a semiconductor device according to the present invention and the subsequent cleaning processing of the opening will be specifically described.
Using the experimental unit A of the semiconductor device shown in FIG. 9, the laser ablation processing was performed on the polyimide protective film at 1 torr = 133.3 Pa (10 -2 -10 -3 Laser energy density 0.1 J / cm under reduced pressure of torr) 2 , 0.4J / cm 2 , 1.0 J / cm 2 After each opening, 0.1 J / cm 2 Laser ablation processing was repeated three times for one pattern, and then plasma treatment was performed.
[0028]
As described above, it is important to perform the laser ablation opening process under reduced pressure, and if necessary, further apply a weak laser ablation to reduce the residue in the opening before the plasma process. That is extremely important. As for the pressure reduction conditions, the above-mentioned range is sufficient, and even if the pressure is reduced further, the effect is not so great because only the apparatus becomes expensive. The conditions of the subsequent plasma treatment are shown below.
Parallel plate type plasma device
13.56 MHZ frequency-1000 watt maximum bias power device
Processing output 500 watts
Atmosphere O 2 : N 2 = 4: 1 (O 2 100ml / min + N 2 25ml / min)
Gas pressure 20Pa
Electrode temperature 80-85 ° C
Processing time 120 seconds
The oxygen-based plasma treatment was performed under the conditions described above, and then the treatment was performed using the same apparatus while changing the conditions to a reducing atmosphere as described below.
Processing output 750 watts
Atmosphere H 2 : N 2 = 4: 1 (H 2 100ml / min + N 2 25ml / min)
Gas pressure 20Pa
Electrode temperature 80 ℃
Processing time 240 seconds
Cleaning by Ar (argon) sputtering
Frequency 13.56MHZ
Processing output 400 watts
Ar 10ml / min
Gas pressure 10Pa
Processing time 30 seconds
For the experimental unit A manufactured under the above conditions, the carbon atom concentration in the opening was examined by ESCA analysis in each of the case immediately after the laser ablation processing and the case in which the cleaning treatment according to the present invention was further added. FIG. 7 shows the result.
[0029]
A plot line 701 in FIG. 7 indicates the carbon atom concentration immediately after the laser ablation processing, and a plot line 702 indicates the carbon atom concentration after the laser ablation processing and after the cleaning processing by the plasma apparatus according to the present invention. The plot line 702 shows that the concentration of carbon atoms existing on the opening surface is extremely reduced as compared with the plot line 701 before the cleaning process. As can be seen from the comparison with the plot line 602 in FIG. It can be seen that the carbon atom concentration level of the plot line 702 is close to or almost equal to the carbon atom concentration level of only the conventional photolithography processing without laser ablation.
[0030]
A unit sample in which an opening was formed by a conventional photolithography process using the experimental unit B shown in FIG. 10 and a laser energy density of 0.2 J / cm. 2 And 1.0 J / cm 2 Each unit sample in which an opening (wire bonding portion) was formed by each laser ablation process of the present invention and the cleaning process according to the present invention was prepared, and five Al wires were bonded to each opening, and the other end was directly on the substrate. And then pulled until they were cut one by one, and the peeling strength was examined by examining the cut locations. FIG. 8 shows the result.
[0031]
FIG. 8 shows the ultrasonic output at the time of bonding of the Al wire on the horizontal axis in terms of the output ratio% to the maximum output of 100%. The vertical axis indicates the peeling rate of the Al wire from the bonding interface when the wire is pulled by the above-described tensile test method. The peeling rate of the Al wire refers to the percentage of the Al wire 1005 in FIG. 10 that has peeled from the bonding interface 1006 with the electrode film 1002 on the opening surface 1004. The Al wire 1005 cut at the neck 1007 or at the middle of the wire 1008 is regarded as a non-defective product.
A plot line 801 in FIG. 8 shows a tensile test result in the case of the experimental unit B in which the opening is formed only by photolithography. The ultrasonic bonding output of the Al wire is 70% or more, and the peeling rate is 0%, in other words, In all cases, the cutting is not performed at the bonding interface of the Al wire but in the middle of the wire.
[0032]
The plot lines 802 and 803 according to the present invention show the laser ablation of 0.4 J / cm, respectively, as shown by the plot line 702 in FIG. 2 And 1.0 J / cm 2 The opening is performed at a laser light energy density of 0.1 J / cm 2 10 shows the results of a tensile test in an experimental unit B in which oxygen-based plasma treatment and reduction-based plasma treatment under the same conditions as the above-described plasma treatment were performed three times after performing weak laser ablation three times.
The plot lines 802 and 803 indicate that the ultrasonic output may be set to 75% and 80%, respectively, in order to set the peeling rate to 0%. The output of the ultrasonic wave is preferably as low as possible as shown by the plot line 801, and the peeling rate of the Al wire is preferably 0%. The output 70% in the case of the plot line 801 is a measure of the cleanliness of the opening surface. It becomes.
[0033]
For example, on an opening surface having a cleanliness of 40 to 60 atm% shown by the plot line 602 described with reference to FIG. 6, although not shown, the peeling rate becomes 30% or more even when the ultrasonic output is 100%, I know I can't solve the problem. Further, if the ultrasonic output exceeds 90%, adverse effects such as cracks on the Al electrode surface and the insulating film under Al become particularly remarkable, leading to deterioration of withstand voltage, which is not preferable.
0.1 J / cm 2 It was also found that the degree of removal of residues such as soot increased when the number of repetitions of the laser ablation of which was weak was 1 to 3, but when the number was 4 or more, the degree of removal did not increase so much. It is considered that the soot to be removed by the weak laser ablation was not the residue remaining at the time of the opening, but the soot blown up by the high heat at the time of the opening and re-adhered to the opening surface. Surprisingly, it has been found that this weak laser ablation has a great effect on the removal of soot from the openings.
[0034]
Even in the case where the cleaning cannot be sufficiently performed only by the plasma treatment performed thereafter, the removal effect of the soot is increased by combining with the weak laser ablation. This weak laser ablation has a low adverse effect on the aperture surface even if it is repeatedly irradiated. 2 The following laser energy density is preferred, 0.01 J / cm 2 Below, since the removal effect becomes small, 0.05 to 0.2 J / cm 2 Was found to be optimal.
According to the laser ablation process and the subsequent plasma cleaning process according to the present invention, the process can be simplified and the cost is reduced as compared with the conventional process using only photolithography, but the remaining soot and the like on the opening surface is reduced. It can be seen that the manufacturing method can be reduced as much as processing by only photolithography.
[0035]
The Ar sputtering may be omitted if necessary. The cleaning process described above is performed only once, but may be performed repeatedly.
In the case of an actual silicon semiconductor substrate or ferrite substrate instead of the experimental unit, the number of patterns to be opened in the same substrate is very large.In such a case, after opening all the patterns first, Cleaning including weak laser ablation is performed.
Hereinafter, an example of a method of manufacturing a semiconductor device manufactured using laser ablation conditions obtained from the above experimental results and subsequent cleaning conditions will be specifically described with reference to the drawings.
[0036]
(Example 1)
FIG. 1 is a process sectional view showing a method for manufacturing an IC having a general MOS type semiconductor device 100. A 8000 Å thick LOCOS insulating isolation film 102 is formed on one surface of a 6-inch semiconductor substrate 101 having a p-type resistivity of 10 to 15 Ωcm and a thickness of 625 μm by a known process so that the gate length 105 becomes 1 μm. Then, a gate oxide film 104 having a thickness of 250 angstroms is formed, a polysilicon gate electrode 103 is formed to a thickness of about 0.3 μm, and is processed into a polysilicon gate electrode and a gate film having a predetermined pattern by photolithography. N as contact layer + The layer 106 has a surface concentration of 1.0 × 10 19 cm -3 To a depth of 0.2 μm.
[0037]
At this time, the polysilicon electrode is simultaneously 31 p + The function as a gate electrode is made effective by implanting ions and adjusting the specific resistance to 10 to 20 Ωcm. Next, an oxide film 107 is formed as an interlayer insulating film. This oxide film 107 has a high temperature thermal oxide (HTO) of 1200 Å and a BPSG (Boro Phospho).
Silicate Glass (6000-8000 Angstroms). The contact portions (109, 110, 111) are opened in the oxide film 107 by photolithography, and an Al electrode 108 in contact with the polysilicon electrode is formed. The Al electrode 108 was made of an alloy having a composition of Al: Si: Cu = 98.9%: 1%: 0.1%, and was formed to have a thickness of 1 μm (FIG. 1A).
[0038]
As shown in the cross-sectional view of FIG. 1B, a polyimide film having a thickness of about 10 μm is formed as the surface protection film 112. Subsequently, as shown in FIG. 1C, the respective portions (source portions of the source, gate, and drain electrodes) 113, 114, and 115 of the polyimide film 112 are formed on the Al electrode 108 by the above-described laser ablation according to the present invention. Are sequentially opened for all the patterns so that the patterns are exposed.
The conditions for the laser ablation are as follows. Using an ablation apparatus shown in FIG. 4, an excimer laser having a KrF wavelength of 248 nm was applied to the opening surface of the polyimide film at 1.0 J / cm. 2 Irradiation was performed so that the laser energy density became. Immediately after opening all patterns, 0.1 J / cm 2 Laser ablation irradiation with a weak laser energy density was performed three times, and then the opening was cleaned by plasma treatment.
[0039]
The plasma processing conditions were the same as the plasma processing conditions (including Ar sputtering) in the experimental unit A shown in FIG. In Example 1, the formation of the opening for the bonding pad in the polyimide protective film was performed by using laser ablation, so that the problem of peeling off the Al bonding wire could be solved, the process could be simplified, and the cost was reduced. .
(Example 2)
FIG. 2 is a process cross-sectional view showing a method for manufacturing an IGBT (insulated gate bipolar transistor) element substrate 200. This IGBT element substrate has a drain side p + Layer 208, n + Buffer layer 212, n formed by epitaxial growth − The conductivity modulating layer 201, n − A p-well layer 206 formed on the surface of the layer 201; − A gate electrode 204 made of polysilicon is formed on a surface of the layer 201 with a gate oxide film 203 interposed therebetween. + A source region 207 is formed, and n is formed under the gate oxide film 203. + Source region 207 and n − A channel region 209 is formed on the surface of the p-well layer 206 sandwiched between the layers 201. The emitter 206 and n + The emitter electrode 205-1, the drain side p + A drain electrode layer 205-2 is formed on the layer 208, and a gate electrode 205-3 is formed on the polysilicon gate electrode 204 using an Al film.
[0040]
An IGBT silicon substrate with a rated voltage and a rated current of 600 volts and 100 to 200 amperes respectively has a drain side p of 0.02 Ωcm. + 0.1 Ωcm n for layer 208 + A buffer layer 212 is formed to a depth of 10 μm, and a drain p is formed. + On a silicon substrate having the layer 208 of 30 μm, a 40 Ωcm n − A layer 201 having a thickness of 70 μm epitaxially grown (total 110 μm) is used.
A thick initial oxide film 202 is formed on the silicon substrate, a window is formed in the oxide film 202 in a predetermined pattern for forming a p-well layer 206, boron ions are implanted, and a p-well layer is formed through doping and driving. Step 206 is formed. After forming gate oxide film 203 to a thickness of 800 to 1000 angstroms, a polysilicon film is formed to a thickness of 5000 angstroms on gate oxide film 203.
[0041]
These films are pattern-etched by photolithography to form a gate oxide film 203 and a polysilicon gate electrode 204 as shown in FIG. Using the formed gate oxide film 203 and the polysilicon gate electrode 204 as a mask, boron ions are ion-implanted and heated to a boron concentration of 1 × 10 14 cm -3 Is formed to a depth of 3 to 4 μm. Subsequently, n is set using the photoresist film as a mask. + The source region 207 has a phosphorus concentration of 5 × 10 Fifteen cm -3 To a depth of 1 μm.
The oxide film 202 formed as an interlayer insulating film is pattern-etched by photolithography, an Al electrode 205-1 (Al-Si (1%)) is formed to a thickness of 5 μm by sputtering, and formed into a predetermined pattern by photolithography. (FIG. 2A). As shown in FIG. 2B, a polyimide resin is coated as a surface protection film 210 to a thickness of 10 μm.
[0042]
Thereafter, as shown in FIG. 2C, the polyimide resin film on the electrode pad portion 211 serving as an electrode terminal take-out portion on the Al electrode film 205 is sequentially opened for all patterns by the laser ablation according to the present invention. The laser ablation conditions and the subsequent cleaning treatment of the opening surface were the same as those in Example 1.
In Example 2, a thin silicon substrate having a thickness of 110 μm was used, but in the present invention, laser ablation was used for forming the opening for the bonding pad in the polyimide protective film, so that the problem of peeling off the Al bonding wire could be solved. Since it was carried out in a non-contact manner, the occurrence of cracks in the silicon substrate was small, and the process was simplified as compared with the photolithography processing, so that it could be manufactured at low cost. Generally, when a silicon semiconductor substrate having a thickness of 200 μm or less, particularly 150 μm or less is used, cracking of the substrate “is likely to occur, but according to the present invention, cracking of the substrate can be reduced.
[0043]
(Example 3)
FIG. 3A is a cross-sectional view of the composite IC 300. This composite IC is obtained by laminating a dedicated IC chip (IC substrate) 301 for a specific application and a thin-film inductor 320 having an inductor function on a predetermined electrode pad 318 on a circuit board 310 via a bonding metal 317. It has a configuration that is placed.
FIG. 3D shows an electric circuit of the composite IC shown in FIG. 3A, in which the dedicated IC chip 301 for the specific application and the thin-film inductor 320 shown in a dotted frame are connected as shown. To indicate that 3B and 3C show a top view and a bottom view of the thin-film inductor 320, respectively. The thin-film inductor 320 has an inductor function by forming metal wirings 306 and 307 into a coil shape using both surfaces of the substrate via through holes 313 formed in the ferrite substrate 305.
[0044]
The ferrite substrate 305 is prepared by mixing powders such as Mn-Zn, Cu-Zn, or Ni-Zn with an appropriate component composition so as to have a required magnetic permeability, forming the mixture into a predetermined shape, and heating at a temperature of 1100 ° C to 1200 ° C. It is made by sintering at high temperature. The magnetic permeability of the thus obtained Mn-Zn-Cu-Ni-based ferrite substrate 305 having a thickness of about 500 µm was about 1,000.
In the ferrite substrate 305, through holes 313 having a diameter of 0.2 mmφ are arranged as shown in FIGS. 3 (b) and 3 (c) by using a metal or resin or the like as a mask by sandblasting, laser light, ion beam, high-pressure jet water or the like. Then, metal wirings 306 and 307 were formed on both sides through the through holes to form an inductor. The continuity in the through hole can be established by sputtering Ti (0.1 μm) / Cu (0.2 μm) on both surfaces and then applying electroless Cu plating to a thickness of 0.2 to 0.4 μm to form the through hole 313. Was formed by coating with a metal plating film.
[0045]
The coil portion of the inductor is formed by forming a predetermined pattern with a dry film so that portions corresponding to the upper coil wiring 306 in FIG. 3B, the lower coil wiring 307 in FIG. After being formed by exposure and development, electrolytic copper plating was laminated using a dry film as a mask to a thickness of 40 μm, Ni plating 5 μm, and Au plating 1 μm to form the metal wirings 306 and 307 in the coil portion. After that, a surface protective film 308 made of a polyimide film or the like is applied to a thickness of 50 to 60 μm, and the polyimide film is dried by heat treatment. Then, the opening 316 of the upper / lower connection electrode 309 is opened by laser ablation according to the present invention. . The laser ablation conditions and the subsequent cleaning treatment of the opening surface were the same as in Example 1 described above.
[0046]
On the other hand, as described in the first embodiment, the IC chip 301 is also subjected to the laser ablation processing according to the present invention, and the Al electrode pad 303 is opened. The IC chip 301 and the thin film inductor 320 are joined to the electrode pads 303 and 316 via a joining metal 317.
The bonding metal 317 is obtained by subjecting the Al electrode pad 303 of the IC chip to a Zn activation treatment, and then electroless Ni plating of 20 to 30 μm, a 0.05 μm thick Au bump electrode, a stud bump by Au wire bonding, or a Ti / Cu seed layer. A convex bump electrode is formed by using, for example, a 5 μm thick Ni by sputtering of a (seed layer) and a bump of 30 to 50 μm solder by electrolytic plating. On the back side of the ferrite substrate 305 (FIG. 3C), solder cream is formed on the electrode pads 318 on the circuit board 310 in advance by screen printing to a thickness of 50 to 60 μm, and is connected by a solder reflow method. In the third embodiment, since the opening of the bump electrode pad of the polyimide protective film is formed by the laser ablation according to the present invention, the opening can be made more accurate than the conventional opening by screen printing or the like, and at the same cost as the cost. I was able to.
[0047]
【The invention's effect】
According to the present invention, after a surface protection film mainly composed of resin is formed on a substrate provided with an electronic or electrical functional element and a metal wiring electrode film connecting the functional element, the metal wiring is formed by laser ablation. In the method for manufacturing a semiconductor device in which an opening is formed in the surface protective film on an electrode film, after forming the opening by laser ablation under a reduced-pressure atmosphere through a pattern mask corresponding to the opening. Since the method of manufacturing a semiconductor device in which the opening surface is subjected to a cleaning process including a plasma ashing process, the process is simpler and cheaper than photolithography, and even a semiconductor device using a thin substrate can be damaged or damaged, such as cracking. Al wires that can be reduced and that the residue remaining on the opening after laser ablation can be removed better and that there is an Al wire bonded to this opening It is provide a method of manufacturing a semiconductor device to reduce the occurrence of peeling of the external extraction electrode terminals made of bump plating.
[Brief description of the drawings]
FIG. 1 is a process sectional view of an IC substrate showing a method of manufacturing a semiconductor device according to the present invention by using an IC.
FIG. 2 is a process cross-sectional view of an IGBT substrate showing the method of manufacturing a semiconductor device according to the present invention by IGBT.
FIG. 3 is a process cross-sectional view of a composite IC substrate showing a method of manufacturing a semiconductor device according to the present invention by a composite IC.
FIG. 4 is a schematic view of a laser ablation processing apparatus used in the present invention.
5 is a diagram showing the relationship between the energy density of laser light used in the apparatus shown in FIG. 4 and the number of laser shots (pulses).
FIG. 6 is a graph showing the relationship between the energy density of laser light and the concentration of carbon atoms on the aperture surface according to the present invention.
FIG. 7 is a graph showing the relationship between the energy density of laser light and the concentration of carbon atoms on the aperture surface according to the present invention.
FIG. 8 is a diagram showing a relationship between an Al wire peeling rate and an ultrasonic output for bonding an Al wire according to the present invention.
FIG. 9 is a top view of an experimental unit A of the semiconductor device according to the present invention.
FIG. 10 is a sectional view of an experimental unit B for examining the peel strength of an Al wire.
[Explanation of symbols]
100 MOS type semiconductor device
108 Al electrode
112 Surface protective film
113 Source electrode pad (opening)
114 Gate electrode pad (opening)
115 Drain electrode pad (opening)
200 IGBT semiconductor device
205-1 Emitter Al electrode
205-2 Drain Al electrode
205-3 Gate Al electrode
210 Surface protective film
211 electrode pad (opening)
300 Composite IC device
303 IC chip electrode pad (opening)
308 Surface protective film
316 Ferrite substrate electrode pad (opening)
400 Laser ablation device.

Claims (7)

電子または電気機能要素と、該機能要素を接続する金属配線電極膜とを備える基板上に、樹脂を主成分とする表面保護膜を被覆した後、レーザーアブレーションにより前記金属配線電極膜上の前記表面保護膜に開口部を形成してなる半導体装置の製造方法において、前記開口部に対応するパターンマスクを介して、減圧雰囲気下でレーザーアブレーションにより前記開口部を形成した後、前記開口面にプラズマ灰化処理を含むクリーニング処理を施すことを特徴とする半導体装置の製造方法。After coating a surface protection film mainly composed of resin on a substrate provided with an electronic or electric functional element and a metal wiring electrode film connecting the functional element, the surface on the metal wiring electrode film is subjected to laser ablation. In a method of manufacturing a semiconductor device having an opening formed in a protective film, the opening is formed by laser ablation under reduced pressure through a pattern mask corresponding to the opening, and then plasma ash is formed on the opening surface. A method for manufacturing a semiconductor device, comprising performing a cleaning process including a chemical conversion process. 基板がシリコン半導体基板またはフェライト基板であることを特徴とする請求項１記載の半導体装置の製造方法。2. The method according to claim 1, wherein the substrate is a silicon semiconductor substrate or a ferrite substrate. シリコン半導体基板の厚さが２００μｍ以下であることを特徴とする請求項２記載の半導体装置の製造方法。3. The method according to claim 2, wherein the thickness of the silicon semiconductor substrate is 200 μm or less. クリーニング処理が受光面で０．２Ｊ／ｃｍ２未満のレーザーエネルギー密度のレーザー光ビームによる照射、酸素系プラズマ処理と水素系プラズマ処理を含むプラズマ灰化処理およびアルゴンスパッタリング処理を含むことを特徴とする請求項１乃至３のいずれか一項記載の半導体装置の製造方法。The cleaning process includes irradiation with a laser beam having a laser energy density of less than 0.2 J / cm 2 on the light receiving surface, plasma ashing process including oxygen-based plasma process and hydrogen-based plasma process, and argon sputtering process. A method for manufacturing a semiconductor device according to claim 1. 表面保護膜がポリイミド樹脂またはエポキシ樹脂であることを特徴とする請求項１乃至４のいずれか一項に記載の半導体装置の製造方法。The method according to claim 1, wherein the surface protection film is a polyimide resin or an epoxy resin. 減圧雰囲気が１．３３乃至０．１３３Ｐａ（１０―２乃至１０―３ｔｏｒｒ）の範囲内のいずれかの値であることを特徴とする請求項１乃至５のいずれか一項に記載の半導体装置の製造方法。6. The semiconductor device according to claim 1, wherein the reduced pressure atmosphere has a value within a range of 1.33 to 0.133 Pa (10 −2 to 10 −3 torr). 7. Manufacturing method. レーザーアブレーションのレーザー光ビームのレーザーエネルギー密度が受光面で０．２乃至１．０Ｊ／ｃｍ２の範囲のいずれかであることを特徴とする請求項１乃至６のいずれか一項に記載の半導体装置の製造方法。The semiconductor according to any one of claims 1 to 6, wherein the laser energy density of the laser light beam for laser ablation is in a range of 0.2 to 1.0 J / cm 2 on the light receiving surface. Device manufacturing method.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006068153A1 (en) * 2004-12-22 2006-06-29 Asahi Glass Co., Ltd. Pattern forming method and electronic circuit manufactured by same
WO2006070649A1 (en) * 2004-12-27 2006-07-06 Asahi Glass Co., Ltd. Pattern forming method and electronic circuit
WO2006070648A1 (en) * 2004-12-27 2006-07-06 Asahi Glass Co., Ltd. Pattern forming method and electronic circuit
JP2008193035A (en) * 2007-02-08 2008-08-21 Matsushita Electric Ind Co Ltd Fine shape transferring method and fine shape transfer device
JP2010515251A (en) * 2006-12-28 2010-05-06 サントル ナシオナル デチュード スパシアル Method and apparatus for exposing the surface of an integrated circuit
JP2011014749A (en) * 2009-07-02 2011-01-20 Fuji Electric Systems Co Ltd Method for manufacturing semiconductor device
US8420512B2 (en) 2008-12-11 2013-04-16 Fuji Electric Co., Ltd. Method for manufacturing semiconductor device
JP2022019549A (en) * 2020-07-15 2022-01-27 芝浦メカトロニクス株式会社 Plasma processing apparatus

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06339784A (en) * 1993-05-31 1994-12-13 Sumitomo Heavy Ind Ltd Laser beam processing method and device therefor
JPH08187588A (en) * 1995-01-06 1996-07-23 Sumitomo Heavy Ind Ltd Laser beam processing method
JPH08236574A (en) * 1995-02-22 1996-09-13 Ricoh Co Ltd Method of assembling semiconductor device
JPH08241894A (en) * 1995-03-03 1996-09-17 Fujitsu Ltd Laser abrasion processing method
JP2000124314A (en) * 1998-08-13 2000-04-28 Internatl Business Mach Corp <Ibm> Module type high frequency integrated circuit structure and manufacture thereof
JP2002009435A (en) * 2000-06-20 2002-01-11 Sumitomo Heavy Ind Ltd Processing method and forming method for via hole of organic substance substrate
JP2002335063A (en) * 2001-05-09 2002-11-22 Hitachi Via Mechanics Ltd Method and apparatus for drilling printed board

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06339784A (en) * 1993-05-31 1994-12-13 Sumitomo Heavy Ind Ltd Laser beam processing method and device therefor
JPH08187588A (en) * 1995-01-06 1996-07-23 Sumitomo Heavy Ind Ltd Laser beam processing method
JPH08236574A (en) * 1995-02-22 1996-09-13 Ricoh Co Ltd Method of assembling semiconductor device
JPH08241894A (en) * 1995-03-03 1996-09-17 Fujitsu Ltd Laser abrasion processing method
JP2000124314A (en) * 1998-08-13 2000-04-28 Internatl Business Mach Corp <Ibm> Module type high frequency integrated circuit structure and manufacture thereof
JP2002009435A (en) * 2000-06-20 2002-01-11 Sumitomo Heavy Ind Ltd Processing method and forming method for via hole of organic substance substrate
JP2002335063A (en) * 2001-05-09 2002-11-22 Hitachi Via Mechanics Ltd Method and apparatus for drilling printed board

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006068153A1 (en) * 2004-12-22 2006-06-29 Asahi Glass Co., Ltd. Pattern forming method and electronic circuit manufactured by same
WO2006070649A1 (en) * 2004-12-27 2006-07-06 Asahi Glass Co., Ltd. Pattern forming method and electronic circuit
WO2006070648A1 (en) * 2004-12-27 2006-07-06 Asahi Glass Co., Ltd. Pattern forming method and electronic circuit
JP2010515251A (en) * 2006-12-28 2010-05-06 サントル ナシオナル デチュード スパシアル Method and apparatus for exposing the surface of an integrated circuit
KR101348971B1 (en) * 2006-12-28 2014-01-10 쌍트르 나쇼날 데튜드 스파씨알르 Method and equipment for exposing the surface of an integrated circuit
JP2008193035A (en) * 2007-02-08 2008-08-21 Matsushita Electric Ind Co Ltd Fine shape transferring method and fine shape transfer device
US8420512B2 (en) 2008-12-11 2013-04-16 Fuji Electric Co., Ltd. Method for manufacturing semiconductor device
JP2011014749A (en) * 2009-07-02 2011-01-20 Fuji Electric Systems Co Ltd Method for manufacturing semiconductor device
JP2022019549A (en) * 2020-07-15 2022-01-27 芝浦メカトロニクス株式会社 Plasma processing apparatus
JP7146017B2 (en) 2020-07-15 2022-10-03 芝浦メカトロニクス株式会社 Plasma processing equipment

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