JP2004265478A - Viterbi decoder and information reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a circuit size reduction and a high-speed operation by subtracting 1/N of a minimum metric outputted from a likelihood determination section to perform normalization at the adder of a viterbi decoder. <P>SOLUTION: A branch metric (BM) value from a waveform equalizer 13, a past metric (P metric) from a metric register 55, and the minimum value of a P metric from a minimum value selection section 57 as a likelihood determination section are inputted to the adder 53 of a viterbi decoder 15. At the adder 53, the BM value and the P metric are added together, and the value of 1/N of the minimum value of the P metric is subtracted, and thus normalization processing is performed to prevent overflowing. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information reproducing apparatus, and more particularly to a Viterbi decoder and an information reproducing apparatus used for PRML (Partial Response and Maximum Likelihood) signal processing and the like.
[0002]
[Prior art]
2. Description of the Related Art In recent years, an equalization / decoding method called PRML signal processing has been generally used in information recording / reproducing apparatuses such as hard disks and optical disks. In the PRML signal processing, the equalizer performs waveform equalization so as to have a known correlation called PR (Partial Response) characteristic, and performs decoding using the PR characteristic of the waveform-equalized reproduction signal in a decoder. . For example, in the case of the PR (1,2,2,1) characteristic, an input code such as 000122110 is output for an input sequence of 00100000, 000134310 is output for 000110000, and 000135531 is output for 00011100000. And its output is expressed by convolution of the PR characteristic. The decoder decodes the PR-equalized reproduced signal by recursively calculating the metric of the state transition. A typical decoding method is the Viterbi decoding method. The Viterbi decoding method is a method of decoding a convolutional code, and a decoder based on this method is called a Viterbi decoder. The Viterbi decoder generally includes an addition / comparison / selection unit (hereinafter, referred to as an ACS unit) for adding / comparing and selecting metrics of a plurality of paths, a path memory unit for holding / updating the selected path, and a path surviving the selected path. And a maximum likelihood determination unit that selects the most likely one from
[0003]
When this Viterbi decoder is implemented by a circuit, there is a problem that the circuit scale is increased due to the complexity of the algorithm. Since a critical path exists in the ACS section of the Viterbi decoder, it is desirable to reduce the scale as much as possible in order to realize high-speed operation of the circuit. Furthermore, since the ACS unit adds, compares, and selects the past metric and the current metric each time, some means is required to avoid overflow before and after the addition.
[0004]
As a solution to this problem, in the ACS unit of the Viterbi decoder, an adder that adds the branch metric of each state and the past metric is compared with an adder that compares the output of the adder and selects a metric with the highest likelihood. A method has been considered in which a metric normalization circuit including a subtractor for calculating a difference between a metric of an arbitrary state and a metric of each state is provided between the selectors to avoid overflow of the metric and reduce the circuit scale (for example, And Patent Document 1.).
[0005]
[Patent Document 1]
JP-A-10-150371 (page 3-10, FIG. 12)
[0006]
[Problems to be solved by the invention]
In Patent Document 1, a metric overflow is avoided by subtracting a metric of an arbitrary state and a metric of each state. However, a metric value in an arbitrary state does not have a constant relative relationship (magnitude relation) to a metric value in another state. Since the fluctuation of the relative relationship leads to the fluctuation of the normalized metric value after the subtraction, the required number of calculation digits may increase depending on the input signal.
[0007]
The present invention has been made to solve the above-described problem, and performs normalization by subtracting 1 / N of the minimum metric output by the maximum likelihood determination unit instead of the metric value in an arbitrary state. It is another object of the present invention to provide a Viterbi decoder and an information reproducing apparatus which realize a reduced circuit scale and a high-speed operation.
[0008]
[Means for Solving the Problems]
A Viterbi decoder according to the present invention includes a branch metric calculator that calculates a branch metric that is a square error between an ideal amplitude value determined according to a partial response characteristic and an input signal, and a branch metric calculated by the branch metric calculator. An adder for adding a past metric; a comparator for comparing paths based on state transition from the addition result of the adder; and a metric selection from the comparison result of the comparator and the addition result of the adder. A selection unit, a metric register for holding the metric selected by the selection unit, and supplying the held metric as a past metric to the addition unit, a path memory unit for holding a history of comparison results of the comparison unit, and a metric register Compare the past metrics held in and select the smallest metric, And a minimum value selection unit that selects the minimum value of the path metric stored in the path memory unit corresponding to the metric of the metric. The minimum value of the past path metric selected by the minimum value selection unit is fed back to the addition circuit. To perform normalization processing in the adder.
[0009]
Also, the information reproducing apparatus of the present invention comprises: a reading means for reading information from an information recording medium; an analog-digital converter for converting an analog reproduced signal read by the reading means into a digital reproduced signal; Equalizer that equalizes the digital signal converted by the equalizer into a waveform corresponding to the partial response characteristic, and a reproduction signal equalized by the waveform equalizer and an ideal amplitude value determined according to the partial response characteristic. A branch metric calculation unit that calculates a branch metric that is a multiplicative error, an addition unit that adds the branch metric calculated by the branch metric calculation unit and a past metric, and a state transition based on a result of addition by the addition unit. The comparison unit that compares the paths, and the metrics from the comparison result of this comparison unit and the addition result of the addition unit A metric register that holds the metric selected by the selection unit, and supplies the held metric to the adding unit as a past metric; and a path memory unit that holds the history of the comparison result of the comparison unit. And the past metric stored in the metric register is compared to select the minimum metric, and the minimum value of the path metric stored in the path memory unit corresponding to the selected minimum metric is selected. A minimum value selector that feeds back the minimum value of the path metric to the addition circuit.
[0010]
Further, the adder of the Viterbi decoder and the information reproducing apparatus of the present invention adds the past metric supplied from the minimum value selector to the result of addition of the branch metric calculated by the branch metric calculator and the past metric supplied from the metric register. Means for reducing 1 / N of the minimum value of the path metric is provided.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating a configuration of a signal processing unit of the optical disc device according to the present embodiment.
The signal processing unit of the optical disk device includes an optical pickup head (hereinafter, referred to as PUH) 3, a preamplifier 5, an analog-digital converter (hereinafter, referred to as an AD converter) 7, a PLL circuit 9, an offset / gain adjuster 11, a waveform. It comprises an equalizer 13 and a Viterbi decoder 15.
[0012]
Next, the operation of the signal processing unit of the optical disk device will be described.
Information recorded as marks and spaces on the optical disc medium 1 is read out as weak analog signals via the PUH 3. The weak analog signal read by the PUH 3 is amplified by the preamplifier 5 to a sufficient size. The analog reproduction signal amplified by the preamplifier 5 is converted into a digital reproduction signal by the AD converter 7. The PLL circuit 9 receives the analog reproduction signal and generates a reference clock synchronized with the phase of the analog reproduction signal. The digital conversion of the analog reproduction signal by the AD converter 7 is performed at the timing of the reference clock of the PLL circuit 9.
[0013]
The digital reproduction signal output from the AD converter 7 is subjected to offset adjustment and gain adjustment by an offset / gain adjuster 11 and supplied to a waveform equalizer 13. The digital reproduction signal supplied to the waveform equalizer 13 is equalized by the waveform equalizer 13 into a waveform corresponding to a PR (Partial Response) characteristic to be used, and is sent to the Viterbi decoder 15. The digital reproduction signal sent to the Viterbi decoder 15 is decoded into binary identification data according to the Viterbi algorithm. The identification data is sent to a subsequent circuit (not shown), and is subjected to processing such as demodulation and error correction as needed.
[0014]
Here, the waveform equalizer 13 will be described.
FIG. 2 is a diagram showing a configuration of the waveform equalizer 13.
In PRML (Partial Response and Maximum Likelihood) signal processing, an FIR (Finite Impulse Response) filter is used as the equalizer 13. The FIR filter equalizes the waveform of the digital reproduction signal using a predetermined filter coefficient and supplies the digital reproduction signal to the Viterbi decoder 18. FIG. 2 shows a configuration example of the FIR filter when the number of taps is five.
[0015]
In FIG. 2, the digital reproduction signal is sequentially supplied to four delay elements 21, and the digital reproduction signal supplied to the equalizer 13 and the output of each delay element 21 are respectively multiplied by a filter coefficient by a multiplier 23. Addition of the multiplication result of the multiplier 23 by the adder 25 equalizes the characteristic to a desired characteristic.
[0016]
Next, the Viterbi algorithm will be described.
FIG. 3 is a state transition diagram for PR (1, 1) and a diagram for explaining an ideal amplitude value in each state.
Viterbi decoding performs decoding by recursively obtaining a state transition corresponding to a predetermined PR characteristic. Since FIG. 3 shows the case of PR (1, 1), the PR-equalized signal is affected by the code one bit before. For example, when the previous code (bit) is 0 and the current code (bit) is 0, the ideal amplitude value of the signal is 0, the previous code (bit) is 0, and the current code (bit) is 1. Is 1, the previous code (bit) is 1, the current code (bit) is 0, the ideal amplitude value of the signal is 1, the previous code (bit) is 1, and the current code is 1. It is assumed that the ideal amplitude value of the signal when (bit) is 1 is 2. The transition of the code and the state at this time are shown in the state transition diagram. In the case of PR (1, 1), the number of states is four.
[0017]
Next, an example of a reproduced signal and decoded data will be described.
FIG. 4 is a diagram for explaining an example of a reproduced signal and decoded data.
The Viterbi decoding calculates a square error between a signal amplitude (Yt) and an ideal level at a certain time (t) (branch metric calculation), integrates the square error (path metric calculation), and determines the most reliable based on the state transition. A suitable code sequence is selected (path memory and minimum value selection). The definition formula of the branch metric (BM) value and the path metric (PM) value in the case of PR (1, 1) is shown below.
[0018]
BM (t, 0) = (Yt-0) ²
BM (t, 1) = (Yt-1) ²
BM (t, 2) = (Yt-2) ²
PM (t, 0) = min {PM (t-1,0) + BM (t, 0), PM (t-1,1) + BM (t, 1)}
PM (t, 1) = min {PM (t-1,0) + BM (t, 1), PM (t-1,1) + BM (t, 2)}
Next, the Viterbi decoder 15 will be described.
FIG. 5 is a block diagram showing the configuration of the Viterbi decoder 15.
The Viterbi decoder 15 includes a branch metric calculation unit (hereinafter referred to as a BM calculation unit) 51, an addition unit 53, a metric register 55, a minimum value selection unit 57 serving as a maximum likelihood determination unit, a comparison unit 59, a selection unit 61, a path memory. It is composed of a unit 63.
[0019]
Next, the operation of the Viterbi decoder 15 will be described.
The reproduced signal equalized to a desired PR characteristic by the waveform equalizer 13 is input to the BM calculator 51. The BM calculator 51 calculates a square error between a plurality of ideal amplitude values determined according to the PR characteristics and the input signal. Each calculated square error is input to the adding unit 53 as a branch metric value (hereinafter, referred to as a BM value).
[0020]
A past metric (hereinafter, referred to as a P metric) is input from the metric register 55 to the addition unit 53. Further, the minimum value of the P metric is input to the addition unit 53 from the minimum value selection unit 57. The adder 53 performs the addition of the BM value and the P metric and normalization processing for preventing overflow using the minimum value of the P metric, and then inputs the current metric value to the comparator 59 and the selector 61. . The comparing unit 59 compares the paths based on the state transition, and supplies the comparison result to the path memory unit 63 and the selecting unit 61. The selection unit 61 selects a metric value using the output from the comparison unit 59. The metric value selected by the selector 61 is output as a P metric to the adder 53 via the metric register 55 and is also supplied to the minimum value selector 57 via the metric register 55.
[0021]
The path memory unit 63 holds and updates the comparison result as far back as the number of path memory stages prepared in advance. The last stage memory value is supplied from the path memory unit 63 to the minimum value selection unit 57. The minimum value selector 57 selects the minimum metric value by comparing the metric values supplied from the selector 61 via the metric register 55, and selects the output from the path memory unit 63 corresponding to the minimum metric value. I do. This output is the decoding result.
[0022]
Next, a normalization process for preventing metric overflow in the addition unit 53 of FIG. 5 will be described.
FIG. 6 is a diagram for explaining a circuit configuration of the adding unit 53.
FIG. 6 shows a circuit configuration of the adder 53 when performing six-state Viterbi decoding in which the run length is limited to one or more. The run length is limited to one or more when the same code bit is continuous at least two or more times. For example, there is no code such as 010 or 101 where the same code is not continuous at all. The 6 states are examples in which the PR characteristic is PR (A, B, B, A) and the run length limit is 1.
[0023]
The BM value in each branch calculated by the BM calculation unit 51 is input to the addition unit 53 as BM0 to BM9. In FIG. 6, BM0 is provided at a terminal 61 of the adder 53, BM1 is provided at a terminal 62, BM2 is provided at a terminal 63, BM3 is provided at a terminal 64, BM4 is provided at a terminal 65, BM5 is provided at a terminal 66, and BM6 is provided at a terminal 67. BM7 is input to the terminal 68, BM8 of the terminal 69 is input to the terminal 72, and BM9 is input to the terminal 72.
[0024]
The BM values BM0 to BM9 input to the adder 53 are added to the P metric supplied from the metric register 55, and a process for metric normalization is performed in a preceding stage.
[0025]
That is, the P metric supplied from the metric register 55 is supplied to the terminal 70 of the adder 53 and is divided by the demultiplexer 81 into M0 to M7. The minimum value of the P metric output from the minimum value selection unit 57 is input to the terminal 71 of the adder 53. The minimum value of the P metric supplied to the terminal 71 is supplied to the 1 / N gain unit 85 via the delay element 83. The minimum value of the P metric is multiplied by 1 / N in a 1 / N gain unit 85 and supplied to ten adder / subtractors 91 to 100, respectively.
[0026]
A constant is supplied to each of the ten adder / subtractors 91 to 100, the adder / subtractor 91 receives the BM value BM0 from the terminal 61, the adder / subtractor 92 receives the BM value BM1 from the terminal 62, and the adder / subtractor. 93, the BM value BM2 from the terminal 63, the adder / subtractor 94, the BM value BM3 from the terminal 64, the adder / subtractor 95, the BM value BM4 from the terminal 65, and the adder / subtractor 96, the BM value from the terminal 66. The value BM5, the adder / subtractor 97 receives the BM value BM6 from the terminal 67, the adder / subtractor 98 receives the BM value BM7 from the terminal 68, the adder / subtractor 99 receives the BM value BM8 from the terminal 69, and the adder / subtractor 100. Is supplied with the BM value BM9 from the terminal 72.
[0027]
The adder / subtractor 91 adds a constant to the supplied BM0 and subtracts the output from the 1 / N gain unit 85. Similarly, in the adder / subtractor 92, a constant is added to BM1 and the output of the 1 / N gain unit 85 is subtracted, and in the adder / subtractor 93, a constant is added to BM2 and the output of the 1 / N gain unit 85 is subtracted and added / subtracted. The adder 94 adds a constant to BM3 and subtracts the output of the 1 / N gain unit 85. The adder / subtractor 95 adds a constant to BM4 and subtracts the output of the 1 / N gain unit 85. The adder / subtractor 96 adds BM5. , And the output of the 1 / N gain unit 85 is subtracted. The adder / subtractor 97 adds the constant to the BM6, the output of the 1 / N gain unit 85 is subtracted, and the adder / subtractor 98 adds the constant to the BM7. At the same time, the output of the 1 / N gain unit 85 is subtracted, a constant is added to the BM 8 in the adder / subtractor 99, the output of the 1 / N gain unit 85 is subtracted, and a constant is added to the BM 9 in the adder / subtractor 100. The output of the 1 / N gain device 85 is subtracted with the.
[0028]
The output of the adder / subtractor 91 is supplied to the adder 111 via the delay element 101. Similarly, the output of the adder / subtractor 92 is added to the adder 112 via the delay element 102, the output of the adder / subtractor 93 is added to the adder 113 via the delay element 103, and the output of the adder / subtractor 94 is added via the delay element 104. The output of the adder / subtractor 95 is supplied to the adder 115 via the delay element 105, the output of the adder / subtractor 96 is supplied to the adder 116 via the delay element 106, and the output of the adder / subtractor 97 is supplied via the delay element 107. The output of the adder 117, the output of the adder / subtractor 98 is supplied to the adder 118 via the delay element 108, the output of the adder / subtractor 99 is supplied to the adder 119 via the delay element 109, and the output of the adder / subtractor 100 is supplied via the delay element 110. And supplied to the adder 120.
[0029]
The output from the delay element 101 is supplied to the adder 111, and the P metric M0 supplied from the metric register 55 is supplied from the demultiplexer 81 via the terminal 70 to the adder 111, and the adder 111 adds the output of the delay element 101 and M0. Is performed. Similarly, the output of the delay element 106 and M7 are supplied to the adder 112 for addition processing, the output of the delay element 102 and M0 are supplied to the adder 113, and the addition processing is performed. The output of the delay element 103 and the output of M6 are supplied to the adder 116 for addition processing. The output of the delay element 103 and the output of M6 are supplied to the adder 116 for addition processing. The output of the delay element 104 and M3 are supplied to the adder 117 for addition processing, the output of the delay element 109 and M7 are supplied to the adder 118 for addition processing, and the adder 119 is supplied with the delay element. The output of 105 and M3 are supplied to perform an addition process, and the adder 120 is supplied with the output of the delay element 110 and M7 to perform an addition process. The addition result of each of the adders 111 to 120 is supplied to the multiplexer 87 and output from the adder 53 to the comparator 59 and the selection unit 61.
[0030]
As described above, the BM values BM0 to BM9 are each subtracted by 1 / N of the minimum value of the P metric output from the minimum value selection unit 57, and a predetermined constant C is added to perform the normalization processing. By doing so, the upper limit value and the lower limit value of the value output from the multiplexer 87 are limited, and it is possible to avoid overflow of the output value obtained by adding the P metric.
[0031]
Note that N depends on the constant value to be added, but it is desirable to substitute 1/2 or 1/4 bit shift for a simple configuration of the adder 53.
[0032]
【The invention's effect】
According to the present invention, the metric overflow can be prevented with a simple configuration by using the minimum value of the path metric in the adding unit of the Viterbi decoder.
[Brief description of the drawings]
FIG. 1 is an exemplary block diagram illustrating a configuration of a signal processing unit of an optical disc device according to an embodiment.
FIG. 2 is a diagram showing a configuration of an equalizer.
FIG. 3 is a state transition diagram in the case of PR (1, 1) and a diagram for explaining an ideal amplitude value in each state.
FIG. 4 is a diagram illustrating an example of a reproduced signal and decoded data.
FIG. 5 is a block diagram showing a configuration of a Viterbi decoder 15;
FIG. 6 is a diagram illustrating a circuit configuration of an adding unit 53.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 optical disk 3 optical pickup head 5 preamplifier 7 analog-to-digital converter 9 PLL circuit 11 offset / gain adjuster 13 waveform equalizer 15 Viterbi decoder 51 branch metric calculator 53 adder 55 metric register 57 minimum value selector 59 comparison Unit 61 selection unit 63 path memory unit 85 1 / N gain unit

Claims (8)

A branch metric calculation unit that calculates a branch metric that is a square error between an ideal amplitude value determined according to the partial response characteristic and an input signal;
An adder that adds the branch metric calculated by the branch metric calculator and the past metric;
A comparing unit that compares paths based on the state transition from the addition result of the adding unit;
A selection unit for selecting a metric from the comparison result of the comparison unit and the addition result of the addition unit;
A metric register that holds the metric selected by the selection unit and supplies the held metric as the past metric to the addition unit;
A path memory unit that holds a history of comparison results of the comparison unit,
The smallest metric is selected by comparing the past metrics held in the metric register, and the minimum value of the path metric held in the path memory unit corresponding to the selected minimum metric is selected. A minimum value selector for feeding back the minimum value of the past path metric to the addition circuit. The adding unit may add, to the result of adding the branch metric calculated by the branch metric calculating unit and the past metric supplied from the metric register, 1/1 / min of the minimum value of the past path metric supplied from the minimum value selecting unit. 2. The Viterbi decoder according to claim 1, further comprising means for reducing N. The adding unit may add, to the result of adding the branch metric calculated by the branch metric calculating unit and the past metric supplied from the metric register, 1/1 / min of the minimum value of the past path metric supplied from the minimum value selecting unit. 2. The Viterbi decoder according to claim 1, further comprising means for subtracting N and adding a predetermined constant. The adding unit may add, to the result of adding the branch metric calculated by the branch metric calculating unit and the past metric supplied from the metric register, 1/1 / min of the minimum value of the past path metric supplied from the minimum value selecting unit. 2. The Viterbi decoder according to claim 1, further comprising means for subtracting 2. The adding unit may add, to the result of adding the branch metric calculated by the branch metric calculating unit and the past metric supplied from the metric register, 1/1 / min of the minimum value of the past path metric supplied from the minimum value selecting unit. 2. The Viterbi decoder according to claim 1, further comprising means for reducing the number of bits. Reading means for reading information from the information recording medium;
An analog-to-digital converter for converting an analog reproduction signal read by the reading means into a digital reproduction signal;
A waveform equalizer that equalizes a digital signal converted by the analog-to-digital converter into a waveform corresponding to a partial response characteristic;
A branch metric calculation unit that calculates a branch metric that is a square error between the reproduced signal equalized by the waveform equalizer and an ideal amplitude value determined according to a partial response characteristic;
An adder that adds the branch metric calculated by the branch metric calculator and the past metric;
A comparing unit that compares paths based on the state transition from the addition result of the adding unit;
A selection unit for selecting a metric from the comparison result of the comparison unit and the addition result of the addition unit;
A metric register that holds the metric selected by the selection unit and supplies the held metric as the past metric to the addition unit;
A path memory unit that holds a history of comparison results of the comparison unit,
The smallest metric is selected by comparing the past metrics held in the metric register, and the minimum value of the path metric held in the path memory unit corresponding to the selected minimum metric is selected. An information reproducing apparatus comprising: a minimum value selector that feeds back the minimum value of the path metric to the addition circuit. The adding unit may add, to the result of adding the branch metric calculated by the branch metric calculating unit and the past metric supplied from the metric register, 1/1 / min of the minimum value of the past path metric supplied from the minimum value selecting unit. 7. The information reproducing apparatus according to claim 6, further comprising means for reducing N. 8. The information reproducing apparatus according to claim 6, wherein said reading means reads information from an optical disk.

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