JP2004258473A - Plasma display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost of a plasma display apparatus by attaching a drive circuit block with simple structure. <P>SOLUTION: At least two through-holes 47a are provided in a heat radiation plate 47 attached to a chassis member 34 of an address driver circuit block 39 supplying signals to a plasma display panel. The chassis member 34 is provided with a positioning boss part 51 having a positioning pin 51a inserted into the one through-hole 47a of the block 39, and an attaching boss part 53 for pressing to fix the heat radiation plate 47 by screwing a screw 52 through the other through-hole 47a of the address driver circuit block 39, and the positioning boss part 51 is set higher than the attaching boss part 53. Thus, the address driver circuit block 39 can be firmly attached to the chassis member 34 with a single screw 52. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a plasma display device known as a large-screen, thin, and lightweight display device.
[0002]
[Prior art]
Plasma display devices can display at higher speeds than liquid crystal panels, have a wider viewing angle, are easier to increase in size, and have higher display quality due to their self-luminous type. It has recently received particular attention in technology.
[0003]
First, the structure of the plasma display panel in the plasma display device will be described with reference to FIG. As shown in FIG. 9, on a transparent front substrate 1 such as a glass substrate, a plurality of stripe-shaped display electrodes 2 forming pairs of scan electrodes and sustain electrodes are formed, and cover the electrode group. A dielectric layer 3 is formed as described above, and a protective film 4 is formed on the dielectric layer 3.
[0004]
A plurality of rows of stripes covered with an overcoat layer 6 are provided on a rear substrate 5 opposed to the front substrate 1 so as to cross the display electrodes 2 of scan electrodes and sustain electrodes. Address electrodes 7 are formed. A plurality of partitions 8 are arranged on the overcoat layer 6 between the address electrodes 7 in parallel with the address electrodes 7, and the phosphor layers 9 are provided on the side surfaces between the partitions 8 and on the surface of the overcoat layer 6. I have.
[0005]
The substrate 1 and the substrate 5 are opposed to each other with a minute discharge space therebetween so that the display electrode 2 of the scan electrode and the sustain electrode and the address electrode 7 are substantially orthogonal to each other, and the periphery thereof is sealed. In the discharge space, one or a mixed gas of helium, neon, argon, and xenon is sealed as a discharge gas. The discharge space is divided into a plurality of sections by partition walls 8, so that a plurality of discharge cells are provided at intersections between the display electrodes 2 and the address electrodes 7, and each of the discharge cells has a red, green, and blue color. The phosphor layers 9 are sequentially arranged for each color such that
[0006]
FIG. 10 shows an electrode arrangement of this plasma display panel. As shown in FIG. 10, the scan electrodes, the sustain electrodes, and the address electrodes have a matrix configuration of M rows × N columns, and M rows × N columns are arranged in the row direction. Scan electrodes SCN1 to SCNM and sustain electrodes SUS1 to SUSM are arranged, and N columns of address electrodes D1 to DN are arranged in the column direction.
[0007]
In the plasma display panel having such an electrode configuration, an address discharge is performed between the address electrode and the scan electrode by applying a write pulse between the address electrode and the scan electrode, and after selecting a discharge cell, the scan electrode A sustain discharge is performed between the scan electrode and the sustain electrode by applying a periodic sustain pulse that is alternately inverted between the scan electrode and the sustain electrode, thereby performing a predetermined display.
[0008]
FIG. 11 shows a configuration of a display drive circuit of a plasma display device. As shown in FIG. 11, a plasma display panel (PDP) 10, an address driver circuit 11, a scan driver circuit 12, a sustain driver circuit 13, a discharge control timing generation circuit 14, power supply circuits 15, 16, A having the configuration shown in FIG. A / D converter (analog / digital converter) 17, a scan number converter 18, and a subfield converter 19 are provided.
[0009]
In the circuit of FIG. 11, first, the video signal VD is input to the A / D converter 17. The horizontal synchronizing signal H and the vertical synchronizing signal V are supplied to a discharge control timing generation circuit 14, an A / D converter 17, a scan number converter 18, and a subfield converter 19. The A / D converter 17 converts the video signal VD into a digital signal, and provides the image data to the scan number converter 18.
[0010]
The scanning number conversion unit 18 converts the image data into image data of the number of lines corresponding to the number of pixels of the PDP 10 and supplies the image data of each line to the subfield conversion unit 19. The subfield conversion unit 19 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and serializes each bit of the pixel data for each subfield to the address driver circuit 11. Output to The address driver circuit 11 is connected to the power supply circuit 15, converts data serially provided for each subfield from the subfield conversion unit 19 into parallel data, and applies a voltage to a plurality of address electrodes based on the parallel data. Supply.
[0011]
The discharge control timing generation circuit 14 generates discharge control timing signals SC and SU with reference to the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the scan driver circuit 12 and the sustain driver circuit 13, respectively. The scan driver circuit 12 has an output circuit 121 and a shift register 122. The sustain driver circuit 13 has an output circuit 131 and a shift register 132. These scan driver circuit 12 and sustain driver circuit 13 are connected to a common power supply circuit 16.
[0012]
The shift register 122 of the scan driver circuit 12 supplies the discharge control timing signal SC supplied from the discharge control timing generation circuit 14 to the output circuit 121 while shifting in the vertical scanning direction. The output circuit 121 sequentially supplies a drive signal voltage to the plurality of scan electrodes in response to a discharge control timing signal SC provided from the shift register 122.
[0013]
The shift register 132 of the sustain driver circuit 13 supplies the discharge control timing signal SU supplied from the discharge control timing generation circuit 14 to the output circuit 131 while shifting in the vertical scanning direction. The output circuit 131 sequentially supplies a drive signal voltage to the plurality of sustain electrodes in response to the discharge control timing signal SU given from the shift register 132.
[0014]
By the way, in the plasma display device having such a configuration, a driver IC for supplying display data to the address electrodes of the PDP and a driver IC for supplying display data to the address electrodes of the PDP are provided in an address driver circuit block portion for supplying display data to the address electrodes of the PDP. A flexible wiring board for mounting the PDP and the drive circuit portion and connecting the driver IC is used. Further, an output wiring for connecting an output terminal of the driver IC and an address electrode of the PDP and an input wiring for connecting to an input terminal of the driver IC are formed on the flexible wiring board. Each of the electrode lead portions of the plurality of address electrodes of the display panel is electrically connected via an anisotropic conductive adhesive or the like, and one end of an input wiring is electrically connected to a drive circuit unit (for example, see Patent Document 1). 1).
[0015]
[Patent Document 1]
JP-A-11-194718
[Problems to be solved by the invention]
In the plasma display device having such a configuration, a plurality of address driver circuit blocks are required according to the number of pixels of the PDP. When these address driver circuit blocks are attached to a chassis member of the plasma display device, FIG. As shown in FIG. 13, the metal plate 20a of the address driver circuit block 20 is fixed to the chassis member 21 with two screws 22. Therefore, many screws are used for mounting the address driver circuit block. However, there is a problem that the mounting work is troublesome. The address driver circuit block 20 has a metal plate 20a for holding a driver IC chip and a flexible wiring board 20b.
[0017]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the cost of a plasma display device by enabling mounting of a drive circuit block such as an address driver circuit block with a simple structure. Is what you do.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, a plasma display device according to the present invention is characterized in that at least two through-holes are provided in a holding plate attached to a chassis member of a drive circuit block for supplying a signal to a PDP, and the drive circuit block is provided in the chassis member. A positioning boss having a positioning pin inserted into one of the through holes; and a mounting boss for pressing and fixing the holding plate by screwing a mounting screw through the other through hole of the drive circuit block. And the height of the positioning boss is higher than the height of the mounting boss.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
That is, the invention according to claim 1 of the present invention provides a PDP having a plurality of discharge cells formed by forming a discharge space and providing electrodes on a pair of opposed substrates, and disposing the PDP on the front side. And a drive circuit block disposed on the back side of the chassis member and supplying a signal to the PDP. At least two through holes are formed in a holding plate attached to the chassis member of the drive circuit block. By providing a positioning boss having a positioning pin inserted into one through hole of the drive circuit block in the chassis member, and screwing a mounting screw through the other through hole of the drive circuit block. And a mounting boss for pressing and holding the holding plate, wherein the height of the positioning boss is higher than the height of the mounting boss.
[0020]
According to a second aspect of the present invention, in the first aspect, the drive circuit block has a wiring board connected to the electrodes of the plasma display panel and a driver IC for supplying a signal to the electrodes; It is characterized by comprising a holding plate attached to the chassis member at a portion where the driver IC is arranged.
[0021]
Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8 taking an address driver circuit block as an example, but embodiments of the present invention are not limited thereto. .
[0022]
FIG. 1 shows an example of the overall configuration of a plasma display device. In the figure, reference numeral 30 denotes a PDP having the configuration shown in FIG. 5, and a housing for accommodating the PDP 30 is composed of a front frame 31 and a metal back cover 32. A front cover 33 made of glass or the like also protecting the PDP 30 is provided. The front cover 33 is coated with, for example, silver to suppress unnecessary radiation of electromagnetic waves. Further, the back cover 32 is provided with a plurality of ventilation holes 32a for releasing heat generated in the PDP 30 and the like to the outside.
[0023]
The PDP 30 is held by being bonded to the front surface of a chassis member 34 made of aluminum or the like via a heat conductive sheet 35, and a plurality of drive circuit blocks for driving the PDP 30 for display are provided on the rear surface side of the chassis member 34. 36 are attached. The heat conductive sheet 35 is for efficiently transmitting the heat generated in the PDP 30 to the chassis member 34 and dissipating the heat. The drive circuit block 36 includes an electric circuit for driving the display of the PDP 30 and controlling the display, and extends beyond the four edges of the chassis member 34 to the electrode extraction portion extended to the edge of the PDP 30. They are electrically connected by a plurality of flexible wiring boards (not shown).
[0024]
A boss 34a for attaching the drive circuit block 36 and fixing the back cover 32 is formed on the rear surface of the chassis member 34 by integral molding such as die casting. The chassis member 34 may be configured by fixing a fixing pin to an aluminum flat plate.
[0025]
FIG. 2 is a plan view showing an arrangement structure of internal drive circuit blocks in the plasma display device having such a configuration with the back cover 32 removed, and FIG. 2 shows a scan driver circuit block 37 which is one of the drive circuit blocks. Supplies a predetermined signal voltage to a scan electrode of the PDP 30, a sustain driver circuit block 38 supplies a predetermined signal voltage to a sustain electrode of the PDP 30, and an address driver circuit block 39 supplies a predetermined signal voltage to an address electrode of the PDP 30. The scan driver circuit block 37 and the sustain driver circuit block 38 are disposed at both ends in the width direction of the chassis member 34, and the address driver circuit block 39 is disposed at the lower end in the height direction of the chassis member 34. ing.
[0026]
The control circuit block 40, which is one of the drive circuit blocks, transmits a signal from an input signal circuit block 41 having an input terminal section to which a connection cable for connecting to an external device such as a television tuner is detachably connected. The image data is converted into an image data signal corresponding to the number of pixels of the PDP 30 and supplied to the address driver circuit block 39 based on the received video signal, and a discharge control timing signal is generated. The scan driver circuit block 37 and the sustain driver It is supplied to the circuit block 38 and performs display drive control such as gradation control, and is arranged at a substantially central portion of the chassis member 34. The power supply block 42 supplies a voltage to each of the circuit blocks. Like the control circuit block 40, the power supply block 42 is disposed substantially at the center of the chassis member 34, and includes a connector 43a to which a power supply cable (not shown) is attached. A commercial power supply voltage is supplied through a power supply input block 43 having the same.
[0027]
The flexible wiring board 44 connects the lead-out portions of the scan electrodes and the sustain electrodes of the PDP 30 to the printed wiring boards of the scan driver circuit block 37 and the sustain driver circuit block 38. It is arranged by being bent 180 degrees further to the back side and routed.
[0028]
The detailed configuration of the address driver circuit block 39 is shown in FIGS. In the drawing, reference numeral 45 denotes a driver IC constituting an address driver circuit. The driver IC 45 supplies display data to the address electrodes of the PDP 30, and a plurality of driver ICs 45 are connected to the PDP 30. Reference numeral 46 denotes a flexible wiring board having a flexible property on which the driver IC 45 is mounted. The flexible wiring board 46 is connected to the address electrodes and the driver IC on an insulating base film 46a made of a resin material such as polyimide. A plurality of wiring conductors 46b made of Cu, and a resin protective film 46c formed on a surface of the flexible wiring board 46 on which the driver IC 45 is mounted so as to cover the wiring conductors 46b. I have. In the wiring conductor 46b of the flexible wiring board 46, the surface of the terminal portion electrically connected to the terminal portion of the driver IC 45 by wire bond mounting, flip chip mounting, or the like is plated with Ni, Au, or the like. In the example shown in the figure, an example of wire bond mounting is shown, and 45a is a connection wire for that. The resin protective film 46c is formed by applying a resin such as a transparent or translucent material such as an epoxy resin, a urethane resin, and a polyimide resin by a printing method, a photolithography method, and curing the resin, and has a thickness of 10 μm to It is about 50 μm.
[0029]
On the surface of the flexible wiring board 46 opposite to the surface on which the driver IC 45 is mounted, a metal heat radiating plate 47 such as an aluminum plate as a holding plate is provided by bonding with a bonding layer 48. The heat radiating plate 47 is attached to the chassis member 34 to which the PDP 30 is fixed by screws or the like, thereby forming a heat radiating path for radiating heat generated from the driver IC 45. Reference numeral 49 denotes a mold resin made of epoxy resin or the like that covers the driver IC 45 mounted on the flexible wiring board 46 so as to cover the driver IC 45, the connection between the driver IC 45 and the wiring conductor 46b, and the end of the resin protection film 46c. Is formed.
[0030]
As shown in FIG. 4, one end of the wiring conductor 46b of the flexible wiring board 46 is electrically connected to the terminal portion of the address electrode of the PDP 30 by an anisotropic conductive adhesive, and is passed through the outer peripheral portion of the PDP 30 from the front side. The wiring conductor 46b of the flexible wiring board 46 is electrically connected to a drive circuit board 50 attached to the chassis member 34 on the back side of the PDP 30.
[0031]
5 to 8 are views showing a mounting structure of the address driver circuit block 39. As shown in FIG. 5, the heat dissipation plate 47 attached to the chassis member 34 of the address driver circuit block 39 is provided with a through hole 47a. Although the figure shows an example in which two through holes 47a are provided, three or four holes may be used as long as the number is two or more.
[0032]
On the other hand, as shown in FIG. 6, the chassis member 34 includes a positioning boss 51 having a positioning pin 51a inserted into one through hole 47a of the address driver circuit block 39, A mounting boss portion 53 is provided for fixing the radiating plate 47 by pressing the radiating plate 47 by screwing the mounting screw 52 through the other through hole 47a. Further, as shown in FIG. 7, the positioning boss 51 and the mounting boss 53 are provided with a step by making the height of the positioning boss 51 higher than the height of the mounting boss 53. ing. As a result, when the heat radiating plate 47 of the address driver circuit block 39 is attached to the chassis member 34, the positioning pins 51a are engaged with the inner wall surfaces of the through holes 47a of the heat radiating plate 47 as shown in FIG. In a state where the radiating plate 47 of the address driver circuit block 39 is urged toward the mounting boss 53 by the screw 52 while being urged toward the mounting boss 53 with the portion 51 as a fulcrum, the address driver is mounted. The circuit block 39 is firmly attached to the chassis member 34 with one screw 52 without rattling.
[0033]
That is, according to the present embodiment, when attaching the address driver circuit block 39 to the chassis member 34, the one through hole 47 a of the heat sink 47 of the address driver circuit block 39 is inserted into the positioning pin 51 a of the positioning boss 51. The screw 52 may be screwed into the mounting boss 53 by passing through the other through hole 47a, and can be easily mounted with only one screw. The number of screws can be reduced, and the number of screw tightening steps can be reduced, which can contribute to the cost reduction of the plasma display device. Further, by making the through-hole 47a long, fine adjustment of the mounting position is also possible.
[0034]
Of course, such a configuration can be applied to a drive circuit block other than the address driver circuit block.
[0035]
【The invention's effect】
As described above, according to the present invention, the number of screws for mounting the drive circuit block can be reduced, and the number of mounting steps can be reduced, and the cost of the plasma display device can be reduced with a simple configuration. Can make a significant contribution.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view showing an internal arrangement structure of a plasma display device according to an embodiment of the present invention; FIG. 2 is a plan view showing an internal arrangement structure of the plasma display device; FIG. FIG. 4 is a cross-sectional view showing a configuration of an address driver circuit block portion of FIG. 4; FIG. 5 is a cross-sectional view showing a mounting structure of an address driver circuit block; FIG. FIG. 7 is a side view showing a structure of a chassis member of a portion to which is mounted. FIG. 8 is a side view showing a mounting structure of an address driver circuit block. FIG. 9 is a schematic configuration of a panel of a general plasma display device. FIG. 10 is an explanatory view showing an electrode arrangement of a panel of the plasma display device. 11 is a perspective view [13] Also a side view showing a mounting structure of the address driver circuit block of the block circuit diagram Figure 12 conventional plasma display apparatus according to an example of the display driving circuit of the plasma display device [Description of symbols]
30 PDP
34 Chassis member 39 Address driver circuit block 47 Heat sink 47a Through hole 51 Positioning boss 51a Positioning pin 52 Screw 53 Mounting boss

Claims (2)

A plasma display panel having a plurality of discharge cells formed by forming electrodes on a pair of substrates facing each other to form a discharge space, a chassis member on which the plasma display panel is arranged on the front side, and a chassis member And a drive circuit block for supplying a signal to the plasma display panel, the drive plate being provided on the back side thereof with at least two through holes in a holding plate attached to a chassis member of the drive circuit block, and A holding plate is pressed and fixed by screwing a mounting boss having a positioning pin inserted into one through hole of the drive circuit block and a mounting screw through the other through hole of the drive circuit block. A mounting boss is provided, and the height of the positioning boss is higher than the height of the mounting boss. A plasma display apparatus, characterized in that the. The drive circuit block has a wiring board connected to the electrodes of the plasma display panel and a driver IC for supplying a signal to the electrodes, and is mounted on the chassis member at a portion where the driver IC is arranged. The plasma display device according to claim 1, wherein the plasma display device is configured by including a plate.

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