JP2004253073A - Semiconductor device and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing through current flowing in an inside circuit at the return from a power-down mode. <P>SOLUTION: The semiconductor device 11 comprises a mode control circuit 3, an inside power source generation circuit 4 and an inside timer 12. The mode control circuit 3 generates a power-down mode signal INTDPD1. The inside power source generation circuit 4 generates inside power source voltage VINT on the basis of outside power source voltage VEXT, and the inside power source voltage VINT is supplied to an inside circuit 5. The inside timer 12 measures an elapsed time after switching off the power-down mode signal INTDPD1 to generate a mode extension signal INTDPD2 extending an on-period of the power-down mode signal INTDPD1 up to only a prescribed time. The mode extension signal INTDPD2 is input to a level shift circuit 7 to deactivate the circuit. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device provided with an internal power supply generation circuit, which stops generation of an internal power supply voltage in the internal power supply generation circuit in a power down mode.
[0002]
An internal power supply generation circuit mounted on a semiconductor device (LSI) generates an internal power supply voltage different from the external power supply voltage based on the supply of the external power supply, and supplies the generated internal power supply voltage to the internal circuit. 2. Description of the Related Art In a semiconductor device used for a portable device or the like that operates on a battery, a reduction in current consumption during standby is required, and a device having a power-down function of deactivating an internal power supply generation circuit has been put to practical use.
[0003]
[Prior art]
2. Description of the Related Art Conventionally, as a specific method of reducing current in a semiconductor device, a method of deactivating an internal power supply circuit during standby and setting an internal power supply voltage, which is an output voltage of the internal power supply circuit, to a voltage lower than an external power supply voltage Also, a method of interrupting a power supply path to which an external power supply voltage is supplied is known (for example, see Patent Documents 1 and 2).
[0004]
The tailing current flows through the internal power supply generation circuit and the semiconductor transistors forming the internal circuit due to the sub-threshold characteristic. However, the tailing current is reduced by the above-described method, and the current consumption in the standby state of the semiconductor device is extremely small. Is done. At this time, the internal circuit to which the internal power supply voltage is supplied is in an operation stopped state or in a state where operation cannot be guaranteed. In this specification, an operation mode in which the current consumption of a semiconductor device is minimized is referred to as a deep power down mode (DPD mode).
[0005]
Hereinafter, a circuit configuration for shifting from the normal mode to the DPD mode in the conventional semiconductor device will be described. FIG. 12 shows a block circuit diagram of a conventional semiconductor device (specifically, synchronous DRAM: SDRAM) 1.
[0006]
The semiconductor device 1 includes an input circuit 2, a mode control circuit 3, an internal power generation circuit 4, and an internal circuit 5.
The input circuit 2 receives the clock signal CLK and various control signals (clock enable signal CKE, chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE). The output signal of the input circuit 2 is input to the mode control circuit 3.
[0007]
The mode control circuit 3 recognizes various commands requested from outside the device based on a combination of the logic levels of the control signals CKE, / CS, / RAS, / CAS, and / WE, and internally stores a mode signal corresponding to the command. Output to the power generation circuit 4 and the internal circuit 5. The mode signal includes a DPD mode mode signal (power down mode signal) INTDPD 1, and the power down mode signal INTDPD 1 is input to the internal power supply generation circuit 4.
[0008]
In the semiconductor device 1, when the power down mode signal INTDPD1 is at the L level, the internal power supply generation circuit 4 is activated, and based on the external power supply voltage VEXT (for example, 3.3 V) supplied from outside the device, the internal circuit 5 is activated. , An internal power supply voltage VINT (for example, 2.0 V) is generated. When power down mode signal INTDPD1 is at H level, internal power supply generating circuit 4 is inactivated, and the operation of generating internal power supply voltage VINT is stopped.
[0009]
FIG. 13 shows the level shift circuit 7 provided in the internal circuit 5. The level shift circuit 7 shifts the level of an input signal AINT that swings at the voltage level of the internal power supply voltage VINT to an output signal AEXT that swings at the voltage level of the external power supply voltage VEXT, and outputs the output signal AEXT.
[0010]
More specifically, the level shift circuit 7 includes a NOR circuit 8 and a plurality of NMOS transistors Tn1, Tn2, Tn3 and PMOS transistors Tp1, Tp2, Tp3, Tp4. In the level shift circuit 7, the PMOS transistors Tp1 and Tp2 and the NMOS transistor Tn1 are connected in series, and the PMOS transistors Tp3 and Tp4 and the NMOS transistor Tn2 are connected in series.
[0011]
The external power supply voltage VEXT is supplied to the source of the PMOS transistor Tp1, and the gate of the transistor Tp1 is connected to the connection between the PMOS transistor Tp4 and the NMOS transistor Tn2. The external power supply voltage VEXT is supplied to the source of the PMOS transistor Tp3, and the gate of the transistor Tp3 is connected to the connection between the PMOS transistor Tp2 and the NMOS transistor Tn1.
[0012]
The sources of the NMOS transistors Tn1 and Tn2 are grounded. The drain of the NMOS transistor Tn3 is connected to the connection between the PMOS transistor Tp2 and the NMOS transistor Tn1, and the source of the transistor Tn3 is connected to the ground.
[0013]
The input signal AINT is input to the gates of the PMOS transistor Tp2 and the NMOS transistor Tn1, and the mode extension signal INTDPD2 is input to the gate of the NMOS transistor Tn3. The mode extension signal INTDPD2 is a signal generated based on the power-down mode signal INTDPD1, and is a signal obtained by extending the on-period (the H-level period) of the power-down mode signal INTDPD1 by a predetermined time.
[0014]
The mode extension signal INTDPD2 is input to a first input terminal of the NOR circuit 8, and an input signal AINT is input to a second input terminal of the NOR circuit 8. The output signal of the NOR circuit 8 is input to the gates of the PMOS transistor Tp4 and the NMOS transistor Tn2. The potential level at the connection between the PMOS transistor Tp4 and the NMOS transistor Tn2 is output as the output signal AEXT.
[0015]
During the period when the power down mode signal INTDPD1 is at the H level (the period when the operation mode is the DPD mode), the operation of generating the internal power supply voltage VINT in the internal power supply generation circuit 4 is stopped. Therefore, the voltage level of the input signal AINT of the level shift circuit 7 may be undefined.
[0016]
When the input signal AINT of the level shift circuit 7 becomes unstable, the NMOS transistor Tn3 is turned on based on the H-level mode extension signal INTDPD2, and the output signal of the NOR circuit 8 is set to L level. In this case, since the level shift circuit 7 is inactivated, an abnormal current (through current) flowing through the level shift circuit 7 is prevented.
[0017]
Incidentally, when there is no deep power down function and the internal power supply generation circuit 4 is always activated, the voltage level of the input signal AINT does not become unstable. As a level shift circuit used in this case, the NMOS transistor Tn3 is omitted from the level shift circuit 7 of FIG. 13, and an inverter circuit is provided instead of the NOR circuit 8. Further, the input of the mode extension signal INTDPD2 is also omitted. In the level shift circuit, when the input signal AINT becomes unstable, a through current flows through the transistors Tp1, Tp2, and Tn1.
[0018]
On the other hand, in the level shift circuit 7 of FIG. 13, when the input signal AINT is undefined, the NMOS transistor Tn3 is turned on and the PMOS transistor Tp3 is turned on based on the H-level mode extension signal INTDPD2. The output signal of the NOR circuit 8 turns on the PMOS transistor Tp4 and turns off the NMOS transistor Tn2. As a result, the output signal AEXT of the level shift circuit 7 is fixed at the H level. At this time, since the PMOS transistor Tp1 is turned off, a through current is prevented from flowing even when the input signal AINT is undefined.
[0019]
FIG. 14 shows a signal generation circuit 9 for generating the mode extension signal INTDPD2, and FIG. 15 shows an operation waveform diagram thereof.
More specifically, in the signal generation circuit 9, PMOS transistors Tp5 and Tp6 and an NMOS transistor Tn4 are connected in series. The internal power supply voltage VINT is supplied to the source of the PMOS transistor Tp5, and the source of the NMOS transistor Tn4 is connected to the ground.
[0020]
The power-on reset signal POR is input to the gate of the PMOS transistor Tp5, and the power-down mode signal INTDPD1 is input to the gates of the PMOS transistor Tp6 and the NMOS transistor Tn4. The power-on reset signal POR is a signal for detecting the potential level of the internal power supply voltage VINT. When the internal power supply voltage VINT is equal to or higher than a predetermined voltage, the power-on reset signal POR goes low (ground potential level). (The potential level of the internal power supply voltage VINT).
[0021]
The power-on reset signal POR is input to the gate of the NMOS transistor Tn5. The drain of the NMOS transistor Tn5 is connected to a connection between the PMOS transistor Tp6 and the NMOS transistor Tn4, and the source of the transistor Tn5 is connected to the ground. Therefore, when the transistor Tn5 is turned on by the power-on reset signal POR, the connection between the PMOS transistor Tp6 and the NMOS transistor Tn4 becomes the ground potential.
[0022]
The gate of the NMOS transistor Tn6 is connected to the connection between the PMOS transistor Tp6 and the NMOS transistor Tn4. The source of the NMOS transistor Tn6 is connected to the ground, and the drain of the NMOS transistor Tn6 is connected to the input terminal of the inverter circuit 10a and the output terminal of the inverter circuit 10b.
[0023]
The drain of the NMOS transistor Tn7 is connected to the output terminal of the inverter circuit 10a and the input terminal of the inverter circuit 10b, and the source of the transistor Tn7 is connected to the ground. The power down mode signal INTDPD1 is input to the gate of the NMOS transistor Tn7.
[0024]
In this signal generation circuit 9, the potential level at the connection between the input terminal of inverter circuit 10a and the output terminal of inverter circuit 10b is output as mode extension signal INTDPD2.
[0025]
Next, the operation of the signal generation circuit 9 will be described.
As shown in FIG. 15, when the operation mode of the semiconductor device 1 is the normal mode (prior to time t1), the power-down mode signal INTDPD1 and the power-on reset signal POR are at the L level. In this case, since the PMOS transistors Tp5 and Tp6 are turned on and the NMOS transistors Tn4 and Tn5 are turned off, the gate potential of the NMOS transistor Tn6 becomes H level and the transistor Tn6 is turned on. Further, the NMOS transistor Tn7 is turned off by the L-level power down mode signal INTDPD1. Therefore, the mode extension signal INTDPD2 output from the signal generation circuit 9 becomes L level.
[0026]
At time t1, the operation mode of semiconductor device 1 shifts from the normal mode to the DPD mode, and when power down mode signal INTDPD1 is inverted from the L level to the H level, internal power supply generating circuit 4 generates internal power supply voltage VINT. Is stopped, and the internal power supply voltage VINT gradually decreases.
[0027]
At this time, the PMOS transistor Tp6 is turned off and the NMOS transistor Tn4 is turned on by the H level power down mode signal INTDPD1, so that the gate potential of the NMOS transistor Tn6 becomes L level and the transistor Tn6 is turned off. The NMOS transistor Tn7 is turned on by the H-level power down mode signal INTDPD1. Therefore, the mode extension signal INTDPD2 output from the signal generation circuit 9 is inverted from L level to H level.
[0028]
Further, as the internal power supply voltage VINT decreases, the power-on reset signal POR becomes H level. The PMOS transistor Tp5 is turned off and the NMOS transistor Tn5 is turned on by the H-level power-on reset signal POR. At this time, the mode extension signal INTDPD2 output from the signal generation circuit 9 is maintained at the H level.
[0029]
At time t2, when power down mode signal INTDPD1 is inverted from H level to L level, internal power supply generation circuit 4 is activated and internal power supply voltage VINT is gradually increased. Here, in a period T1 (time t2 to t3) until the internal power supply voltage VINT reaches a predetermined voltage value, the power-on reset signal POR is at the H level, so that the PMOS transistor Tp5 is turned off and the NMOS transistor Tn5 Is turned on. At this time, both the NMOS transistor Tn6 and the NMOS transistor Tn7 are turned off, and the mode extension signal INTDPD2 output from the signal generation circuit 9 is maintained at the H level.
[0030]
When the internal power supply voltage VINT rises and the power-on reset signal POR goes low at time t3, the PMOS transistor Tp5 is turned on and the NMOS transistor Tn5 is turned off. At this time, the transistor Tp6 is turned on by the power-down mode signal INTDPD1, and the transistor Tn4 is turned off, so that the NMOS transistor Tn6 is turned on. Since the NMOS transistor Tn7 is turned off by the power down mode signal INTDPD1, the mode extension signal INTDPD2 output from the signal generation circuit 9 is inverted from H level to L level.
[0031]
As described above, the mode extension signal INTDPD2 is maintained at the H level during the period T1 when the internal power supply voltage VINT is at the low voltage and the power-on reset signal POR is at the H level.
[0032]
[Patent Document 1]
JP-A-2002-170383
[0033]
[Patent Document 2]
JP-A-2002-305245
[0034]
[Problems to be solved by the invention]
Incidentally, the power-on reset signal POR is normally inverted from the H level to the L level in the middle of the return period T2 (time t3) in which the internal power supply voltage VINT returns to the predetermined voltage value. Therefore, there is a possibility that the extension of the ON period of the mode extension signal INTDPD2 cannot be sufficiently compensated as a measure against the through current described above.
[0035]
The internal power supply generation circuit 4 mounted on the semiconductor device 1 includes a plurality of internal power supply voltages VINT1 (for example, 2.0 V) and VINT2 (for example, based on the external power supply voltage VEXT (for example, 3.3 V)). (4.0 V) has also been put to practical use. That is, in the internal power supply generation circuit 4, one internal power supply voltage VINT1 is generated by reducing the external power supply voltage VEXT, and the other internal power supply voltage VINT2 is generated by boosting the external power supply voltage.
[0036]
In this case, as shown in FIG. 16, the return period T3 until the internal power supply voltage VINT2 becomes a constant voltage is longer than the return period T4 of the internal power supply voltage VINT1. The extension of the ON period of the mode extension signal INTDPD2 becomes insufficient. Therefore, in the level shift circuit that shifts the level between the internal power supply voltage VINT2 and the external power supply voltage VEXT or the level shift circuit that shifts the level between the internal power supply voltages VINT1 and VINT2, the above-described through current becomes a problem.
[0037]
In general, the driving capability of the circuit that generates the internal power supply voltage VINT1 (step-down circuit) is greater than that of the circuit that generates the internal power supply voltage VINT2 (step-up circuit). Therefore, if the countermeasure against the through current is not sufficient, the internal power supply voltage VINT2 cannot be boosted by the through current, and the semiconductor device 1 cannot be normally restarted after returning from the DPD mode. Would.
[0038]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of preventing a through current flowing in an internal circuit when returning from a power down mode, and a control method thereof. It is in.
[0039]
[Means for Solving the Problems]
In the semiconductor device of the present invention, the internal power supply voltage is generated by the internal power supply circuit, and the internal power supply voltage is supplied to the internal circuit. The mode control circuit generates a power-down mode signal based on a control signal input from outside the device. When the power down mode signal is turned on, the internal power supply generation circuit is inactivated and generation of the internal power supply voltage is stopped. Thereafter, when the power down mode signal is turned off, the internal power supply generation circuit is activated to set the internal power supply voltage to a predetermined value. It returns to the voltage value.
[0040]
According to the first aspect of the present invention, the internal timer measures the elapsed time after the power down mode signal is turned off, and generates a mode extension signal obtained by extending the on period of the power down mode signal by a predetermined time. Then, when a mode extension signal is input to at least a part of the internal circuit that operates by being supplied with two power supply voltages including the internal power supply voltage, the circuit is inactivated. Here, only one of the two power supply voltages serving as the operating voltages of the internal circuit may be the internal power supply voltage, or both may be the internal power supply voltage.
[0041]
With this configuration, the mode extension signal can be reliably turned on during a period in which the internal power supply generating circuit is activated and the internal power supply voltage is restored to a predetermined voltage value. Then, by inactivating the internal circuit by the mode extension signal, it is possible to prevent a through current flowing through the circuit.
[0042]
According to the second aspect of the present invention, in the signal generating circuit, the oscillation frequency of the oscillating unit that operates based on the internal power supply voltage is detected by the frequency detection unit, and based on the detection signal output from the frequency detection unit. A mode extension signal is generated. Then, when the mode extension signal is input to at least a part of the internal circuit, the circuit is inactivated. According to this configuration, similarly to the first aspect of the invention, the mode extension signal can be reliably turned on during the return period of the internal power supply voltage, and the through current flowing in the internal circuit can be prevented. Become.
[0043]
According to the third aspect of the present invention, in the signal generation circuit, a voltage signal whose voltage level gradually increases after the power down mode signal is turned off is output by the voltage generation means, and the voltage signal rises to a predetermined voltage or more. Is detected by the voltage detecting means. A mode extension signal is generated based on the detection signal output from the voltage detection means, and the circuit is deactivated by inputting the mode extension signal to at least a part of the internal circuits. According to this configuration, similarly to the first aspect of the invention, the mode extension signal can be reliably turned on during the return period of the internal power supply voltage, and the through current flowing in the internal circuit can be prevented. Become.
[0044]
According to the fourth aspect of the present invention, in the signal generation circuit, a predetermined command is recognized by the command recognition unit based on a control signal input from outside the device, and mode expansion is performed based on an output signal of the command recognition unit. A signal is generated. Then, when the mode extension signal is input to at least a part of the internal circuit, the circuit is inactivated. According to this configuration, similarly to the first aspect of the invention, the mode extension signal can be reliably turned on during the return period of the internal power supply voltage, and the through current flowing in the internal circuit can be prevented. Become.
[0045]
According to the invention described in claim 5, the signal generation circuit includes a flip-flop circuit, and the output signal of the command recognition unit and the power-down mode signal are input to the flip-flop circuit.
[0046]
According to the invention described in claim 6, the flip-flop circuit has the set input unit and the reset input unit, and the mode extension signal is turned on by the power down mode signal input to the set input unit, and the reset unit is turned on. The mode extension signal is turned off by the input output signal of the command recognition unit.
[0047]
According to the seventh aspect of the invention, the mode extension signal is input to the level shift circuit that performs voltage conversion between the internal power supply voltage and the external power supply voltage, and the level shift circuit is inactivated. Therefore, the problem that the input of the level shift circuit becomes unstable during the return period of the internal power supply voltage and a through current flows can be avoided.
[0048]
According to the invention of claim 8, the first internal power supply voltage and the second internal power supply voltage different from the first internal power supply voltage are generated by the internal power supply generation circuit. Then, the mode extension signal is input to a level shift circuit that performs voltage conversion between the first internal power supply voltage and the second internal power supply voltage, and the level shift circuit is inactivated. Therefore, the problem that the input of the level shift circuit becomes unstable during the return period of each internal power supply voltage and a through current flows is avoided.
[0049]
According to the ninth and tenth aspects of the present invention, when the power down mode signal is turned on, the internal power supply generating circuit is inactivated and the internal power supply voltage is controlled from the first potential level to the second potential level. Thereafter, when the power down mode signal is turned off, the internal power supply generating circuit is activated, and the internal power supply voltage is returned from the second potential level to the first potential level.
[0050]
According to the ninth aspect, the time elapsed after the power down mode signal is turned off is measured by the internal timer, and two power supply voltages including the internal power supply voltage are supplied by the output signal of the internal timer to operate. At least a part of the internal circuit is deactivated for a predetermined time. With this configuration, after the power down mode is released, the internal circuit is deactivated during a period in which the internal power supply generating circuit is activated and the internal power supply voltage returns from the second potential level to the first potential level. , It is possible to prevent a through current flowing through the circuit.
[0051]
According to the tenth aspect, after the power down mode signal is turned off, at least a part of the internal circuits is inactive until a predetermined command for shifting to an operation mode other than the power down mode is recognized. Be converted to This makes it possible to prevent a through current flowing through the internal circuit during the return period of the internal power supply voltage, as in the ninth aspect of the present invention.
[0052]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0053]
FIG. 1 shows a semiconductor device (specifically, SDRAM) 11 of the present embodiment. In FIG. 1, the same components (the input circuit 2, the mode control circuit 3, the internal power generation circuit 4, and the internal circuit 5) as those of the conventional example are denoted by the same reference numerals, and the description thereof is partially omitted.
[0054]
As shown in FIG. 1, the semiconductor device 11 is provided with an input circuit 2, a mode control circuit 3, an internal power supply generation circuit 4, an internal circuit 5, and an internal timer 12. The internal circuit 5 includes an internal processing circuit 6 and a level shift circuit 7. Internal processing circuit 6 includes a CPU for executing various processes in semiconductor device 11 and peripheral circuits thereof. The level shift circuit 7 has the same circuit configuration as the level shift circuit (see FIG. 13) described in the related art, and responds to an input signal AINT input from the internal processing circuit 6 from an internal power supply voltage VINT to an external power supply. An output signal AEXT converted to the voltage level of the voltage VEXT is output.
[0055]
The power-down mode signal INTDPD1 is input from the mode control circuit 3 to the internal timer 12. The internal timer 12 generates and outputs a mode extension signal INTDPD2 obtained by extending the on-period (the H-level period) of the power-down mode signal INTDPD1 by a predetermined time.
[0056]
FIG. 2 shows a circuit configuration of the internal timer 12, and FIG. 3 shows an operation waveform diagram thereof.
As shown in FIG. 2, the internal timer 12 includes a DPD signal generation unit 14, an oscillation unit 15, a count unit 16, and a release signal output unit 17. In the internal timer 12, the external power supply voltage VEXT is supplied as an operation voltage to the DPD signal generation unit 14 (the NOR circuits 14a and 14b), the oscillation unit 15, the count unit 16, and the release signal output unit 17.
[0057]
The oscillating unit 15 outputs an oscillating signal OSC of a predetermined frequency. When the power down mode signal INTDPD1 is inverted from the H level to the L level, the counting unit 16 detects the falling edge of the signal and starts the counting operation of the oscillation signal OSC of the oscillation unit 15. The release signal output unit 17 determines whether or not the count value C1 of the count unit 16 has exceeded a predetermined value, and outputs a pulse-shaped release signal CA when the count value C1 has exceeded the predetermined value.
[0058]
The DPD signal generation unit 14 is a flip-flop circuit including two NOR circuits 14a and 14b. In the NOR circuit 14a of the DPD signal generation unit 14, a power down mode signal INTDPD1 is input to a first input terminal, a clear signal CLRB is input to a second input terminal, and an output signal of the NOR circuit 14b is input to a third input terminal. Has been entered. An output signal of the NOR circuit 14a is input to a first input terminal of the NOR circuit 14b, and a release signal CA is input to a second input terminal of the NOR circuit 14b. Then, the output signal of the NOR circuit 14b is output as the mode extension signal INTDPD2.
[0059]
In the DPD signal generator 14, the input terminal of the NOR circuit 14a corresponds to a set input unit, and the input terminal of the NOR circuit 14b corresponds to a reset input unit.
The operation of the internal timer 12 configured as described above will be described.
[0060]
As shown in FIG. 3, when the operation mode of the semiconductor device 11 is the DPD mode and the power down mode signal INTDPD1 from the mode control circuit 3 is at the H level, the output signal of the NOR circuit 14a is at the L level, and the NOR circuit 14b Becomes H level. At this time, the DPD signal generation unit 14 outputs the H-level mode extension signal INTDPD2.
[0061]
At time t11, when power down mode signal INTDPD1 is inverted from H level to L level, internal power supply generation circuit 4 is activated, and internal power supply voltage VINT, which is the output voltage of internal power supply generation circuit 4, is gradually increased. . Further, in the internal timer 12, the counting operation of the oscillation signal OSC output from the oscillation unit 15 is started by the counting unit 16, and the count value C1 is incremented by "1" after time t11.
[0062]
At time t12 when a predetermined time has elapsed from time t11, the release signal output unit 17 determines that the count value C1 has exceeded the predetermined value, and outputs a pulse-shaped release signal CA. With the release signal CA, the output signal of the NOR circuit 14b in the DPD signal generator 14 goes low, and the mode extension signal INTDPD2 output from the DPD signal generator 14 is inverted from the high level to the low level.
[0063]
In the semiconductor device 11, a return period T11 in which the internal power supply voltage VINT returns to a predetermined voltage value (= 2.0 V) differs depending on the operation state of the internal circuit 5. Therefore, in the present embodiment, the output timing (time t12) of the release signal CA from the internal timer 12 is determined by the extension time (time t11 to t12) of the mode extension signal INTDPD2 in consideration of the operation state of the internal circuit 5. It is set to be longer than the return period T11 of the voltage VINT.
[0064]
When the mode extension signal INTDPD2 is input to the level shift circuit 7 (see FIG. 13), a through current in the level shift circuit 7 is prevented.
[0065]
As described above, according to the above embodiment, the following effects can be obtained.
The internal timer 12 operates by being supplied with the external power supply voltage VEXT, and can accurately measure the elapsed time after the power-down mode signal INTDPD1 is turned off. Therefore, the internal timer 12 appropriately sets the extension time of the mode extension signal INTDPD2 with respect to the power down mode signal INTDPD1 (the period from time t11 to time t12). Specifically, in the return period T11 of internal power supply voltage VINT, mode extension signal INTDPD2 is maintained at the H level, and level shift circuit 7 is deactivated by mode extension signal INTDPD2. In this way, by inactivating the level shift circuit 7 during the return period T11 of the internal power supply voltage VINT, it is possible to prevent a through current flowing through the level shift circuit 7.
[0066]
(2nd Embodiment)
Hereinafter, a second embodiment of the present invention will be described.
The semiconductor device 11 of the present embodiment includes a signal generation circuit 21 shown in FIG. 4 instead of the internal timer 12 of the first embodiment.
[0067]
More specifically, the signal generation circuit 21 includes an oscillation unit 22, a frequency detection unit 23, a release signal output unit 24, and a DPD signal generation unit 14. The DPD signal generator 14 has the same circuit configuration as that of the first embodiment.
[0068]
The oscillating unit 22 includes odd-numbered (three in FIG. 4) inverter circuits 22a, 22b, and 22c connected in a loop to form a ring oscillator. The internal power supply voltage VINT from the internal power supply generation circuit 4 is supplied to the oscillating unit 22, and the oscillating unit 22 outputs an oscillating signal OSC 1 having a frequency corresponding to the voltage value of the internal power supply voltage VINT.
[0069]
The external power supply voltage VEXT is supplied to the frequency detection unit 23 and the release signal output unit 24, and the circuits of the frequency detection unit 23 and the release signal output unit 24 operate based on the external power supply voltage VEXT.
[0070]
That is, the frequency detection unit 23 captures the oscillation signal OSC1 of the oscillation unit 22, and detects the frequency of the oscillation signal OSC1. Here, when the oscillation signal OSC1 is lower than the predetermined frequency, the frequency detector 23 outputs the L-level detection signal MON1, and when the oscillation signal OSC1 becomes higher than the predetermined frequency, outputs the H-level detection signal MON1. I do. Note that, as the predetermined frequency, a frequency slightly lower than the oscillation frequency of the oscillation unit 22 in the normal mode (when the internal power supply voltage VINT is 2.0 V) is set. Further, the release signal output unit 24 detects a rising edge of the detection signal MON1, and outputs a pulse-shaped release signal CA at the time of the detection.
[0071]
The operation of the signal generation circuit 21 configured as described above will be described.
As shown in FIG. 5, at time t21, when power down mode signal INTDPD1 is inverted from H level to L level, internal power supply generating circuit 4 is activated, and internal power supply voltage VINT is gradually increased. As the internal power supply voltage VINT rises, the frequency of the oscillation signal OSC1 of the oscillation unit 15 gradually increases.
[0072]
At time t22, the frequency detector 23 detects that the oscillation signal OSC1 has exceeded a predetermined frequency, and the detection signal MON1 is inverted from L level to H level. Then, the release signal output section 24 outputs a pulse-like release signal CA. With the release signal CA, the output signal of the NOR circuit 14b in the DPD signal generator 14 goes low, and the mode extension signal INTDPD2 output from the DPD signal generator 14 is inverted from the high level to the low level.
[0073]
As described above, according to the above embodiment, the following effects can be obtained.
The timing (time t22) when the oscillation frequency of the oscillation unit 22 becomes equal to or higher than the predetermined frequency is detected by the frequency detection unit 23, and the mode extension signal INTDPD2 is turned off based on the detection signal MON1 output from the frequency detection unit 23. . By doing so, the extension time of the mode extension signal INTDPD2 with respect to the power-down mode signal INTDPD1 (the period from time t21 to time t22) can be accurately set according to the voltage level of the internal power supply voltage VINT. That is, the mode extension signal INTDPD2 can be reliably turned on during the return period of the internal power supply voltage VINT. Then, the mode extension signal INTDPD2 is input to the level shift circuit 7 (see FIG. 13), and the level shift circuit 7 is deactivated during the return period of the internal power supply voltage VINT, so that the through current flowing through the level shift circuit 7 is reduced. Can be prevented.
[0074]
(Third embodiment)
Hereinafter, a third embodiment of the invention will be described.
The semiconductor device 11 of the present embodiment includes a signal generation circuit 31 shown in FIG. 6 instead of the internal timer 12 of the first embodiment.
[0075]
The signal generation circuit 31 includes a voltage generation unit 32, a voltage detection unit 33, a release signal output unit 34, and a DPD signal generation unit 14. The DPD signal generator 14 has the same circuit configuration as the first embodiment.
[0076]
More specifically, in the voltage generator 32, PMOS transistors Tp11 and Tp12 are connected in series. The external power supply voltage VEXT is supplied to the source of the PMOS transistor Tp11, and the drain of the PMOS transistor Tp12 is connected to the ground via the resistor R11. The power down mode signal INTDPD1 from the mode control circuit 3 is input to the gate of the PMOS transistor Tp11. The gate and the drain of the PMOS transistor Tp12 are connected, and a voltage signal VR is output from the connection.
[0077]
The voltage detection unit 33 includes an inverter circuit 35, a PMOS transistor Tp13, and an NMOS transistor Tn11, and activates the detection signal MON2 by detecting that the voltage signal VR output from the voltage generation unit 32 has reached a predetermined voltage.
[0078]
Specifically, in the voltage detection unit 33, the PMOS transistor TP13 and the NMOS transistor Tn11 are connected in series. The external power supply voltage VEXT is supplied to the source of the PMOS transistor Tp13, and the source of the NMOS transistor Tn11 is connected to the ground. The gate of the PMOS transistor Tp13 is connected to the ground, and the voltage signal VR is input to the gate of the NMOS transistor Tn11.
[0079]
A logic inversion circuit is formed by the PMOS transistor TP13 and the NMOS transistor Tn11, and a connection between the PMOS transistor TP13 and the NMOS transistor Tn11 is an output terminal of the logic inversion circuit. The output terminal thereof is connected to an inverter circuit 35, through which the detection signal MON2 is output.
[0080]
In the voltage detector 33, the threshold voltage of the logic inversion circuit including the PMOS transistor TP13 and the NMOS transistor Tn11 is set by the balance between the conductance of the PMOS transistor Tp13 and the conductance of the NMOS transistor Tn11.
[0081]
Specifically, when power down mode signal INTDPD1 is inverted from the H level to the L level and the operation mode of semiconductor device 11 returns from the DPD mode to the normal mode, voltage signal VR rises from the ground voltage and is set in advance. It reaches a predetermined voltage. A constant voltage value up to the predetermined voltage is set as a threshold voltage. Therefore, when the voltage signal VR exceeds the threshold voltage, the voltage detection unit 33 outputs the H-level detection signal MON2.
[0082]
The release signal output unit 34 includes a buffer circuit 36, an inverter circuit 37, and an AND circuit 38. In the release signal output unit 34, the detection signal MON2 from the voltage detection unit 33 is input to the first input terminal of the AND circuit 38, and the second signal of the AND circuit 38 is input via the buffer circuit 36 and the inverter circuit 37. Input to the input terminal. Here, when the detection signal MON2 is inverted from the L level to the H level, a pulse-shaped release signal CA is output from the AND circuit 38, and the release signal CA is input to the DPD signal generation unit 14.
[0083]
The operation of the signal generation circuit 31 configured as described above will be described.
As shown in FIG. 7, when power down mode signal INTDPD1 output from mode control circuit 3 attains an H level, internal power supply generation circuit 4 is deactivated, so that internal power supply voltage VINT gradually decreases to the ground voltage. I do. At this time, since the PMOS transistor Tp11 is turned off in the voltage generator 32, the voltage signal VR also gradually decreases to the ground voltage. Then, when the voltage signal VR decreases, the detection signal MON2 of the voltage detection unit 33 is inverted from the H level to the L level. When the power-down mode signal INTDPD1 goes high, the output signal of the NOR circuit 14a goes low and the output signal of the NOR circuit 14b goes high, and the DPD signal generation section 14 outputs the mode expansion signal INTDPD2 of high level. Is output.
[0084]
At time t31, when power down mode signal INTDPD1 is inverted from H level to L level, internal power supply generation circuit 4 is activated, and internal power supply voltage VINT is gradually increased. At this time, in the voltage generator 32, the PMOS transistor Tp11 is turned on, and the voltage signal VR is gradually increased until it reaches a predetermined voltage. Then, at time t32, when the voltage signal VR exceeds the threshold voltage of the voltage detection unit 33, the detection signal MON2 of the voltage detection unit 33 is inverted from L level to H level.
[0085]
At this time t32, the pulse-shaped release signal CA is output from the release signal output unit 34, the output signal of the NOR circuit 14b in the DPD signal generation unit 14 becomes L level, and the mode expansion output from the DPD signal generation unit 14 is performed. Signal INTDPD2 is inverted from H level to L level.
[0086]
In semiconductor device 11, the return period of internal power supply voltage VINT differs depending on the operation state of internal circuit 5, whereas the return period of voltage signal VR (time t31 to t32) is independent of the operation state of internal circuit 5. It will be a certain time. In the present embodiment, the return period of the voltage signal VR is the extension time of the mode extension signal INTDPD2 (time t31 to t32), and is set to be longer than the return period of the internal power supply voltage VINT.
[0087]
As described above, according to the above embodiment, the following effects can be obtained.
After the power down mode signal INTDPD1 is turned off, the voltage signal VR output from the voltage generation unit 32 is gradually increased, and the voltage detection unit 33 detects that the voltage signal VR has reached a predetermined voltage value or more. . The mode extension signal INTDPD2 is turned off based on the detection signal MON2 of the voltage detector 33. By doing so, the mode extension signal INTDPD2 can be reliably turned on during the return period of the internal power supply voltage VINT. Then, the mode extension signal INTDPD2 is input to the level shift circuit 7 (see FIG. 13), and the level shift circuit 7 is deactivated during the return period of the internal power supply voltage VINT, so that a through current flowing through the level shift circuit 7 is obtained. Can be prevented.
[0088]
(Fourth embodiment)
Hereinafter, a fourth embodiment of the invention will be described.
The semiconductor device 11 of the present embodiment includes a signal generation circuit 41 shown in FIG. 8 instead of the internal timer 12 of the first embodiment.
[0089]
In the semiconductor device 11, when returning from the DPD mode to the normal mode, a mode register set command or the like is issued as initialization processing for accessing the memory. In the present embodiment, the ON period of the mode extension signal INTDPD2 is extended using the mode register set command.
[0090]
More specifically, the signal generation circuit 41 includes a command recognition unit 42 and a DPD signal generation unit 14. The DPD signal generator 14 has the same circuit configuration as the first embodiment.
[0091]
The command recognition unit 42 includes AND circuits 43 and 44, a buffer circuit 45, and an inverter circuit 46. The AND circuit 43 of the command recognition unit 42 is a multi-input logic gate. The control signal INTCSQB is input to a first input terminal, and the control signal INTRASQB is input to a second input terminal. Further, a control signal INTCASQB is input to a third input terminal of the AND circuit 43, and a control signal INTWEQB is input to a fourth input terminal.
[0092]
Then, the output signal of the AND circuit 43 is input to a pulse generation unit including the AND circuit 44, the buffer circuit 45, and the inverter circuit 46. Specifically, the output signal of the AND circuit 43 is input to the first input terminal of the AND circuit 44 and is input to the second input terminal of the AND circuit 44 via the buffer circuit 45 and the inverter circuit 46.
[0093]
Here, each control signal input to the AND circuit 43 is a signal used to determine various modes in the mode control circuit 3, and is based on a control signal input from the outside of the device via the input circuit 2. Generated.
[0094]
In the semiconductor device 11 of the present embodiment, when a command of the mode register set is issued, each of the control signals INTCSQB, INTRASQB, INTCASQB, and INTWEQB, which are input signals of the AND circuit 43, becomes H level. Therefore, when the command is issued, the output signal of the AND circuit 43 is inverted from the L level to the H level in the command recognition unit 42, and the AND circuit 44 outputs a pulse-like release signal CA.
[0095]
The operation of the signal generation circuit 41 configured as described above will be described.
As shown in FIG. 9, at time t41, a command DPDEX for releasing the DPD mode is issued. At this time, the power down mode signal INTDPD1 is inverted from H level to L level. Therefore, internal power supply generation circuit 4 is activated, and internal power supply voltage VINT is gradually increased.
[0096]
Also, at time t42 when a predetermined time has elapsed after the command DDPEX was issued, the mode register set command MRS is issued. When the command MRS is issued, the output signal of the AND circuit 43 is inverted from the L level to the H level in the command recognition unit 42 of the signal generation circuit 41, and a pulse release signal CA is output from the AND circuit 44. . Then, the mode extension signal INTDPD2 is inverted from H level to L level by the release signal CA.
[0097]
As described above, in the present embodiment, the period from the time t41 at which the release command DPDEX of the DPD mode is issued to the time t42 at which the command MRS of the mode register set is issued is the extension time of the mode extension signal INTDPD2 (time t41 to time t41). t42).
[0098]
As described above, according to the above embodiment, the following effects can be obtained.
The command MRS of the mode register set is recognized by the command recognition unit 42, and the mode extension signal INTDPD2 is turned off based on the release signal CA output from the command recognition unit 42. By doing so, the mode extension signal INTDPD2 can be reliably turned on during the return period of the internal power supply voltage VINT. Then, the mode extension signal INTDPD2 is input to the level shift circuit 7 (see FIG. 13), and the level shift circuit 7 is deactivated, whereby a through current flowing through the level shift circuit 7 can be prevented.
[0099]
The above embodiment can be modified as follows.
In the semiconductor device 11 of each of the above embodiments, the semiconductor device 11 is applied to the level shift circuit 7 that performs voltage conversion between the internal power supply voltage VINT and the external power supply voltage VEXT, but is not limited thereto. For example, as shown in FIG. 10, the present invention may be applied to a level shift circuit 7 that performs voltage conversion between a first internal power supply voltage VINT1 and a second internal power supply voltage VINT2 output from an internal power supply generation circuit 4.
[0100]
Specifically, in semiconductor device 11 of FIG. 10, internal power supply generation circuit 4 includes first generation unit 4a and second generation unit 4b. The first generator 4a generates a first internal power supply voltage VINT1 (= 2.0V) by stepping down the external power supply voltage VEXT (= 3.3V), and uses the internal power supply voltage VINT1 to the internal processing circuit 6 and the level. It is supplied to the shift circuit 7. The second generator 4b generates the second internal power supply voltage VINT2 (= 4.0V) by boosting the external power supply voltage VEXT, and supplies the internal power supply voltage VINT2 to the level shift circuit 7.
[0101]
Also, the mode extension signal INTDPD2 from the internal timer 12 is input to the level shift circuit 7, and the level shift circuit 7 is inactivated during the return period of each of the internal power supply voltages VINT1 and VINT2. Here, the return period of the second internal power supply voltage VINT2 generated by boosting the external power supply voltage VEXT is longer than the return period of the internal power supply voltage VINT1. Therefore, the extension time of the mode extension signal INTDPD2 in the internal timer 12 is set to be longer than the return period of the second internal power supply voltage VINT2.
[0102]
This can prevent a through current in the level shift circuit 7. Further, the second internal power supply voltage VINT2 higher than the external power supply voltage VEXT can be reliably boosted.
[0103]
In the above embodiments, positive internal power supply voltages VINT1 (= 2.0 V) and VINT2 (= 4.0 V) are used as power supply voltages to be converted by the level shift circuit 7. However, other than that, A negative internal power supply voltage may be used.
[0104]
In the above embodiments, the internal power supply generating circuit 4 sets the internal power supply voltage VINT to the ground potential when inactive (during the DPD mode). However, the internal power supply voltage VINT may be set to the floating potential.
[0105]
In the semiconductor device 11 of each of the above embodiments, the configuration is such that the through current of the level shift circuit 7 is prevented. However, the present invention is not limited to this, and a mode extension signal is supplied to circuits other than the level shift circuit 7 in the internal circuit 5. The configuration may be such that INTDPD2 is supplied to prevent a through current.
[0106]
FIG. 11 shows a signal transmission circuit as a specific example thereof. In this signal transmission circuit, an input signal AIN is input to an inverter circuit 51, and an output signal of the inverter circuit 51 is transmitted to an inverter circuit 52 via an NMOS transistor Tn51, and is output as an output signal AOUT from the inverter circuit 52. . An external power supply voltage VEXT is supplied to power supply terminals of the inverter circuits 51 and 52. That is, the input signal AIN and the output signal AOUT are signals that swing at the voltage level of the external power supply voltage VEXT.
[0107]
The control signal S1 is input to the gate of the NMOS transistor Tn51 via the inverter circuit 53. The power supply terminal of the inverter circuit 53 is supplied with a boosted voltage Vpp (for example, 4.0 V) higher than the external power supply voltage VEXT (for example, 3.3 V). Boosted voltage Vpp is an internal power supply voltage generated by the boosting operation in internal power supply generation circuit 4. As described above, by driving the NMOS transistor Tn51 with a gate voltage higher than the external power supply voltage VEXT, the input signal AIN that swings at the voltage level of the external power supply voltage VEXT can be transmitted through the NMOS transistor Tn51.
[0108]
The drain of the PMOS transistor Tp51 is connected between the NMOS transistor Tn51 and the inverter circuit 52, and the source of the transistor Tp51 is supplied with the external power supply voltage VEXT. The mode extension signal INTDPD2 from the internal timer 12 is input to the gate of the transistor Tp51 via the inverter circuit 54.
[0109]
Here, if the internal power supply voltage Vpp decreases in the DPD mode, the input of the inverter circuit 52 becomes unstable and a through current may flow through the inverter circuit 52. In order to prevent the shoot-through current, in the DPD mode, the input of the inverter circuit 52 is fixed at the voltage level of the external power supply voltage VEXT by turning on the PMOS transistor Tp51 based on the mode extension signal INTDPD2. Further, even during the period in which the internal power supply voltage Vpp returns from the transition from the DPD mode to the normal mode, the through current can be reliably prevented by turning on the PMOS transistor Tp51 by the mode extension signal INTDPD2.
[0110]
The internal timer 12 of the first embodiment measures the elapsed time after the power-down mode signal INTDPD1 is turned off by the counting unit 16 counting up the oscillation signal OSC of the oscillation unit 22. It is not limited to this. For example, a counting unit that counts down instead of counting up may be used. Instead of counting the oscillation signal OSC of the oscillation unit 22, a counting unit that counts the clock signal CLK input from the outside may be used.
[0111]
In the fourth embodiment, the mode extension signal INTDPD2 is turned off when the command MRS of the mode register set is recognized. However, another command for performing the initialization process (for example, a command for precharge or auto-refresh) ) Is recognized, the mode extension signal INTDPD2 may be turned off.
[0112]
The internal timer 12 and the signal generation circuits 21, 31, and 41 are configured to operate by being supplied with the external power supply voltage VEXT, but are not limited thereto. Specifically, some semiconductor devices include an internal power supply generation circuit that is activated even in the DPD mode. Since the internal power supply voltage generated by the internal power supply generation circuit is always maintained at a constant voltage value regardless of whether the power down mode signal INTDPD1 is on or off, the internal power supply voltage is set to the internal timer 12 and the signal generation circuit. It is good also as composition supplied to 21,31,41.
[0113]
In the above embodiment, the semiconductor device 11 is embodied as a clock synchronous semiconductor memory device (SDRAM), but may be embodied in another semiconductor device.
[0114]
The above various embodiments are summarized as follows.
(Supplementary Note 1) An internal power supply generating circuit that generates an internal power supply voltage and supplies the internal power supply voltage to an internal circuit, and a mode control circuit that generates a power down mode signal based on an input control signal, When the power down mode signal is turned on, the internal power supply generating circuit is inactivated to stop the generation of the internal power supply voltage, and when the power down mode signal is turned off, the internal power supply generating circuit is activated to set the internal power supply voltage to a predetermined value. In the semiconductor device to return to the voltage value of
An internal timer that generates a mode extension signal by measuring an elapsed time after the power-down mode signal is turned off and extending an on-period of the power-down mode signal by a predetermined time,
A semiconductor device, wherein the mode extension signal is input to at least a part of circuits of the internal circuit which operate by receiving two power supply voltages including the internal power supply voltage, and deactivate the circuit.
(Supplementary Note 2) The internal timer includes an oscillating unit that outputs an oscillating signal of a predetermined frequency, a counting unit that counts an oscillating signal of the oscillating unit, and outputs a release signal when the count value of the counting unit reaches a predetermined value. 2. The semiconductor device according to claim 1, further comprising: a release signal output unit for performing the operation, and a flip-flop circuit to which the power down mode signal and the release signal are input.
(Supplementary Note 3) The flip-flop circuit includes a set input unit for turning on the mode extension signal, and a reset input unit for turning off the mode extension signal. 3. The semiconductor device according to claim 2, wherein a mode signal is input, and the reset signal is input to the reset input unit.
(Supplementary Note 4) The power supply device further includes: an internal power supply generation circuit that generates an internal power supply voltage and supplies the internal power supply voltage to an internal circuit; and a mode control circuit that generates a power down mode signal based on an input control signal. When the power down mode signal is turned on, the internal power supply generating circuit is inactivated to stop the generation of the internal power supply voltage, and when the power down mode signal is turned off, the internal power supply generating circuit is activated to set the internal power supply voltage to a predetermined value. In the semiconductor device to return to the voltage value of
The power-down mode signal includes frequency detection means for detecting that an oscillation signal of an oscillating unit that is operated by being supplied with the internal power supply voltage has reached a predetermined frequency, based on a detection signal output from the frequency detection means. A signal generation circuit that generates a mode extension signal in which the ON period is extended by a predetermined time,
A semiconductor device, wherein the mode extension signal is input to at least a part of circuits of the internal circuit which operate by receiving two power supply voltages including the internal power supply voltage, and deactivate the circuit.
(Supplementary Note 5) The power supply device includes: an internal power supply generation circuit that generates an internal power supply voltage and supplies the internal power supply voltage to an internal circuit; and a mode control circuit that generates a power down mode signal based on an input control signal. When the power down mode signal is turned on, the internal power supply generating circuit is inactivated to stop the generation of the internal power supply voltage, and when the power down mode signal is turned off, the internal power supply generating circuit is activated to set the internal power supply voltage to a predetermined value. In the semiconductor device to return to the voltage value of
Voltage generating means for outputting a voltage signal whose voltage level gradually increases after the power-down mode signal is turned off, and voltage detecting means for detecting that the voltage signal has risen to a predetermined voltage or more, the voltage detecting means A signal generation circuit that generates a mode extension signal obtained by extending an ON period of the power-down mode signal by a predetermined time based on a detection signal output from
A semiconductor device, wherein the mode extension signal is input to at least a part of circuits of the internal circuit which operate by receiving two power supply voltages including the internal power supply voltage, and deactivate the circuit.
(Supplementary Note 6) An internal power supply generating circuit that generates an internal power supply voltage and supplies the internal power supply voltage to an internal circuit, and a mode control circuit that generates a power-down mode signal based on an input control signal, When the power down mode signal is turned on, the internal power supply generating circuit is inactivated to stop the generation of the internal power supply voltage, and when the power down mode signal is turned off, the internal power supply generating circuit is activated to set the internal power supply voltage to a predetermined value. In the semiconductor device to return to the voltage value of
A command recognition unit that recognizes a predetermined command based on a control signal input from the outside of the apparatus, wherein a predetermined command is externally applied to the ON period of the power-down mode signal based on an output signal of the command recognition unit A signal generation circuit that generates a mode extension signal extended to
A semiconductor device, wherein the mode extension signal is input to at least a part of circuits of the internal circuit which operate by receiving two power supply voltages including the internal power supply voltage, and deactivate the circuit.
(Supplementary note 7) The supplementary note 6, wherein the signal generation circuit includes, in addition to the command recognition unit, a flip-flop circuit to which an output signal of the command recognition unit and the power-down mode signal are input. Semiconductor device.
(Supplementary Note 8) The flip-flop circuit includes a set input unit for turning on the mode extension signal, and a reset input unit for turning off the mode extension signal. 8. The semiconductor device according to claim 7, wherein a mode signal is input, and an output signal of the command recognition unit is input to the reset input unit.
(Supplementary Note 9) The command recognition unit includes a multi-input logic gate to which a plurality of control signals for recognizing a command are input, and a pulse generation unit that generates a pulse signal based on an output signal of the logic gate. 7. The semiconductor device according to supplementary note 6, wherein
(Supplementary note 10) The semiconductor device according to supplementary note 6, wherein the command recognized by the command recognition unit is a command for performing an initialization process of the internal circuit. (Supplementary Note 11) The semiconductor device according to any one of Supplementary Notes 1 to 10, further including a level shift circuit that performs voltage conversion between the internal power supply voltage and another power supply voltage as a part of the internal circuit. 13. The semiconductor device according to claim 1.
(Supplementary Note 12) The semiconductor according to any one of Supplementary Notes 1 to 10, further comprising a level shift circuit that performs voltage conversion between the internal power supply voltage and the external power supply voltage as a part of the internal circuit. apparatus.
(Supplementary Note 13) The internal power supply generating circuit generates a first internal power supply voltage and a second internal power supply voltage different from the first internal power supply voltage.
11. The semiconductor according to claim 1, further comprising a level shift circuit that performs voltage conversion between the first internal power supply voltage and the second internal power supply voltage as a part of the internal circuit. apparatus.
(Supplementary note 14) The semiconductor device according to supplementary note 1, wherein a power supply voltage maintained at a constant voltage value is supplied to the internal timer regardless of whether the power down mode signal is on or off.
(Supplementary note 15) In any one of Supplementary notes 4 to 6, wherein a power supply voltage maintained at a constant voltage value is supplied to the signal generation circuit regardless of whether the power down mode signal is on or off. 13. The semiconductor device according to claim 1.
(Supplementary Note 16) The internal power supply voltage is controlled from the first potential level to the second potential level when the internal power supply generation circuit is inactivated, and the internal power supply voltage is controlled to the second potential level when the internal power supply generation circuit is activated. 7. The semiconductor device according to any one of supplementary notes 1, 4 to 6, wherein the semiconductor device is restored from the level to the first potential level.
(Supplementary Note 17) An internal power supply generating circuit for generating an internal power supply voltage and supplying the internal power supply voltage to an internal circuit, and for activating or deactivating the internal power supply generation circuit based on an input control signal. A mode control circuit for generating a power-down mode signal.
Deactivating the internal power supply generating circuit to change the internal power supply voltage from a first potential level to a second potential level when the power down mode signal is on;
Activating the internal power supply generating circuit to return the internal power supply voltage from a second potential level to a first potential level when the power down mode signal is off;
At least a part of the internal circuit that operates by measuring an elapsed time after the power-down mode signal is turned off by using an internal timer and supplying two power supply voltages including the internal power supply voltage by an output signal of the internal timer. Inactivating for a predetermined time;
A method for controlling a semiconductor device, comprising:
(Supplementary Note 18) The time at which the internal timer starts counting at the time when the power down mode signal is inverted from on to off, and the elapse of a predetermined time by the count value, thereby turning off the mode extension signal. 18. The method for controlling a semiconductor device according to claim 17, wherein
(Supplementary Note 19) An internal power supply generating circuit for generating an internal power supply voltage and supplying the internal power supply voltage to an internal circuit, and for activating or deactivating the internal power supply generation circuit based on an input control signal. A mode control circuit for generating a power-down mode signal.
Deactivating the internal power supply generating circuit to change the internal power supply voltage from a first potential level to a second potential level when the power down mode signal is on;
Activating the internal power supply generating circuit to return the internal power supply voltage from a second potential level to a first potential level when the power down mode signal is off;
After the power down mode signal is turned off, two internal power supply voltages including the internal power supply voltage are supplied to operate the internal circuit until a predetermined command for shifting to an operation mode other than the power down mode is recognized. Deactivating at least a part of the circuit;
A method for controlling a semiconductor device, comprising:
(Supplementary note 20) The control method of a semiconductor device according to any one of Supplementary notes 17 to 19, wherein in a part of the internal circuit, an input signal is voltage-converted from the internal power supply voltage to a predetermined power supply voltage.
(Supplementary note 21) The control method of a semiconductor device according to supplementary note 20, wherein the predetermined power supply voltage is an internal power supply voltage higher than an external power supply voltage or an internal power supply voltage having a negative potential.
(Supplementary note 22) The control method of the semiconductor device according to supplementary note 21, wherein the internal power supply voltage higher than the external power supply voltage or an internal power supply voltage having a negative potential is generated by the internal power supply generation circuit.
[0115]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to prevent a through current flowing in the internal circuit when returning from the power down mode.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram illustrating a semiconductor device according to a first embodiment.
FIG. 2 is a circuit diagram showing an internal timer.
FIG. 3 is an operation waveform diagram of an internal timer.
FIG. 4 is a circuit diagram illustrating a signal generation circuit according to a second embodiment.
FIG. 5 is an operation waveform diagram of the signal generation circuit of FIG. 4;
FIG. 6 is a circuit diagram illustrating a signal generation circuit according to a third embodiment.
FIG. 7 is an operation waveform diagram of the signal generation circuit of FIG. 6;
FIG. 8 is a circuit diagram illustrating a signal generation circuit according to a fourth embodiment.
FIG. 9 is an operation waveform diagram of the signal generation circuit of FIG. 8;
FIG. 10 is a block circuit diagram showing another semiconductor device.
FIG. 11 is a circuit diagram showing a signal transmission circuit.
FIG. 12 is a block circuit diagram showing a conventional semiconductor device.
FIG. 13 is a circuit diagram showing a level shift circuit.
FIG. 14 is a circuit diagram showing a signal generation circuit.
FIG. 15 is an operation waveform diagram showing the signal generation circuit of FIG. 14;
FIG. 16 is an operation waveform diagram of another example.
[Explanation of symbols]
3 Mode control circuit
4 Internal power generation circuit
5 Internal circuit
7 Level shift circuit
11 Semiconductor device
12 Internal timer
21, 31, 41 signal generation circuit
22 Oscillator
23 Frequency detector as frequency detector
32 Voltage generator as voltage generator
33 Voltage detector as voltage detector
42 Command Recognition Unit
CKE, / CS, / RAS, / CAS, / WE control signal
INTDPD1 power down mode signal
INTDPD2 mode extension signal
MON1, MON2 detection signal
MRS command
OSC1 oscillation signal
VEXT External power supply voltage
VINT, VINT1, VINT2, Vpp Internal power supply voltage
VR voltage signal

Claims (10)

An internal power supply generating circuit that generates an internal power supply voltage and supplies the internal power supply voltage to an internal circuit; and a mode control circuit that generates a power down mode signal based on an input control signal; When the power supply mode is turned off, the internal power supply generation circuit is inactivated to stop generation of the internal power supply voltage, and when the power down mode signal is off, the internal power supply generation circuit is activated to set the internal power supply voltage to a predetermined voltage value. In the semiconductor device to be restored,
An internal timer that generates a mode extension signal by measuring an elapsed time after the power-down mode signal is turned off and extending an on-period of the power-down mode signal by a predetermined time,
A semiconductor device, wherein the mode extension signal is input to at least a part of circuits of the internal circuit which operate by receiving two power supply voltages including the internal power supply voltage, and deactivate the circuit. An internal power supply generating circuit that generates an internal power supply voltage and supplies the internal power supply voltage to an internal circuit; and a mode control circuit that generates a power down mode signal based on an input control signal; When the power supply mode is turned off, the internal power supply generation circuit is inactivated to stop generation of the internal power supply voltage, and when the power down mode signal is off, the internal power supply generation circuit is activated to set the internal power supply voltage to a predetermined voltage value. In the semiconductor device to be restored,
The power-down mode signal includes frequency detection means for detecting that an oscillation signal of an oscillating unit that is operated by being supplied with the internal power supply voltage has reached a predetermined frequency, based on a detection signal output from the frequency detection means. A signal generation circuit that generates a mode extension signal in which the ON period is extended by a predetermined time,
A semiconductor device, wherein the mode extension signal is input to at least a part of circuits of the internal circuit which operate by receiving two power supply voltages including the internal power supply voltage, and deactivate the circuit. An internal power supply generating circuit that generates an internal power supply voltage and supplies the internal power supply voltage to an internal circuit; and a mode control circuit that generates a power down mode signal based on an input control signal; When the power supply mode is turned off, the internal power supply generation circuit is inactivated to stop generation of the internal power supply voltage, and when the power down mode signal is off, the internal power supply generation circuit is activated to set the internal power supply voltage to a predetermined voltage value. In the semiconductor device to be restored,
Voltage generating means for outputting a voltage signal whose voltage level gradually increases after the power-down mode signal is turned off, and voltage detecting means for detecting that the voltage signal has risen to a predetermined voltage or more, the voltage detecting means A signal generation circuit that generates a mode extension signal obtained by extending an ON period of the power-down mode signal by a predetermined time based on a detection signal output from
A semiconductor device, wherein the mode extension signal is input to at least a part of circuits of the internal circuit which operate by receiving two power supply voltages including the internal power supply voltage, and deactivate the circuit. An internal power supply generating circuit that generates an internal power supply voltage and supplies the internal power supply voltage to an internal circuit; and a mode control circuit that generates a power down mode signal based on an input control signal; When the power supply mode is turned off, the internal power supply generation circuit is inactivated to stop generation of the internal power supply voltage, and when the power down mode signal is off, the internal power supply generation circuit is activated to set the internal power supply voltage to a predetermined voltage value. In the semiconductor device to be restored,
A command recognition unit that recognizes a predetermined command based on a control signal input from the outside of the apparatus, wherein a predetermined command is externally applied to the ON period of the power-down mode signal based on an output signal of the command recognition unit A signal generation circuit that generates a mode extension signal extended to
A semiconductor device, wherein the mode extension signal is input to at least a part of circuits of the internal circuit which operate by receiving two power supply voltages including the internal power supply voltage, and deactivate the circuit. 5. The semiconductor device according to claim 4, wherein the signal generation circuit includes a flip-flop circuit to which an output signal of the command recognition unit and the power down mode signal are input, in addition to the command recognition unit. . The flip-flop circuit has a set input unit for turning on the mode extension signal, and a reset input unit for turning off the mode extension signal. The power input mode signal is input to the set input unit. 6. The semiconductor device according to claim 5, wherein an output signal of the command recognition unit is input to the reset input unit. 7. The semiconductor device according to claim 1, further comprising a level shift circuit that performs voltage conversion between the internal power supply voltage and an external power supply voltage as a part of the internal circuit. The internal power supply generating circuit generates a first internal power supply voltage and a second internal power supply voltage different from the first internal power supply voltage,
7. The circuit according to claim 1, further comprising a level shift circuit that performs voltage conversion between the first internal power supply voltage and the second internal power supply voltage as a part of the internal circuit. Semiconductor device. An internal power supply generating circuit for generating an internal power supply voltage and supplying the internal power supply voltage to an internal circuit; and a power down mode signal for activating or deactivating the internal power supply generation circuit based on an input control signal. And a mode control circuit for generating a control signal.
Deactivating the internal power supply generating circuit to change the internal power supply voltage from a first potential level to a second potential level when the power down mode signal is on;
Activating the internal power supply generating circuit to return the internal power supply voltage from a second potential level to a first potential level when the power down mode signal is off;
At least a part of the internal circuit that operates by measuring an elapsed time after the power-down mode signal is turned off by using an internal timer and supplying two power supply voltages including the internal power supply voltage by an output signal of the internal timer. Deactivating the semiconductor device for a predetermined time. An internal power supply generating circuit for generating an internal power supply voltage and supplying the internal power supply voltage to an internal circuit; and a power down mode signal for activating or deactivating the internal power supply generation circuit based on an input control signal. And a mode control circuit for generating a control signal.
Deactivating the internal power supply generating circuit to change the internal power supply voltage from a first potential level to a second potential level when the power down mode signal is on;
Activating the internal power supply generating circuit to return the internal power supply voltage from a second potential level to a first potential level when the power down mode signal is off;
After the power down mode signal is turned off, two internal power supply voltages including the internal power supply voltage are supplied to operate the internal circuit until a predetermined command for shifting to an operation mode other than the power down mode is recognized. Deactivating at least a part of the circuit.

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