JP2004251895A - Quality evaluation method and generation method for delay fault inspecting series, delay fault simulation method and delay fault inspecting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a quality evaluation method for delay fault inspecting series which can precisely evaluate the quality of delay fault inspecting series by taking a design delay value of a signal route which defines a delay fault into consideration. <P>SOLUTION: The quality evaluation method for delay fault inspecting series excludes a delay fault which has a delay value lower than a predetermined design delay value out of the objects of the delay faults. The number of the remaining delay faults is used as a reference standard. An object to be compared is the number of delay faults which are detected by the quality evaluation method for delay fault inspecting series. By using a default detection ratio, which is the ratio of the object to be compared to the reference standard, quality of delay fault inspecting series is evaluated. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a technology for evaluating quality representing a failure inspection capability of a test sequence used when performing a delay failure inspection of a semiconductor integrated circuit.

  2. Description of the Related Art The rapid progress of the miniaturization technology of a semiconductor process in recent years has rapidly increased the scale and complexity of a semiconductor integrated circuit, which has made inspection of a semiconductor integrated circuit more difficult. In order to deal with this problem, a design method for facilitating inspection by a scan method or the like has become popular as a means for facilitating inspection of a semiconductor integrated circuit, and a fault represented by a stuck-at fault model can be efficiently inspected. Became. When detecting faults assumed by the stuck-at fault model, the fault detection ability does not depend on the clock frequency.Conventionally, when performing a scan test, conventionally, a clock frequency lower than the actual operating speed is generally used. Has been done.

However, with the progress of the miniaturization of semiconductor processes, process variations have become apparent, and inspection using only a low clock frequency using the conventional scan method cannot guarantee sufficient inspection quality. Inspections that take delay into account, such as a delay failure inspection technique using a clock frequency, have become necessary.
JP-A-9-269959

  Conventionally, a failure detection rate indicating the quality of a test sequence for a delay failure is calculated by the following formula.

ところで、この故障検出率では、どの遅延故障も重要度が等しいと見なされている。そのため、式（１）の故障検出率は、検査系列の実際の故障検査に対する品質を十分に反映できていない、という問題がある。この問題を図を用いて具体的に説明する。

By the way, in this fault detection rate, all the delay faults are regarded as having equal importance. Therefore, there is a problem that the failure detection rate of the equation (1) does not sufficiently reflect the quality of the test sequence with respect to the actual failure inspection. This problem will be specifically described with reference to the drawings.

FIG. 14 is a diagram showing characteristics of delay faults defined on a semiconductor integrated circuit. The lengths of the arrows shown on the right side of the signal paths b _{1 to} b ₆ indicate design delay values of the signal paths. Further, a dotted line on the right side of the figure represents a value of one clock rate of the semiconductor integrated circuit.

In general, the larger the designed delay value of a signal path (closer to one clock rate), the greater the possibility that the signal path will cause a delay fault. Thus, in FIG. 14, that the signal path b ₃ is large can cause delay faults than the signal path b ₆ is clear. Therefore, inspection for detecting a delay fault defined signal path b _3, as compared to the test for detecting a delay fault defined signal path b _6, the quality of the inspection can be said that higher.

However, the in fault coverage according to formula (1), even when detecting a delay fault of the signal path b _3, even when detecting delay faults in the signal path b _6, and also detected a single delay fault Treated and their quality is considered equivalent. For example, assume that defines a delay fault one by one on each of the signal path b ₁ ~b _6. When a fault on the signal paths b _{1 to} b ₃ that is likely to cause a delay fault is detected, the fault detection rate is:
(3/6) × 100 [%] = 50%
It becomes. On the other hand, even when a fault is detected on the signal path b ₄ ~b ₆ possibility is small resulting in delay fault, is the failure detection rate,
(3/6) × 100 [%] = 50%
It becomes. Although both have different possibilities of causing a delay fault, the fault detection rates are equal to each other.

And inspection of large signal path b ₁ ~b ₃ above the fault detection delay value, in a test for detecting a fault of small signal path b ₄ ~b ₆ delay value, it is clear that the former is higher quality . Therefore, equation (1) for the failure detection rate does not correctly reflect the quality of the inspection. As a result, the quality of the test sequence used for the test is erroneously evaluated.

  In order to solve such a problem, the present invention considers a delay fault test by considering a design delay value on a signal path defining a delay fault when evaluating the quality of a test sequence for the delay fault. It is an object of the present invention to provide a method for evaluating the quality of a delay fault inspection sequence, which can evaluate the quality of the sequence with higher accuracy.

  In order to achieve the above object, the present invention takes the following measures.

  As a first solution, the quality evaluation method of the delay fault test sequence according to the present invention excludes, among the defined delay faults, delay faults having a delay value equal to or less than a predetermined delay value in design as a fault test target. Then, the number of delay faults in the remaining target is used as a reference. The comparison target is the number of delay faults for which the delay fault test sequence can be detected. The quality of the delayed fault test sequence is evaluated using the ratio between the two, that is, the ratio of the comparison target to the comparison standard as the fault detection rate.

  The operation of this configuration is as follows. The fault detection rate is calculated after excluding delay faults having a low degree of influence on quality evaluation, instead of considering all the defined delay faults with equal importance. Then, since the quality evaluation of the delayed fault test sequence is performed based on the fault detection rate calculated in this way, the degree of influence on the fault detection rate of a delayed fault having a high possibility of actually generating a fault is increased. . As a result, it is possible to improve the accuracy of the quality evaluation of the delay fault test sequence.

  As a second solution, the method for evaluating the quality of a delay fault test sequence according to the present invention weights each of the defined delay faults. The sum of the weights of the delay faults is used as a reference. The comparison target is the sum of the weights of the delay faults for which the delay fault test sequence has been detected. The quality of the delayed fault test sequence is evaluated using the ratio of the two, that is, the ratio of the comparison target to the comparison standard as the fault detection rate.

  The operation of this configuration is as follows. Rather than assuming all the significance of the defined delay faults as equal, weighting is performed according to the degree of influence on the quality evaluation, and the fault detection rate is calculated using the sum of the weights as an index. Then, since the quality evaluation of the delayed fault test sequence is performed based on the fault detection rate calculated in this way, the degree of influence on the fault detection rate of a delayed fault having a high possibility of actually generating a fault is increased. . As a result, it is possible to improve the accuracy of the quality evaluation of the delay fault test sequence.

  In the above, there are several aspects of the weight.

One is a numerical value indicating the magnitude of the 'design delay value of the signal path in which the delay fault is defined' with respect to the 'design value of the timing in the signal path in which the delay fault is defined'. Some use a 'design delay value of a signal path in which a delay fault is defined'. There are a plurality of delay fault a ₁ ~a _n, the delay value on the respective design and T ₁ through T _n. Delay faults a ₁ ~a delay value on the delay fault test sequence of delay fault could be detected design of _n and _{t 1 ~t m (m ≦ n} ). Delay value T ₁ through T _n the sum of the sigma _T, when the sum of the delay value t ₁ ~t _m and sigma _t, the fault coverage eta, is η = σ _t / σ _T.

第１の解決手段の場合には、品質評価に対する影響の度合いが低い遅延故障を除外したが、重み付けの場合にはそのような除外はしない。定義されたすべての遅延故障の遅延値を故障検出率に反映する。そのため、遅延故障検査系列の品質評価をさらに高精度なものにできる。

In the case of the first solution, delay faults having a low degree of influence on the quality evaluation are excluded, but in the case of weighting, such exclusion is not performed. The delay values of all the defined delay faults are reflected in the fault detection rate. Therefore, the quality evaluation of the delay fault test sequence can be made even more accurate.

Instead of the delay values T _i and t _j , the number of gate stages of the delay faults a _i and a _j may be used.

The other uses, as the weight, a product of the 'design delay value of the signal path in which the delay fault is defined' and the 'physical path length of the signal path in which the delay fault is defined'. There is. The physical path lengths of the signal paths of the plurality of delay faults a _{1 to an} are _denoted by Q _{1 to} Q _n . The physical path length of the signal path of the delay fault for which the delay fault test sequence can be detected is defined as q ₁ to q _m (m ≦ n). Each of the products of each and path length Q ₁ to Q _n of the delay value T ₁ through T _n is the _{T 1 · Q 1 ~T n ·} Q n. Let the sum of these products be σ _Q. Each of the products of each and path length q ₁ to q _m delay value t ₁ ~t _m is _{t 1 · q 1 ~t m ·} q m. Let the sum of these products be σ _q . The failure detection rate η is η = σ _q / σ _Q.

この場合も、品質評価に対する影響の度合いが低い遅延故障を除外することはしない。定義されたすべての遅延故障の遅延値を故障検出率に反映する。そしてさらに、遅延値と経路長との２要素を加味する。以上の相乗により、遅延故障検査系列の品質評価を一層高精度なものにできる。

Also in this case, a delay fault having a low degree of influence on the quality evaluation is not excluded. The delay values of all the defined delay faults are reflected in the fault detection rate. Further, two factors of the delay value and the path length are added. By the above synergy, the quality evaluation of the delay fault inspection sequence can be made with higher accuracy.

The other is, as the weight, the product of the 'design delay value of the signal path in which the delay fault is defined' and the 'physical wiring area on the path of the signal path in which the delay fault is defined'. Some use. The physical wiring area of the plurality of delay faults a ₁ ~a _n respective signal paths and H ₁ to H _n. The physical wiring area of the delay fault signal path delay fault test sequences can be detected and _{h 1 ~h m (m ≦ n} ). Each with each of the products of the wiring area H ₁ to H _n of the delay value T ₁ through T _n is the _{T 1 · H 1 ~T n ·} H n. Let the sum of these products be σ _H. Each and each product of the wiring area h ₁ to h _m delay value t ₁ ~t _m is _{t 1 · h 1 ~t m ·} h m. Let the sum of these products be σ _h . The failure detection rate η is η = σ _h / σ _H.

この場合も、品質評価に対する影響の度合いが低い遅延故障を除外することはしない。定義されたすべての遅延故障の遅延値を故障検出率に反映する。そしてさらに、遅延値と配線面積との２要素を加味する。以上の相乗により、遅延故障検査系列の品質評価を一層高精度なものにできる。

Also in this case, a delay fault having a low degree of influence on the quality evaluation is not excluded. The delay values of all the defined delay faults are reflected in the fault detection rate. Further, two elements of the delay value and the wiring area are taken into account. By the above synergy, the quality evaluation of the delay fault inspection sequence can be made with higher accuracy.

Still another type uses the product of the following two elements as the weight. One factor is the 'design delay value of the signal path in which the delay fault is defined'. Another factor is the result of adding the element area to 'physical wiring area on the path of the signal path in which the delay fault is defined'. That is,
It is assumed that the design delay value of the signal path × (physical wiring area + element area) = weight.

The physical wiring area of the plurality of delay faults a ₁ ~a _n respective signal paths and H ₁ to H _n, each element area (gate area) and G ₁ ~G _n. The physical wiring area of the delay fault signal path delay fault test sequences can be detected and h ₁ to h _m, each element area (gate area) and _{g 1 ~g m (m ≦ n} ). The sum of each gate area G ₁ ~G _n of wiring area H ₁ to H _n, the product of the result of multiplying each of the delay value T ₁ through T _{n is, T 1 · (H 1 +} G 1) ~T n a _{· (H n + G n)} . Let σ _HG be the sum of these products. The sum of each gate area g ₁ to g _m of wiring area h ₁ to h _n, the product of the result of multiplying each of the delay value t ₁ ~t _{m is, t 1 · (h 1 +} g 1) ~t m (H _m + g _m ). Let the sum of these products be σ _hg . The failure detection rate η is η = σ _hg / σ _HG .

この場合も、品質評価に対する影響の度合いが低い遅延故障を除外することはしない。定義されたすべての遅延故障の遅延値を故障検出率に反映する。そしてさらに、配線面積と素子面積と遅延値との３要素を加味する。以上の相乗により、遅延故障検査系列の品質評価をさらに一層高精度なものにできる。

Also in this case, a delay fault having a low degree of influence on the quality evaluation is not excluded. The delay values of all the defined delay faults are reflected in the fault detection rate. Further, three elements of the wiring area, the element area, and the delay value are added. With the above synergy, the quality evaluation of the delay fault inspection sequence can be made even more accurate.

  The weight may be further multiplied by the defect density. The defect density is calculated statistically from a yield analysis at a factory or the like. The defect density is usually constant for each delay fault. However, the quality evaluation of the delayed fault inspection sequence can be made even more accurate by taking into account the small difference in defect density between them.

  In connection with the above-described method for evaluating the quality of a delayed fault test sequence, the method for generating a delayed fault test sequence according to the present invention uses any one of the above-described methods for evaluating the quality of a delayed fault test sequence for the generated delayed fault test sequence. To calculate the failure detection rate. According to this, the generation of the delay fault test sequence can be performed with higher accuracy than in the related art.

  In addition, in relation to the above-described method for evaluating the quality of a delay fault test sequence, the delay fault simulation method according to the present invention provides a method for evaluating the quality of any of the above-described delay fault test sequences for a given delay fault test sequence. This is used to calculate the failure detection rate. According to this, the simulation of the delay fault can be performed with higher accuracy than the conventional technology.

  Further, in connection with the above-described method for evaluating the quality of a delayed fault test sequence, the fault test method according to the present invention provides a method of testing any one of the above-described delay fault test sequences used for testing in a semiconductor integrated circuit test process. The failure detection rate is calculated by using the quality evaluation method of the failure inspection sequence. According to this, the failure inspection of the semiconductor integrated circuit can be performed with higher accuracy than the conventional technology.

  As described above in detail, according to the present invention, the importance of each delay fault is determined by considering the 'design delay value on the signal path where the delay fault is defined'. It can be reflected in quality evaluation. As a result, the accuracy of the quality evaluation of the delay fault test sequence can be improved. Further, a delayed fault having a high possibility of actually generating a fault can have a greater influence on the fault detection rate. That is, when such a failure is detected, the degree of improvement in the failure detection rate is large, and conversely, when it is not detected, the degree of reduction in the failure detection rate can be increased.

  In general, there are two types of delay faults on one signal path, a rising transition fault and a falling transition fault, and a delay fault is represented by a combination of a signal path and a transition type. However, hereinafter, for convenience of description, the description will be made assuming that the type of transition is omitted and one delay fault is defined on one signal path.

(First Embodiment)
The present embodiment relates to a specific implementation method for improving the accuracy of the quality evaluation of a delay fault test sequence by excluding a fault having a small value in detecting the delay fault from the quality of the delay fault test sequence. belongs to.

  First, an embodiment of a quality evaluation method for the delayed fault test sequence generated in the delayed fault test sequence generation processing will be described.

(Quality evaluation of delayed fault inspection sequence)
FIG. 1 is a flowchart showing a delay fault test sequence generation method according to the first embodiment of the present invention. 1 is logic circuit data to be tested, 2 is delay fault definition information defined in the logic circuit, 3 is a delay fault test sequence generation operation, 4 is a delay fault test sequence for testing a delay fault of a logic circuit, 5 Indicates the fault coverage obtained as a result of the delayed fault test sequence generation operation.

  FIG. 3 is a flowchart showing details of the delay fault test sequence generation operation 3. 31 is an operation for setting a predetermined delay value Dmin, 32 is an operation for excluding, among all the defined faults, ones in which each 'design delay value of the signal path in which the delay fault is defined' is smaller than the predetermined delay value Dmin, 33 Denotes a test sequence generation operation for generating a test sequence for each defined delay fault, 34 denotes an operation for counting the number of detected delay faults, and 35 denotes an operation for calculating a fault detection rate by the following equation.

なお、式（１４）において、全故障数は遅延故障定義情報２で定義された全定義故障から、操作３２において信号経路の設計上の遅延値が所定の遅延値Ｄminよりも小さい信号経路上の故障を除外した数であり、また、検出故障数は全故障のうち検査系列生成操作３３において検査系列生成に成功した故障の数である。

In equation (14), the total number of faults is calculated from the total faults defined in the delay fault definition information 2 on the signal path where the design delay value of the signal path in operation 32 is smaller than the predetermined delay value Dmin. The number of faults is excluded, and the number of detected faults is the number of faults for which test sequence generation has succeeded in the test sequence generation operation 33 among all faults.

FIG. 5 is a diagram showing characteristics of delay faults defined on a semiconductor integrated circuit. The lengths of the arrows shown to the right of the delay faults a _{1 to} a ₆ indicate the magnitudes of the 'design delay values of the signal paths in which the delay faults are defined', respectively, and are attached above the arrows. A numerical value such as 9 ns indicates a specific delay value. Further, a dotted line on the right side of the figure represents a value of one clock rate of the semiconductor integrated circuit.

  Hereinafter, the present embodiment will be described with reference to FIGS. 1, 3, and 5. FIG.

First, a delay fault test sequence generation operation 3 is executed using the given logic circuit data 1 and delay fault definition information 2. It is assumed that the delay fault definition information 2 includes the delay faults a _{1 to} a ₆ shown in FIG. In the delay fault test sequence generation operation 3, first, a predetermined delay value Dmin is set in operation 31. The value of the predetermined delay value Dmin is set to a value sufficiently smaller than the value of one clock rate. Now, it is assumed that the value of one clock rate is 10 ns and the predetermined delay value Dmin is 3 ns. Next, in operation 32, comparison determination is performed. Because of the delay fault a ₁ ~a ₆ is whole definition failure, delay value in design of the signal path delay fault a ₆ is defined smaller a 2ns than the predetermined delay value Dmin, the delay fault a ₆ is excluded. As a result, the total fault to be processed becomes delay fault a ₁ ~a _5. Subsequently, in operation 33, it is assumed that the test sequence generation operation is performed on the delay faults a _{1 to} a ₅ , and as a result, only the delay faults a ₄ and a ₅ succeed (ie, detect) the test sequence generation. From this result, in operation 34, the number of detected faults is counted as two. Finally, in operation 35, the failure detection rate is (2/5) × 100 = 40%
Is calculated. Then, the data of the fault detection rate 5 and the data of the generated delayed fault test sequence 4 are output.

[Quality evaluation of failure simulation]
Next, an embodiment of a quality evaluation method for a given delay fault test sequence in a delay fault simulation process will be described.

  FIG. 2 is a flowchart showing a delay fault simulation method according to the first embodiment of the present invention. Reference numeral 6 denotes a delay fault simulation operation, and the other reference numerals corresponding to those in FIG. 1 indicate the same as those in FIG.

  FIG. 4 is a flowchart showing details of the delay fault simulation operation 6. 4, a failure simulation execution operation 36 is performed instead of the test sequence generation operation 33 of FIG. 3, and the other operations are the same as those of FIG.

  Hereinafter, a second example of the present embodiment will be described with reference to FIGS. 2, 4, and 5. FIG.

First, a delay fault simulation operation 6 is performed using the given logic circuit data 1, delay fault definition information 2, and delay fault test sequence 4. It is assumed that the delay fault definition information 2 includes the delay faults a _{1 to} a ₆ shown in FIG. In the delay fault simulation operation 6, first, a predetermined delay value Dmin is set in operation 31. It is assumed that the value of the predetermined delay value Dmin is set to 3 ns as in the first embodiment. Next, in operation 32, comparison determination is performed. Because of the delay fault a ₁ ~a ₆ is whole definition failure, delay value in design of the signal path delay fault a ₆ is defined smaller a 2ns than the predetermined delay value Dmin, the delay fault a ₆ is excluded. As a result, the total fault to be processed becomes delay fault a ₁ ~a _5. In subsequent operation 36, a fault simulation using the delay fault test sequences 4 relative delay faults a ₁ ~a ₅ is executed, and as a result, only the delay fault a ₄ and a ₅ are detected. From this result, in operation 34, the number of detected faults is counted as two. Finally, in operation 35, the failure detection rate is (2/5) × 100 = 40%
Is calculated. Finally, data of the failure detection rate 5 is output.

[Evaluation of the present embodiment]
Next, a comparison between the present invention and the prior art will be made.

  FIG. 13 shows a flowchart of a quality evaluation method for a delayed fault test sequence generated in a delayed fault test sequence generation process according to the prior art, which corresponds to FIG. 2 of the present invention. In the drawing, the same reference numerals as those in FIG. 2 indicate the same components as those in FIG.

Hereinafter, the operation of the prior art will be described with reference to FIGS. 1, 5 and 13. In the prior art, all the faults given by the delay fault definition information 2 are to be subjected to test sequence generation. Then, test sequence generation is executed for the delay faults a _{1 to} a ₆ . Here, as a result of the test sequence generation, it is assumed that the test sequence generation is successful (that is, detected) for the delay faults a _{4 to} a ₆ . From this result, the number of detected faults is counted as three in operation 34, and the fault detection rate in operation 35 is (3/6) × 100 = 50%
Is calculated.

When calculating the fault coverage in the prior art, the delay fault a ₁ also delay fault a ₆ are treated exactly equally, detected actually only delay faults a ₄ ~a ₆ possibility is small resulting in delay fault Thus, the delay faults a _{1 to} a ₃ that are likely to cause a delay fault have not been detected. Nevertheless, the possibility of occurrence of a delay fault for each delay fault (occurrence probability) is not considered at all, so that the fault detection rate is excessively high.

However, in this embodiment, to exclude practically as an inspection subject to the exclusion of delay fault a ₆ possibility is small resulting in delay fault, the magnitude of the potential to cause delay fault is reflected in the failure detection rate, The fault detection rate is lower than that of the prior art, and the quality of the delayed fault test sequence can be evaluated with higher accuracy.

(Second embodiment)
The present embodiment improves the accuracy of the quality evaluation of the delay fault test sequence by performing the quality evaluation of the delay fault test sequence by using the design delay value on the signal path defining the delay fault. It is about a simple implementation method.

  FIG. 6 is a flowchart showing a method of evaluating the quality of a delayed fault test sequence showing details of the delayed fault test sequence generation operation 3 in FIG. 1 according to the present invention. In the drawing, the same reference numerals as those in FIG. 2 indicate the same components as those in FIG. Reference numeral 33 denotes an operation for generating a test sequence for each defined delay fault, and reference numeral 37 denotes an operation for calculating a fault detection rate by the following equation.

図７は信号経路上の配線面積とゲート面積（素子面積）の算出方法を説明するための半導体集積回路のレイアウト図である。５１，５２はフリップフロップ、５３〜５５は論理ゲート（ＡＮＤ論理）、５６〜５９は配線を示す。

FIG. 7 is a layout diagram of a semiconductor integrated circuit for explaining a method of calculating a wiring area and a gate area (element area) on a signal path. Reference numerals 51 and 52 denote flip-flops, 53 to 55 denote logic gates (AND logic), and 56 to 59 denote wirings.

FIG. 8 shows the total area value of the wiring area and the gate area on the signal path in each of the signal paths in which the delay faults a _{1 to} a ₆ are defined. The length of the arrow shown on the right side of each of the delay faults a _{1 to} a ₆ indicates the magnitude of the total value of the area of the signal path in which each delay fault is defined, such as 800 μm ² added above each arrow. Indicates a specific value.

FIG. 9 shows the total wiring length on the signal path in each of the signal paths in which the delay faults a _{1 to} a ₆ are defined. The length of the arrows shown on the right side of the delay faults a _{1 to} a ₆ indicates the size of each 'total wiring length of the signal path in which the delay fault is defined', such as 5000 μm added above each arrow. Indicates a specific value.

FIG. 10 is a diagram illustrating characteristics of delay faults defined on a semiconductor integrated circuit. In the figure, the same symbols as those in FIG. The values of one clock rate of the delay faults a _{1 to} a ₄ , the delay fault a ₅ , and the delay fault a ₆ are 10 ns, 8 ns, and 2.5 ns, respectively, and are indicated by dotted lines in the figure.

FIG. 11 is a diagram illustrating the characteristics of the delay fault defined on the semiconductor integrated circuit. In the figure, the same symbols as those in FIG. 5 indicate the same as those in FIG. The values of one clock rate of the delay faults a _{1 to} a ₄ and the delay faults a _{5 to} a ₆ are 10 ns and 2.5 ns, respectively, and are indicated by dotted lines in the figure. The signal path delay fault a ₅ is defined, the signal during the three clock period that may be propagated, and a multi-cycle path of the so-called three cycles.

  Hereinafter, this embodiment will be described with reference to FIGS. 1, 3, 5, 5, 7, 8, 9, 10, and 11.

  The operation of the entire method of evaluating the quality of a delayed fault test sequence in FIG. 1 is the same as that of the first embodiment, and thus the description thereof will be omitted, and only the details of the delayed fault test sequence generating operation 3 will be described.

Since all the faults given by the delayed fault definition information 2 are subject to test sequence generation, the test sequence generation operation 33 executes test sequence generation for the delay faults a _{1 to} a ₆ , and as a result, It is assumed that test sequence generation has been successful (ie, detected) for a _{4 to} a ₆ . Next, the operation 37, the weight sum of the delay fault a ₁ ~a ₆ is whole define failure, the sum of the weights of the delay fault a ₄ ~a ₆ detected by the test sequence generation operation 33 respectively calculated, The failure detection rate is calculated using equation (15).

  As a specific example of the weight, a description will be given of a case where a 'design delay value of a signal path in which each delay fault is defined' is used as shown in FIG.

[Specific example 1 of weight]
As a specific example of the weight, when the relative value of the 'design delay value of the signal path in which the delay fault is defined' to the 'design value of the signal path in which the delay fault is defined' is used. Will be described. 'Required value in timing design of signal path with delay fault defined' is the value of time constraint such that signal propagation must be completed in a signal path with delay fault defined within a certain time For example, the clock rate value for the signal path where the delay fault is defined, or when the signal path where the delay fault is defined is a multi-cycle path, is represented by the product of the clock rate for the signal path and the number of multi-cycles. Value. Here, a description will be given using a clock rate as a “required value in timing design of a signal path in which a delay fault is defined”.

For example the weight of delay faults a _1, since the delay values of the design of the signal path the failure is defined is 9 ns, using a figure of 9 as a weight. In this case, the sum of the weights of all the defined faults calculated in operation 37 is
(9 + 8 + 9 + 5 + 7 + 2) = 40
And the sum of the weights of the delay faults a _{4 to} a ₆ detected in the test sequence generation operation 33 is
(5 + 7 + 2) = 14
It is. Therefore, the failure detection rate is obtained from the equation (15) as follows.
(14/40) × 100 = 35%
Is calculated.

In the present embodiment, since the detected delay faults are often those having a small design delay value, the fault detection rate is smaller than the fault detection rate 50% calculated by the conventional technology as in the first embodiment. It can be seen that a more accurate quality evaluation method for the delay fault test sequence has been realized. Also, unlike Embodiment 1, each “delay value of a signal path in which a delay fault is defined” is determined without ignoring a fault on a signal path having a small design delay value such as a delay fault a _6. Since this can be reflected in the failure detection rate, a quality evaluation method of a delayed failure inspection sequence with higher accuracy than in the first embodiment can be realized.

  In this specific example, the relative value of the design delay value of the signal path in which each fault is defined with respect to the clock rate (10 ns) is used. The same effect can be obtained by using the delay value of

[Specific example 2 of weight]
Next, another specific example of the weight will be described. This takes into account the 'design delay value of the signal path in which the delay fault is defined' and the probability that a defect will occur on the signal path. In this case, a weight represented by the following equation (16) is used.

欠陥発生確率×係数は、故障発生頻度とみなすことができる。

The defect occurrence probability × coefficient can be regarded as a failure occurrence frequency.

  The defect occurrence probability is further expressed by the following equation (17).

信号経路上の（配線面積＋ゲート面積）は、図７を例に取ると、フリップフロップ５１，５２間の信号経路上の配線５６〜５９の総面積と、ゲート５３〜５５の総面積の和で算出することができる。このようにして算出した遅延故障ａ₁〜ａ₆が定義された信号経路上の（配線面積＋ゲート面積）の値を図８に示している。

In the example of FIG. 7, (wiring area + gate area) on the signal path is the sum of the total area of wirings 56 to 59 on the signal path between flip-flops 51 and 52 and the total area of gates 53 to 55. Can be calculated. FIG. 8 shows the value of (wiring area + gate area) on the signal path in which the delay faults a _{1 to} a ₆ thus calculated are defined.

  The value of the coefficient of the equation (16) is set to 1 in the present embodiment, and the defect density in the equation (17) is statistically calculated from a yield analysis at a factory or the like. write. Assuming that the value of α is constant on the semiconductor integrated circuit, the failure detection rate is calculated by the following equation (18) from equations (15) to (17).

ここでは、例えば遅延故障ａ₁の重みは、図５よりこの故障が定義される信号経路の設計上の遅延値９ｎｓと、また、図８より信号経路上の（配線面積＋ゲート面積）の値１０００μｍ²を用いて、
９×１０００＝９０００
として計算される。したがって、操作３７で計算される全定義故障の重みの総和は、
(9×1000+8×600+9×800+5×500+7×600+2×100)=27900
であり、検査系列生成操作３３で検出された遅延故障ａ₄〜ａ₆の重みの総和は、
（５×５００＋７×６００＋２×１００）＝６９００
である。したがって、故障検出率は式（１８）から、
６９００／２７９００×１００＝２４．７％
と算出される。

Here, for example, the weight of the delay fault a ₁ is, as shown in FIG. 5, the designed delay value 9 ns of the signal path in which this fault is defined, and the value of (wiring area + gate area) on the signal path from FIG. Using 1000 μm ² ,
9 × 1000 = 9000
Is calculated as Therefore, the sum of the weights of all the defined faults calculated in operation 37 is
(9 × 1000 + 8 × 600 + 9 × 800 + 5 × 500 + 7 × 600 + 2 × 100) = 27900
And the sum of the weights of the delay faults a _{4 to} a ₆ detected in the test sequence generation operation 33 is
(5 × 500 + 7 × 600 + 2 × 100) = 6900
It is. Therefore, the failure detection rate is obtained from the equation (18) as follows.
6900/27900 × 100 = 24.7%
Is calculated.

In this example, since many of the detected delay faults have a small design delay value, the detected fault fault has a value smaller than the fault detection rate of 50% calculated by the conventional technology as in the first embodiment. It can be seen that a quality evaluation method for a delay fault test sequence with a high level of quality has been realized. Also, each “failure on the signal path in which the delay fault is defined” can be performed without ignoring the fault on the signal path having a small design delay value such as the delay fault a ₆ as in the first embodiment. Since this can be reflected in the detection rate, a more accurate quality evaluation method for a delay fault test sequence than in the first embodiment can be realized.

[Specific Example 3 of Weight]
Next, still another specific example of the weight will be described. This uses a simpler value of the total wiring length instead of (wiring area + gate area) in equation (17). In this case, a weight represented by the following equation (19) is used.

式（１９）における総配線長は、図７における配線５６〜５９の長さの和で算出することができ、このようにして算出した遅延故障ａ₁〜ａ₆が定義された信号経路上の総配線長の値を図９に示している。

The total wiring length in the equation (19) can be calculated by the sum of the lengths of the wirings 56 to 59 in FIG. 7, and the delay faults a _{1 to} a ₆ calculated in this way are defined on the defined signal path. FIG. 9 shows the values of the total wiring length.

  In addition, assuming that the value of the defect density α is constant on the semiconductor integrated circuit by replacing Expression (17) with Expression (19), Expression (18) is also replaced by Expression (20) below.

ここでは、例えば遅延故障ａ₁の重みは、図５よりこの故障が定義される信号経路の設計上の遅延値９ｎｓと、また、図９より信号経路上の総配線長の値８０００μｍを用いて、
９×８０００＝７２０００
として計算される。したがって、操作３７で計算される全定義故障の重みの総和は、
(9×8000+8×5000+9×6000+5×3000+7×5000+2×2000)=220000
であり、検査系列生成操作３３で検出された遅延故障ａ₄〜ａ₆の重みの総和は、
（５×３０００＋７×５０００＋２×２０００）＝５４０００
である。したがって、故障検出率は式（２０）から、
５４０００／２２００００×１００＝２４．５％
と算出される。

Here, for example, the weight of the delay fault a ₁ is determined using the designed delay value 9 ns of the signal path in which the fault is defined from FIG. 5 and the total wiring length value 8000 μm on the signal path from FIG. ,
9 × 8000 = 72000
Is calculated as Therefore, the sum of the weights of all the defined faults calculated in operation 37 is
(9 × 8000 + 8 × 5000 + 9 × 6000 + 5 × 3000 + 7 × 5000 + 2 × 2000) = 220,000
And the sum of the weights of the delay faults a _{4 to} a ₆ detected in the test sequence generation operation 33 is
(5 × 3000 + 7 × 5000 + 2 × 2000) = 54000
It is. Therefore, the failure detection rate is obtained from the equation (20) as follows.
54000 / 220,000 × 100 = 24.5%
Is calculated.

In this example, since many of the detected delay faults have a small design delay value, the detected fault fault has a value smaller than the fault detection rate of 50% calculated by the conventional technology as in the first embodiment. It can be seen that a quality evaluation method for a delay fault test sequence with a high level of quality has been realized. Also, each “failure on the signal path in which the delay fault is defined” can be performed without ignoring the fault on the signal path having a small design delay value such as the delay fault a ₆ as in the first embodiment. Since this can be reflected in the detection rate, a more accurate quality evaluation method for a delay fault test sequence than in the first embodiment can be realized. Further, in this example, the use of Expression (20) can reduce the amount of calculation compared to the case of using Expression (18).

[Specific Example 4 of Weight]
Next, still another specific example of the weight will be described. Here, taking a case where the semiconductor integrated circuit has a plurality of clock rates and multi-cycle paths, as a 'request value in the timing design of the signal path in which the delay fault is defined', the The description will be made using a clock rate value and a case where the product is represented by the product of the clock rate for the signal path and the number of multicycles. In addition, each 'delay fault' is defined as a relative value of 'design delay value of signal path where delay fault is defined' with respect to 'design timing requirement value of signal path where delay fault is defined'. The ratio of the 'design delay value of the signal path in which the delay fault is defined' to the 'design value of the signal path timing design' (specifically, the clock rate value, the product of the clock rate and the number of multicycles). The description will be made using the values represented.

For example, as shown in FIG. 10, when the clock rate of the signal path in which the delay faults a _{1 to} a ₄ are defined is 10 ns, the “request value in timing design of the signal path” in which the delay fault a ₁ is defined Can be considered as 10 ns. At this time, the weight of the delay fault a ₁ is represented by a ratio of a design delay value of a signal path in which the fault is defined to a required value in timing design, that is, 9 ns / 10 ns = 0.9. Similarly, since the clock rates of the delay fault a ₅ and the delay fault a ₆ are 8 ns and 2.5 ns, respectively, the weights of the delay fault a ₅ and the delay fault a ₆ are (7 ns / 8 ns) = 0.875, respectively. (2 ns / 2.5 ns) = 0.8. In this case, the sum of the weights of all the defined faults calculated in operation 37 is
(0.9 + 0.8 + 0.9 + 0.5 + 0.875 + 0.8) = 4.775
It is. The sum of the weights of the delay faults a _{4 to} a ₆ detected in the test sequence generation operation 33 is
(5 + 0.875 + 0.8) = 2.175
It is. Therefore, from equation (15),
(2.175 / 4.775) = 45.5%
Is calculated.

Further, as shown in FIG. 11, the clock rate of the signal path delay fault a ₅ is defined is 2.5 ns, when the signal path is a multi-cycle path of 3 cycles, a delay fault a ₅ The 'required value in timing design of signal path' defined can be regarded as (2.5 ns × 3) = 7.5 ns. In this case, the weight of the delay fault a ₅ is represented by (7ns / 7.5ns) = 0.933. In FIG. 11, the weights of the other delay faults a _{1 to} a ₄ and a ₆ are the same as those in the example of FIG.
(0.9 + 0.8 + 0.9 + 0.5 + 0.933 + 0.8) = 4.833
It is. The sum of the weights of a _{4 to} a ₆ detected in the test sequence generation operation 33 is
(0.5 + 0.933 + 0.8) = 2.233
It is. Therefore, from equation (15),
(2.233 / 4.833) = 46.2%
Is calculated.

  In these examples, many of the detected delay faults have a small design delay value, and thus have a value smaller than the fault detection rate of 50% calculated by the conventional technology. That is, it can be seen that a more accurate method for evaluating the quality of the delay fault test sequence has been realized.

Further, unlike the first embodiment, it will not be ignored failure on small signal path delay values on design as delay fault a _6. Each 'delay value of the signal path in which the delay fault is defined' is reflected in the fault detection rate. Therefore, it is possible to realize a method of evaluating the quality of the delay fault test sequence with higher accuracy than in the first embodiment.

  In the specific example of the weights, the clock rate and the multi-cycle path have been described as the required values for the timing design of the signal path, but the AC timing between the external terminal and the inside of the semiconductor integrated circuit has been described. It is clear that the same effect can be obtained by using other general timing constraint values such as values.

  It should be noted that the same effect can be realized by using FIG. 2 instead of FIG. 1 described in the present embodiment, and by using the failure simulation execution operation 36 instead of the test sequence generation operation 33. .

  In addition, in Equations (17) and (18), almost the same effect can be realized by simply using the wiring area instead of (wiring area + gate area).

  Furthermore, substantially the same effect can be obtained by using the number of gate stages of the signal path as a simple expression of the delay value instead of the designed delay value of the signal path used in the present embodiment.

(Third embodiment)
FIG. 12 is a flowchart showing a failure inspection method according to the third embodiment of the present invention. The operations 3 to 6 in the figure are the same as those in FIG. 1 and FIG. 2, and reference numeral 101 denotes a judgment as to whether or not the delayed fault detection rate satisfies a test requirement, and reference numeral 102 denotes a fault test.

  Hereinafter, the present embodiment will be described with reference to FIGS. 3, 4, 6, and 12. FIG.

  First, a delayed fault test sequence generation operation 3 generates a delayed fault test sequence 4 to be used for inspection, and then a delayed fault simulation operation 6 calculates a fault detection rate 5 of the delayed fault test sequence 4. In the delay fault simulation operation 6, more specifically, the method described in the first embodiment or the second embodiment (using the operation 33 in FIG. 3 or 6 in which the operation 33 is replaced with the operation 36) is used. To calculate the failure detection rate. Next, in operation 101, using the failure detection rate 5 output from the delayed failure simulation operation 6, it is determined whether or not the failure detection rate has reached a value required for inspection, and if the result is positive (Yes). ), The operation shifts to the operation of the failure inspection 102, and if the answer is negative (No), the delay fault inspection sequence having a higher fault detection rate is generated again by, for example, starting over from the delay error inspection sequence generation operation 3 again. Perform the operation you want.

  In the case of using the failure detection rate calculation according to the conventional technology, even if a high delayed failure detection rate is calculated, it is not possible to judge from the numerical value alone whether or not the quality of the delayed fault inspection sequence is sufficiently high, so that it is complemented. It is necessary to examine the test sequence or test method. However, this causes an increase in the number of steps involved in the failure inspection and instability of the quality of the failure inspection.

  On the other hand, when the method for evaluating the quality of the delay fault test sequence according to the present invention is used, the calculated delay fault detection rate accurately represents the quality of the delay fault test sequence, so that the fault test operation is started. Good or bad can be easily determined, the number of steps involved in the failure inspection can be reduced, and the quality of the failure inspection can be stably set to a high level.

5 is a flowchart illustrating a method for generating a delay fault test sequence according to the first embodiment of the present invention. 4 is a flowchart illustrating a delay fault simulation method according to the first embodiment of the present invention. A flowchart for explaining in detail the delay fault test sequence generation operation of the flowchart of FIG. 1 according to the first embodiment of the present invention 2 is a flowchart for explaining in detail the delay fault simulation operation of the flowchart of FIG. 2 according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating delay fault characteristics defined on a semiconductor integrated circuit according to the first embodiment of the present invention; A flowchart for explaining in detail the delay fault test sequence generation operation of the flowchart of FIG. 1 according to the second embodiment of the present invention Layout diagram of a semiconductor integrated circuit for describing a method of calculating a wiring area and a gate area on a signal path according to a second embodiment of the present invention The figure which shows the total area value of the wiring area and the gate area on the signal path in each of the signal paths in which the delay fault is defined in the second embodiment of the present invention. The figure which shows the total wiring length on the signal path in each of the signal paths in which the delay fault was defined in the second embodiment of the present invention. FIG. 10 is a diagram illustrating characteristics of delay faults defined on a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 10 is a diagram illustrating characteristics of delay faults defined on a semiconductor integrated circuit according to a second embodiment of the present invention. 3 is a flowchart illustrating a failure inspection method according to a third embodiment of the present invention. Flowchart for explaining a delay fault test sequence generation method according to the related art Diagram showing the characteristics of delay faults defined on a semiconductor integrated circuit in the prior art

Explanation of reference numerals

31 An operation of setting a predetermined delay value Dmin 32 An operation of excluding a fault whose delay value is smaller than a predetermined delay value Dmin among all the defined faults from the processing target 35 A fault detection rate for the target fault processed in the operation 32 37 Operation to calculate the fault coverage by adding weight to each defined fault

Claims (20)

  Among the defined delay faults, delay faults with a delay value that is equal to or less than a predetermined delay value in the design are excluded from the fault test, and the delay fault test sequence for the number of delay faults in the remaining target was detected. A quality evaluation method for a delayed fault test sequence configured to evaluate the quality of a delayed fault test sequence using a ratio of the number of faults as a fault detection rate. A step of excluding a delay fault having a delay value equal to or less than a predetermined delay value in design among the defined delay faults as a target for failure inspection,
A step of calculating the ratio of the number of delayed faults in which the delayed fault test sequence could be detected to the number of delayed faults in the target remaining in the step of exclusion as a fault detection rate,
Evaluating the quality of the delayed fault test sequence based on the fault coverage.   Weighting is performed for each of the defined delay faults, and the quality of the delay fault test sequence is evaluated using the ratio of the sum of the weights of the delay fault test sequences that can detect the delay fault test sequence to the sum of the weights of the delay faults as the fault detection rate. Quality evaluation method of a delay fault test sequence configured to perform Weighting each of the defined delay faults;
A step of calculating, as a failure detection rate, a ratio of the sum of the weights of the delay faults in which the delay fault test sequence can be detected to the sum of the weights of the delay faults,
Evaluating the quality of the delayed fault test sequence based on the fault coverage.   As the weight, a configuration is used in which a relative value of the 'design delay value of the signal path where the delay fault is defined' to the 'design value of the timing of the signal path where the delay fault is defined' is used. The method for evaluating the quality of a delay fault test sequence according to claim 3.   6. The delay fault test sequence according to claim 5, wherein the 'design value in timing design of the signal path in which the delay fault is defined' is configured to use a clock rate for the signal path in which the delay fault is defined. Quality evaluation method.   4. The quality evaluation method for a delay fault test sequence according to claim 3, wherein the weight is determined by using the number of gate stages of a signal path in which the delay fault is defined.   The weight may be a product of the 'design delay value of the signal path in which the delay fault is defined' and the 'physical path length of the signal path in which the delay fault is defined'. Item 3. A method for evaluating the quality of a delay fault inspection sequence according to item 3.   As the weight, a product of the 'design delay value of the signal path in which the delay fault is defined' and the 'physical wiring area on the path of the signal path in which the delay fault is defined' is used. The method for evaluating the quality of a delay fault test sequence according to claim 3.   As the weight, a result obtained by adding an element area to the 'design delay value of the signal path where the delay fault is defined' and the 'physical wiring area on the path of the signal path where the delay fault is defined'. 4. The quality evaluation method for a delay fault test sequence according to claim 3, wherein the product is configured to use the product of   The quality evaluation method of a delay fault inspection sequence according to any one of claims 7 to 10, wherein the weight is further multiplied by a defect density.   A delayed fault test sequence generation method configured to calculate a fault coverage by using the delayed fault test sequence quality evaluation method according to claim 1 for the generated delayed fault test sequence.   A delayed fault test sequence generation method configured to calculate a fault coverage by using the delayed fault test sequence quality evaluation method according to claim 3 for the generated delayed fault test sequence.   A delay fault simulation method configured to calculate a fault coverage for a given delay fault test sequence using the delay fault test sequence quality evaluation method according to claim 1.   A delay fault simulation method configured to calculate a fault coverage using a delay fault test sequence quality evaluation method according to claim 3 for a given delay fault test sequence.   In the semiconductor integrated circuit inspection process, a fault detection rate is calculated for a delay fault inspection sequence used for inspection by using the delay fault inspection sequence quality evaluation method according to claim 1. Failure inspection method.   In the inspection process of the semiconductor integrated circuit, a failure detection rate is calculated for the delay failure inspection sequence used for inspection by using the quality evaluation method of the delay failure inspection sequence according to claim 3. Failure inspection method.   Claims: A configuration wherein the ratio of the 'design delay value of a signal path in which a delay fault is defined' to the 'design value of a signal path in which a delay fault is defined' is used as the weight. Item 3. A method for evaluating the quality of a delay fault inspection sequence according to item 3.   19. The delay fault test sequence according to claim 18, wherein the 'design value required for timing of a signal path in which a delay fault is defined' is configured to use a clock rate for the signal path in which the delay fault is defined. Quality evaluation method. The 'requested value in timing design of the signal path in which the delay fault is defined' is a clock for the signal path in which the delay fault is defined when the signal path in which the delay fault is defined is a multi-cycle path. 19. The method for evaluating the quality of a delay fault test sequence according to claim 18, wherein the method is configured to use a product of the rate and the number of multicycles.

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