JPH11110431A - Signal propagation delay time calculating method for logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make highly accurately performable the signal propagation delay time calculation of a logic circuit such as a semiconductor integrated circuit at a high speed, by avoiding wiring delay time calculation utilizing a high-accuracy calculation model concerning a wiring within the range of an allowable error for the calculated result of signal propagation delay time between flip-flops. SOLUTION: Design information, execution necessity judgement reference value and wiring delay time estimate table are inputted from a design information file (S10). Calculation factors related to the circuit load delay time calculation of a logic element and the wiring delay time calculation of a microbus are extracted from the design information (S11 and S12). The circuit load delay time calculation of the microbus is performed by the high-accuracy calculation model (S13). The estimated wiring delay time of each microbus is found from the extracted calculation factors and the wiring delay time estimate table (S14). The estimated wiring delay time of each microbus is compared with the execution necessity discrimination reference value and when it is less than the execution necessity discrimination reference value, the wiring delay time calculation of that microbus is omitted (S15).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for calculating a signal propagation delay time of a logic circuit applied to a design automation system such as a semiconductor integrated circuit or a logic processing device. And how to find it fast.

[0002]

2. Description of the Related Art In the design of a semiconductor integrated circuit or a logic processing device, not only the logical functions but also the timing constraints of the logic circuit as to whether the designed logic circuit operates as expected are sufficiently verified at the design stage. That has become very important. In particular, the operating clock frequency of the logic processing device has been increasing with the speeding up of the logic processing device, and the signal propagation delay time of the logic circuit is calculated in the design stage in advance, and it is verified whether the logic circuit can operate at the expected timing. Is essential. On the other hand, the scale of integrated circuits has increased due to advances in semiconductor manufacturing technology, and it has become very difficult to verify the timing of the entire device.

As one of the conventional timing verification methods, there is a method in which a test pattern is input, and a logic function verification and a timing verification are simultaneously performed by a logic simulation. However, this method cannot perform delay verification other than the path activated by logic verification. Further, due to the recent increase in the scale of the apparatus, the computer time becomes enormous in verification by logic simulation. Therefore, a method of performing simulation in synchronization with the clock signal of the flip-flop input terminal of the logic circuit by setting the element delay to 0 has been proposed. It has been used (for example, see JP-A-3-99372). However, in this method, since the element delay is treated as 0, the timing cannot be verified. Further, a timing verification system using a path analysis method with high accuracy for all combinations of flip-flops in combination with such a 0-delay logic simulation has been adopted for high-performance integrated circuits. The path analysis method is mainly applied to synchronous circuits, and unlike logic simulation,
The input test pattern has the merit of being unnecessary. Actually, there are two methods, a path enumeration method and a critical path method. The path enumeration method enumerates all paths of a combinational circuit, finds the delay of each path, and finds the delay of the combinational circuit based on the result. In addition, the critical path method is for determining a delay between flip-flops only for a path having a maximum delay and a minimum delay between flip-flops, and has an effect of reducing the amount of verification paths.

On the other hand, when calculating the wiring delay time of a logic circuit such as a semiconductor integrated circuit with high precision, recently, a high-precision calculation model such as an AWE algorithm has been used to calculate the delay between all the logic elements in the semiconductor integrated circuit. The wiring delay time is calculated using the same calculation model for the wiring. A
In the WE method, a wiring pattern is regarded as a distributed constant circuit load of a CR, a voltage-current relational expression of the load is Laplace-transformed, and a voltage at an end position of the wiring is analytically obtained. This is a method of converting into a relationship (for example, LT Pillage,: Asymptotic Wavefor
m Evaluation for Timing Analysis; IEEE Tra
ns. on CAD, vol. 9, No. 4, pp. 352-pp. 36
6, (1990)).

[0005]

SUMMARY OF THE INVENTION When calculating a wiring delay time in an electronic calculation system or a semiconductor integrated circuit used therein using a high-precision calculation model such as the AWE method, the scale of the system or the integrated circuit is large. As the amount of data becomes enormous, the calculation of the signal propagation delay time of the entire logic circuit requires enormous processing time, and the timing verification period becomes longer. It has become.

In recent years, as the speed of the semiconductor integrated circuit has been increased and the scale thereof has been increased, the wiring between the logic elements has become the mainstream as shown in FIG. ing. Further, in the distribution of the wiring length and the number of wirings shown in FIG. 7, the hatched partial wiring of A that is equal to or less than a certain wiring length has a wiring delay time within the range of an error of a signal propagation delay time calculation result such as between flip-flops. The wiring is as short as possible. If the calculation of the wiring delay time between all the logic elements is performed by the calculation method using the high-precision calculation model such as the AWE method including the wiring between the logic elements having a small wiring delay time, an enormous processing time is required. In short, the calculated wiring delay time is so small that it is within the range of the error of the result of calculating the signal propagation delay time between flip-flops and the like, and there is an negligible wiring amount.

SUMMARY OF THE INVENTION It is an object of the present invention to avoid the calculation of a wiring delay time for a wiring whose wiring delay time between logic elements is short enough to be within an error range of a signal propagation delay time calculation result between flip-flops including the logic element. It is another object of the present invention to calculate a signal propagation delay time between all flip-flops and other logic elements in a logic circuit such as a semiconductor integrated circuit with high accuracy and high speed.

[0008]

According to the present invention, for example, a signal propagation delay time between all flip-flops included in a semiconductor integrated circuit is calculated by calculating a circuit load delay time and a wiring delay time between logic elements between flip-flops. This is applied when the sum is obtained from the sum, and extracts the factors related to the circuit load delay time calculation from the design data of the semiconductor integrated circuit to perform the circuit load delay time calculation, and extracts the factors related to the wiring delay time calculation. Then, an estimated wiring delay time is calculated, and the estimated wiring delay time is within a predetermined allowable range of the signal propagation delay time calculation result between the flip-flops. (Hereinafter referred to as the execution necessity determination reference value.) For the following wiring, a step of avoiding the calculation of the wiring delay time using the high-precision calculation model, Wiring delay time exceeds embodiment necessity determination reference value, and characterized in that it is composed of such step of performing line delay time calculation using highly accurate calculation by AWE method.

Further, according to the present invention, when calculating the estimated wiring delay time between the respective logic elements, the wiring capacitance and the wiring resistance of the wiring to be processed are used as calculation factors, or the wiring to be processed is It is characterized in that the wiring length is used as a calculation factor.

According to the present invention, it is possible to avoid the calculation of the wiring delay time using a high-precision calculation model by the AWE method or the like for wiring that is short enough to be within the error range of the calculation result of the signal propagation delay time between flip-flops. Thereby, the calculation processing time of the signal propagation delay time between the flip-flops can be reduced, and the calculation with the calculation accuracy can be performed at high speed. Note that the present invention is not limited to flip-flops,
Generally, the present invention can be applied to calculation of a signal propagation delay time between logic elements.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment according to the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of a circuit to be subjected to calculation of a signal propagation delay time between flip-flops according to the present invention in a synchronous logic circuit. In a synchronous logic circuit, the signal propagation delay time between flip-flops must be within a predetermined value range. FIG.
Is composed of two flip-flops G01, G04 and two logic elements G02, G03, which are connected by signal lines L1, L2, L3.
M1, M2 and M3 are respectively flip-flops G0
1 is the minimum unit (hereinafter referred to as a micropath) when calculating the signal propagation delay time between G04 and G04.
The signal propagation delay time between 1 and G04 is calculated as the sum of each micropath. Here, the signal propagation delay time of one micropath is calculated as the sum of the circuit load delay time of a flip-flop or a logic element and the wiring delay time of a signal line connected to the flip-flop or the logic element. For example, the micropath M1 is a flip-flop G01.
And the wiring delay time of the signal line L1. The same applies to the micropaths M2 and M3.

FIG. 2 shows the micropaths M1 and M in FIG.
2, M3, and the circuit load delay time of the flip-flops and logic elements included in the signal lines L1, L2. FIG. 9 is a diagram illustrating an example of a wiring factor value of L3 and a wiring delay time. As shown in FIG. 2, here, the circuit load delay time of the flip-flop G01 included in the micropath M1 is 180 ps, and the signal line L
1, the wiring capacity is 2.0 fF, the wiring resistance is 0.5 Ω, the wiring length is 0.05 mm, the wiring delay time is T1 ps, the circuit load delay time of the logic element G02 included in the micropath M2 is 250 ps, and the signal line L2 When the wiring capacitance is 7.0 fF,
The wiring resistance is 2.0Ω, the wiring length is 0.15 mm, the wiring delay time is T2 ps, the circuit load delay time of the logic element G03 included in the micropath M3 is 220 ps, and the signal line L3
The wiring capacitance is 5.0 fF, the wiring resistance is 1.5 Ω, the wiring length is 0.10 mm, and the wiring delay time is T3 ps.

The circuit load delay time and the wiring delay time in FIG. 2 are values calculated by a high-precision calculation model requiring a processing time. However, in FIG. 2, a specific calculation value of the wiring delay time is omitted.

FIG. 3 is a flowchart showing a series of processes of a program for calculating a signal propagation delay time between all flip-flops included in a semiconductor integrated circuit according to the method of the present invention.

In step 10, design information relating to all logic elements and all signal lines between flip-flops to be calculated is input from a design information file prepared in advance. In the present embodiment, it is assumed that a reference value for determining the necessity of performing the wiring delay time calculation is also prepared in the design information file, and when the design information is input, the reference value for determining whether or not the execution is necessary is also input. In step 10, it is assumed that a wiring delay time estimation table described later is also input.

Next, at step 11, calculation factors (load capacity, signal rise time, etc.) relating to the calculation of the circuit load delay time of the logic element are extracted from the design information input at step 10. Next, in step 12, calculation factors (wiring capacitance, wiring resistance, wiring length, etc.) related to the wiring delay time calculation of the signal path of the micropath to be calculated are
Similarly, it is extracted from the design information input in step 10.

Next, at step 13, the circuit load delay time of the micropath to be calculated is calculated using a high-precision calculation model. As a result, the logic circuit of FIG.
As shown in FIG.
ps, 250 ps in logic element G02, logic element G
It is assumed that 220 ps is calculated in 03.

Next, in step 14, the estimated wiring delay time of the signal line of each micropath is set for the calculation factor extracted in step 12 and the estimated wiring delay time for the calculation factor previously input in step 10. From a given table (this is referred to as a wiring delay time estimation table). Here, there are the following two methods for calculating the estimated wiring delay time according to the present invention, and any one of them can be selected.

The first method is a method of obtaining from the wiring delay time estimation table shown in FIG. 4 based on the wiring capacitance and wiring resistance of the signal line extracted in step 12. FIG.
Is a matrix table prepared in advance, which describes the wiring capacitances of the signal lines L1, L2, L3 included in each of the micropaths M1, M2, M3 shown in FIG. When the estimated wiring delay time of the signal line L1 in FIG. 1 is obtained from the wiring capacitance and wiring resistance shown in FIG. 2 using the table shown in FIG. 4, an estimated wiring delay time 1 ps can be obtained. Similarly, FIG.
, The estimated wiring delay time of the signal line L2 is 7 ps, and the estimated wiring delay time of the signal line L3 is 3 ps.

The second method is a method of obtaining the wiring delay time estimation table shown in FIG. 5 from the wiring length of the signal line extracted in step 12. FIG. 5 shows signal lines L1, L2 included in each of the micropaths M1, M2, M3 shown in FIG.
It is a table prepared in advance that describes the estimated wiring delay time with respect to the wiring length of L2 and L3. When the estimated wiring delay time of the signal line L1 in FIG. 1 is obtained from the wiring length shown in FIG. 2 using the table shown in FIG. 5, an estimated wiring delay time 1 ps can be obtained. Similarly, FIG.
, The estimated wiring delay time of the signal line L2 is 7 ps, and the estimated wiring delay time of the signal line L3 is 3 ps.

For convenience, it is assumed in step 14 that the estimated wiring delay time of the signal line of each micropath is obtained by the first method based on the wiring capacitance and the wiring resistance of the signal line.

Next, in step 15, step 1
The estimated wiring delay time of the signal line of each micropath obtained in 4 is compared with the execution necessity determination reference value input in step 10. If the estimated wiring delay time is equal to or less than the execution necessity determination reference value, The calculation of the wiring delay time of the signal path of the micropath is omitted, and the process proceeds to step 17, where the wiring delay time is set to 0 to avoid the calculation of the wiring delay time using the high-precision calculation model by the AWE method or the like. On the other hand, when the estimated wiring delay time is equal to or more than the execution necessity determination reference value, the process proceeds to step 16, and the wiring delay time is calculated using a high-precision calculation model such as the AWE method.

Here, the execution necessity determination reference value will be described with reference to FIG. FIG. 8 is a diagram showing the execution necessity determination reference value and the required calculation accuracy when calculating the wiring delay time between all the logic elements of the semiconductor integrated circuit including the logic circuit in FIG. In FIG. 8, when A is a calculation error in the signal propagation delay time calculation, it is set as a reference value of the necessity of performing the wiring delay time calculation. Here, the implementation necessity determination reference value is 6 ps. As described above, in step 15, the estimated wiring delay times of the signal lines L1, L2, and L3 of the circuit shown in FIG. 1 are determined to be 1 ps, 7 ps, and 3 ps, respectively. Estimated wiring delay time 1ps for signal line L1
Is smaller than the execution necessity determination reference value 6 ps, the wiring delay time of the signal L1 is set to 0, and the calculation of the wiring delay time using a high-precision calculation model by the AWE method or the like is avoided.
Since the estimated wiring delay time 7 ps of the signal line L2 is larger than the execution necessity determination reference value 6 ps, the AWE
The wiring delay time is calculated using a high-precision calculation model by the method or the like, and the wiring delay time T1ps is calculated. Signal line L
The estimated wiring delay time 3ps of 3 is the execution necessity determination reference value 6
Since it is smaller than ps, the wiring delay time of the signal line L3 is set to 0, and the calculation of the wiring delay time using a high-precision calculation model by the AWE method or the like is avoided.

Next, in step 18, step 1
3, and obtained in step 16 or step 17,
The delay time of each micropath is obtained by summing the circuit load delay time and the wiring delay time. As a result, in the case of the circuit shown in FIG.
The micropath signal propagation delay time of (250 + T1) ps for P.2 and 220 ps for micropath M3 is obtained.

Next, in step 19, the signal propagation delay time between the flip-flops is obtained by summing the signal propagation delay times of the micropaths included between the flip-flops. Thus, the flip-flop G of the circuit shown in FIG.
01, G04 signal propagation delay time (650 + T1)
It is calculated as ps.

Steps 10 to 19 described above
The series of processing up to is performed on all the flip-flops included in the semiconductor integrated circuit to calculate the signal propagation delay time between all the flip-flops included in the semiconductor integrated circuit.

As described above, by using the calculation method of the present invention, it is possible to avoid the calculation of the wiring delay time using the high-precision calculation model by the AWE method or the like for the wiring between the logic elements that does not require the calculation accuracy. Accordingly, the calculation of the signal propagation delay time between flip-flops can be speeded up.

FIG. 6 is a schematic block diagram showing a hardware configuration for implementing the signal propagation delay time method of the present invention. In FIG. 6, the design information file 100 includes design information on all flip-flops, all logic elements between all flip-flops, all signal lines included in the semiconductor integrated circuit or the logic processing device to be designed, A reference value for determining whether or not to execute the wiring delay time, which is within an allowable error range of the signal propagation delay time calculation result, is stored. The wiring delay time estimation table file 110 is a matrix table describing the estimated wiring delay time for the wiring capacitance and the wiring resistance shown in FIG. 4 or a table describing the estimated wiring delay time for the wiring length shown in FIG. Stores a time estimation table. The computer 120 includes a so-called CPU, RAM, ROM, and the like, and includes a signal propagation delay calculation program 121 and a high-precision calculation model 122 as software resources according to the present invention. The signal propagation delay time calculation program 121 processes most of the flowchart shown in FIG. 3 (each step other than the steps 13 and 16), and executes only the signal lines whose estimated wiring delay time is equal to or more than the execution necessity determination reference value. The high-precision calculation model 122 is requested to calculate the signal propagation delay time. The high-precision calculation model 122 calculates the circuit load delay time of each logic element (step 13 in FIG. 3) and the signal propagation delay time calculation of the signal line requested by the signal propagation delay time calculation program 121 (step in FIG. 3). The program is executed with high accuracy using an algorithm such as the AWE method, and the calculation result is stored in a program 121.
Pass to.

The circuit load delay time of each logic element can be calculated with high accuracy by the AWE method or the like by preparing in advance a table in which the circuit load delay time for the load capacitance, signal rise time, and the like is set. The calculation by the model can be omitted.

FIG. 9 is a diagram showing the effect of increasing the signal propagation delay time according to the present invention. In FIG. 9, A is A
It shows a processing time when a signal propagation delay time between all flip-flops included in a semiconductor integrated circuit is calculated using a high-precision calculation model such as a WE method. On the other hand, B in FIG. 9 represents the processing time when the calculation method according to the present invention is used. In FIG. 9, when the calculation processing time when the conventional calculation method and the calculation method according to the present invention are used is compared, the calculation processing time of the portion C is shortened, and the calculation of the signal propagation delay time can be speeded up. As is clear from FIG. 9, the effect of the present invention increases as the scale of the semiconductor integrated circuit increases.

[0031]

As described above, according to the present invention,
Wiring delay time calculation using a high-precision calculation model by the AWE method or the like for a wiring having a small delay time so as to fall within an error range of a signal propagation delay time calculation result between flip-flops included in a logic circuit such as a semiconductor integrated circuit. By avoiding the above, there is an effect that the signal propagation delay time of a logic circuit such as a semiconductor integrated circuit can be calculated at high speed while maintaining the calculation accuracy.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a logic circuit for which a signal propagation delay time is calculated.

FIG. 2 shows a flip-flop, a logic element, and the like used in FIG.
FIG. 7 is a diagram illustrating an example of signal line design information.

FIG. 3 is a flowchart showing a series of processes of a program for calculating a signal propagation delay time according to an embodiment of the present invention.

4 is a diagram showing a table for obtaining an estimated signal propagation delay time from a wiring capacitance and a wiring resistance of a signal line used in the circuit of FIG. 1;

FIG. 5 is a diagram showing a table for obtaining an estimated signal propagation delay time from a wiring length of a signal line used in the circuit of FIG. 1;

FIG. 6 is a schematic block diagram of a hardware configuration for implementing a signal propagation delay time calculation method according to the present invention.

FIG. 7 is a diagram illustrating an example of a distribution of wiring lengths and the number of wirings among all logic elements included in a semiconductor integrated circuit.

FIG. 8 is a diagram illustrating a criterion value for determining whether or not to perform a wiring delay time calculation;

FIG. 9 is a diagram showing the effect of the present invention.

[Explanation of symbols]

G01, G04 Flip-flop G02, G03 Logic element L1, L2, L3, L4 Signal line M1, M2, M3 Minimum unit for calculating signal propagation delay time (micropath)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshiyuki Takagi 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture Within Hitachi Information Technology Co., Ltd. Inside the Central Research Laboratory (72) Inventor Hidechi Hongo 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Nichi Information Technology Co., Ltd. (72) Inventor Toru Hiyama 1st Horiyamashita, Hadano-shi, Kanagawa Inside General-purpose Computer Business Division, Hitachi, Ltd.

Claims (3)

[Claims] In a method for automatically obtaining a signal propagation delay time of a logic circuit as a sum of a circuit load delay time and a wiring delay time between each logic element included in the logic circuit, When performing the wiring delay time calculation, the wiring delay time between the logic elements is estimated from a factor relating to the wiring delay time, and the estimated wiring delay time is calculated between the logic elements having a predetermined reference value or less. To avoid
A method for calculating a signal propagation delay time of a logic circuit, comprising calculating a wiring delay time only between logic elements exceeding a reference value. 2. A signal propagation delay time calculation method for a logic circuit according to claim 1, wherein when calculating the wiring delay time between each of the logic elements, the wiring resistance and the wiring capacitance of the wiring between the logic elements are also determined. A signal propagation delay time calculation method for a logic circuit, wherein a wiring delay time between the logic elements is estimated. 3. The signal propagation delay time calculation method for a logic circuit according to claim 1, wherein when calculating the wiring delay time between the respective logic elements, the wiring length between the respective logic elements is calculated based on the length of the wiring between the respective logic elements.
A signal propagation delay time calculation method for a logic circuit, comprising estimating a wiring delay time between the logic elements.