JP2001051027A - Detecting method of delay failure of logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make detectable even a slight delay of each logic element by using a random-number sequence or using an inspection list which activates routes of a sufficiently small number as compared with the number of all existing routes. SOLUTION: When an inspection list is generated, a delay failure is supported inside a logic circuit to be tested, a first memory element group is shifted to a second internal state from a first internal state, and a signal transition is generated at an output terminal so as to be propagated to a second memory element. Alternatively, a third memory element in which a signal transition is passed through a failure supposition part from the part group of external input terminals so as to reach the input terminal is searched, or a route in which the signal transition is propagated to the part group of the external input terminals is searched. Then, the signal propagation time on the route is calculated, a first parameter value is set so as to be situated between its maximum value and a value in which a first parameter value expressing the degree of the signal propagation delay of a delay failure to be supposed is subtracted from the threshold value corresponding to a test time interval, and a supposed failure can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a delay fault in a logic circuit, and more particularly, to a method for detecting a manufacturing failure of a logic integrated circuit constituting a computer and a substrate on which a plurality of logic integrated circuits are mounted, and detecting a manufacturing process. The present invention relates to a method for detecting a delay fault of a logic circuit which is suitable for use in improving, reducing the number of return steps, and maintaining product quality.

[0002]

2. Description of the Related Art Generally, most of the functions of a computer are built in an integrated circuit, and the performance such as the calculation speed greatly depends on the manufacturing technology of the integrated circuit. In addition, there are many defective integrated circuits that do not operate at a high speed corresponding to product specifications even when they operate completely at a low speed. In order to ensure high performance as an apparatus such as a computer, a test for guaranteeing the operation speed of each integrated circuit as a product when assembled as a product is required. An integrated circuit constituting a computer includes many logic elements, and the number of possible states is enormous. For this reason, if the test of the integrated circuit is performed for all the propagation states of the transition signals, all the conditions necessary for ensuring the performance can be included. It's too much, the test takes too long and isn't practical.

In order to reduce the number of states used for the test to a realistic value, a test is generally performed by approximating a failure with a simple failure model. According to this method, modeling makes it possible to assume a fault in a circuit and simulate the response of the circuit to evaluate the effectiveness of the test sequence. , The required test sequence can be supplemented.

There are roughly two types of failure models for failures that cause a failure depending on the operation speed of a circuit. There are roughly two types of target parts for which a failure operation is assumed, one is a gate delay failure, and the other is a path delay failure. It is a failure.
The former assumes a delay fault for each input / output terminal of each element, and the latter assumes all propagation paths 1 from the starting point at which the signal transition occurrence time can be controlled to the point at which the signal value at a specific time can be observed. Next, a delay fault is assumed. The latter starting point and observation point are an external input / output terminal of a circuit, a storage element controlled by a clock, and the like.

[0005] The total assumed number of gate delay faults does not depend on the structure of the circuit and is the total number of propagation paths of input / output terminals for each element. In a certain test sequence, when the signal transition passes through the fault assumption point and reaches the observation point, it can be determined that detection is possible. For this reason, the model that assumes a gate delay fault requires only the order of the number of states in the processing of test sequence generation and detection judgment processing, and a test sequence with an almost perfect detection rate is used in the conventional technology. Can also be obtained. On the other hand, the total assumed number of path delay faults depends on the structure of the circuit. For this reason, in the model that assumes a path delay fault, all transition signal propagation paths are included in the test target, and thus the necessary state is likely to be covered. However, since the number of paths increases, test generation and detection determination It takes a lot of time and is not realistic for large circuits.

Many attempts have been made to efficiently handle a large number of routes, and as this kind of prior art, for example, [1]
MA Gharaybeh, "A Parallel-Vector Concurr"
ent-Fault Simulator and Generation of Single-Input
-Change Tests for Path-Delay Faults ”IEEE Transac
tion on Computer-Aided Design of Integrated Circui
ts and Systems, Vol. 17, No. 4, pp. 873-876, 1998
And the like are known. This prior art,
The source of the transition signal in each pattern is limited to one bit,
By using six types of logical values, it is possible to efficiently handle a plurality of transition signal propagations simultaneously. However, even if this conventional technique is used, the number of paths to be tested is still large, and it is difficult to apply this conventional technique to all parts of a large-scale integrated circuit.

[0007] In order to avoid such a problem, there is known a method in which paths which are considered to greatly affect the performance of a circuit are preliminarily selected, and test sequences are generated and tested for those paths. For example, [2] RS Fetherston, et al., “Testa
bility Features of the AMD-K6 Microprocessor ”IEE
E Design & Test of Computers, Vol. 15, No. 3, pp.
The techniques described in 64-69, 1998, etc. are known. In this prior art, a test is performed by assuming a path delay fault on 5,000 paths having the longest propagation time and 5,000 paths sampled from the entire surface of an integrated circuit chip without bias.

On the other hand, by devising a method capable of applying a large number of test sequences without calculating path test coverage by a path delay fault model,
Methods have also been used that attempt to substantially test the operation of the circuit. As a conventional technique of this kind, for example,
[3] B. Koenemann, et al., “Delay Test: The NextF
rontier for LSSD Test Systems ”Proceedings of the
IEEE International Test Conference, 1992, pp. 578
-587 and the like are known. This prior art uses a pseudo random number generator provided in an integrated circuit,
This is a method in which a large number of transition signals are propagated and a test is performed at time intervals corresponding to the operation speed when the device is assembled. [4] MP Kus
ko, et al., “Microprocessor Test and Test Tool Meth
odology for the 500MHz IBM S / 390G5 Chip ”Proceedi
ngs of the IEEE International Test Conference, 199
8, pp. 717-726.

In a test performed on the assumption of a delay fault, the degree of a delay time recognized as a fault is determined by a signal transition in applying a test sequence to a test target circuit, as discussed in the aforementioned reference [3]. And the test time interval between injection and observation. The detection rate for the test sequence delay fault is
The case where the degree of delay time of a failure determined to be detected is larger than the test time interval is defined. Therefore, in the process of generating a test sequence and performing detection determination according to the related art, it is customary to assume a transition fault in which detection determination is performed on the assumption that the degree of delay time due to a failure is always greater than the test time interval. For this reason, the detection rate, which is the ratio of the number of faults determined to be detectable to the total number of assumed faults, is determined assuming a transition fault.

[0010]

The prior art described above is
In any case, in order to search for a test sequence group for guaranteeing the speed at the time of actual operation and perform the test within the range possible within the practical time, the number of target signal propagation paths is narrowed down in advance, or There is no other choice but to operate a large number of paths at random at the same time using random numbers or the like, and to expect that necessary paths are covered by chance. For this reason, in the prior art described above, if there is a circuit part that is hard to be tested by random numbers, that is, a circuit part that cannot be tested except in a state where the probability of realization is low by accident, the random number is continuously applied. However, there is a problem that the number of undetected failures increases. Because of this, testing large circuits
The number of remaining faults is very large, and it is still difficult to generate a complete test sequence for coverage.

The logic of the input / output terminal of the element is "0" when a fault occurs.
Inspection with almost perfect detection rate for a single stuck-at fault model fixed to either one of "1" or "1", or a transition fault model that makes a detection decision assuming that the degree of delay time due to a fault is always greater than the test time interval Even an integrated circuit that is determined to be non-defective in the system may not be neglected because it may exhibit a defective operation when assembled in the device. [5] W. Needham, et al., “HIGH VOLUME MICRO
PROCESSOR TEST ESCAPES, AN ANALYSIS OF DEFECTS OUR
TESTS ARE MISSING. ”Proceedings of the IEEE Inte
As described in the rnational Test Conference, 1998, pp. 25-34, the detection rate for existing fault models is 10%.
Because it is not 0%, there are some defects to be overlooked.

However, when a large number of failure cases of the apparatus are collected and analyzed in detail, even if a single stuck-at fault model or the above-described transition fault is assumed, a test sequence having a 100% detection rate is temporarily obtained. It can be seen that even if the test can be performed in a series, the failure when operated as a device cannot be completely eliminated.

When the yield is obtained for each test type, a value corresponding to the density of defects that cause defects detectable by the test type can be obtained. By calculating the detection rate for a certain failure model in the test type, it is possible to estimate the number of failures corresponding to the failure model to be missed in the test. Considering a single stuck-at fault model and a gate-delay transition fault model as a fault model, for an integrated circuit constituting an actual computer device, the number of faults to be missed because the detection rate is not 100% is estimated. Comparing with the number of integrated circuits that cause a failure phenomenon that is not deterioration after assembling in a computer device, it has been found that not less than a small number of failures remain as compared with the overlooked failure modeled.

Although it is difficult to determine the physical direct cause of these residual failures, the cause has been found in some cases by adding a test sequence or analyzing the failure phenomenon in detail. According to it, the physical cause is
This is a defect in the structure of a logic element, which is in accordance with the transition failure model of gate delay, in which a transition signal passing through it has a delay. It has been found that the failure detection route included in the above did not reach the threshold value determined to be defective. In the inspection series, only a limited circuit state is realized due to capital investment in manufacturing processes and time constraints.
On the other hand, since the integrated circuit in the assembled device operates under various conditions, even a slight delay as described above of a certain element causes a transition signal propagation path that appears as a failure. May be included.

[0015] For example, [6] PC Maxwell, et al., "IDDQ AND AC SCAN: THE WAR AGAINST UNMODELLED D
EFECTS ”Proceedings of the IEEE International Tes
t Conference, 1996, pp. 250-258. Therefore, in order to keep the quality of an integrated circuit high, a test sequence that can detect even a slight delay of each logic element is required.

An object of the present invention is to detect a slight delay of each logic element by using a random number sequence or a test sequence that activates a sufficiently small number of paths compared to the number of all existing paths. A method of detecting a delay fault of a logic circuit that can detect a fault, detecting a fault assumption point where a slight delay cannot be detected, and providing a means for generating a test sequence for the fault. And a method of detecting a delay fault in a logic circuit, which can improve the required performance.

[0017]

According to the present invention, an object of the present invention is to input connection information of a logic element of a logic circuit to be tested and wiring between elements and information of signal propagation time of each element and each wiring. Setting a first internal state to a first storage element group included in the test target logic circuit, applying a plurality of transition signals at test time intervals from a test apparatus, and setting the first storage element group to a second storage element group. After changing to the internal state, a value held by the first storage element group is read out, a test sequence to be compared with an expected value is generated, and a delay of a logic circuit for detecting a failure of the circuit using the test sequence is detected. In the fault detection method, the generation of the test sequence may be performed by assuming a delay fault in the logic circuit to be tested and shifting the first group of storage elements from a first internal state to a second internal state. Causes a signal transition, The signal transition propagates through the propagation path in the circuit under test, and the signal transition propagates through the fault assumption site to the second storage element, or the signal transition propagates from the subgroup of external input terminals to the fault assumption. Searching for a path that propagates through a portion to a third storage element or a subgroup of external output terminals that reaches the input terminal thereof, calculates a signal propagation time of the transition signal on the searched path, The maximum value of the signal propagation time is between a threshold value corresponding to the test time interval and a value obtained by subtracting a first parameter value representing the degree of signal propagation delay of the assumed delay fault from the threshold value. This is achieved by setting the first parameter value so that the assumed failure can be detected.

Further, the object is as described above, wherein the maximum value of the signal propagation time is a threshold value corresponding to the test time interval, and a first parameter representing the degree of signal propagation delay of a delay fault assumed from the threshold value. Instead of setting the first parameter value to be between the decremented value, the maximum value of the signal propagation time may be a threshold value corresponding to the test time interval and a delay assumed from the threshold value. This is achieved by setting the test time interval to be between a value obtained by subtracting the value of the first parameter representing the degree of signal propagation delay of the fault.

The object is to search for a path through which the transition signal propagates, by transmitting a logical value in the circuit to be tested and a signal transition caused by a transition from the first internal state to a second internal state. , And the propagation path thereof is recorded, and the signal transition is performed by searching for a path passing through the assumed fault point, and setting of a first internal state in the first storage element group. Is obtained by obtaining a logical value to be set corresponding to each term of the random number sequence.

The object of the present invention is to provide connection information of a logic element of a logic circuit to be tested and wiring between the elements, and a propagation path of a signal transition from an output terminal of the storage element to be tested to an input terminal of the storage element. Inputting information specifying a set, setting a first internal state in a first storage element group included in the test target logic circuit, applying a plurality of transition signals at test time intervals from a test apparatus, After changing one storage element group to the second internal state, a value held by the first storage element group is read out, a test sequence to be compared with an expected value is generated, and the circuit is generated using the test sequence. In the method for detecting a delay failure of a logic circuit for detecting a failure of the logic circuit, a first state is set in the first storage element group using design information of a logic element constituting the test target logic circuit and wiring between the elements. And during the test time After applying the plurality of transition signals, a first means for reading a value held by the storage element in a second state and generating a test sequence to be compared with an expected value; The signal transition propagates through the circuit under test from a second sub-group in the first storage element group or an external input terminal at the time of a test, which causes a signal transition at an output terminal by transition to an internal state, It is determined whether there is a path to a subgroup of the third storage element whose propagation reaches the input terminal or a path to an external output terminal at the time of testing. If the path exists, the path is set to the signal transition propagation path set. Is determined, and when it is recognized that the fault is included in the determination, a test sequence generated by a test sequence generation unit including: a unit that determines that a fault related to the delay of the path can be detected is used. Theory It is accomplished by detecting a failure of the circuit.

In general, in order to enable handling of a fault model in which the time required for a transition signal to pass through a fault assumed part increases by a finite amount, a unit of a circuit part which assumes a fault, that is, a path, a wiring, Each element has means for inputting, storing, and processing information for calculating a partial transit time for each of the case where a failure is assumed and the case where a failure is not assumed. Conventional fault simulation technology determines that a fault is detectable when a fault appears and a signal transition passing through the fault assumed part reaches the observation point.However, the present invention further defines a fault assumed part. It traces the source of the passing signal transition and calculates the time from the occurrence to the observation point for each of the cases with and without a fault, and compares the time with the test time interval to determine the detectability. judge. The present invention also provides a means for holding information of a set of paths having proper propagation times including a path required for detecting a failure group to be detected, a transition signal propagation path in a test circuit for a test sequence candidate, Is determined to be included in the set, thereby determining the possibility of detecting a failure on the path.

In order to find a detectable test sequence for a fault that has not been determined to be detectable, a circuit state that satisfies the condition that the transition signal passes through the assumed fault location and the passed transition reaches the observation point is determined. is necessary. The present invention further uses a means for setting a condition for a path through which the transition signal passes and guiding the transition signal to pass through a path having a longer propagation time. When the test time interval is set to a value not smaller than the maximum value of the transition signal propagation time of the test path of the normal circuit, the transition signal propagation path for detection has a large propagation time that is as close to the test time interval as possible. Selecting a route increases the possibility of detecting a fault with a small delay increase. Guidance to a path having a long propagation time for this purpose is possible by the following two means.

First, for each combination of an external input terminal or storage element serving as a transition signal generation point and an external output terminal or storage element serving as a transition signal observation point, a test target path having the maximum propagation time. Is a means for calculating the propagation time of the transition signal and determining a set of a transition signal generation point and an observation point having a part that assumes a failure in the path, using a set with a longer time.

Second, for each input terminal of each element constituting the circuit, the maximum value of the propagation time of the transition signal propagation path to the storage element or the external terminal, and the transition signal propagation path from the storage element or the external input terminal. Means for calculating or holding a numerical value corresponding to the maximum value of the propagation time of, and, when there are a plurality of propagation destinations of the transition signal passing through the assumed fault part, a candidate having the larger value of the element input terminal of the propagation destination candidate Selected as
When there are a plurality of options on the path of the transition signal flowing into each element, a means for selecting a candidate having a larger numerical value of the input terminal of the element as a candidate.

The search for the propagation path in the above two methods is performed by repeatedly selecting one of a plurality of candidates and checking whether the propagation is possible, and if not, selecting another option and checking the possibility. is there. By means of assigning priorities based on propagation times in the order of selecting candidates, it is possible to generate a highly accurate test sequence capable of detecting a delay fault having the smallest possible delay time.

The amount of processing in the search for the propagation path depends on the structure of the circuit and the algorithm for selecting the candidates. In the maximum case, the processing amount is almost on the order of the exponent of the circuit scale. In a large-scale integrated circuit, the time required for generating the test sequence is not enough, and the search may have to be terminated. Censoring can be performed, for example, by a method of making a determination for each hypothetical fault.However, the process returns to the selection of the propagation path, and a path having the next longer propagation time is selected from the priority order options based on the propagation time. If means for continuing the propagation path search for detecting the failure is provided,
A test sequence with higher accuracy can be generated.

According to the above-described means, the test sequence having the highest possible accuracy can be obtained even if the test time interval is set to a time interval corresponding to the propagation time of the time-consuming propagation path of the circuit under test. When used in combination with a means for superimposing a plurality of test sequences having no inconsistent value assignment, a test with a high detection rate can be performed with a small number of test sequences while keeping temporal accuracy as much as possible.

The propagation time of the transition signal needs to be handled separately for each path from the start point to the end point of the transition.
However, the number of paths is very large because it is the number of all combinations of elements and wirings that can be passed from all start points to all end points. The choice in the route search is nothing but the selection of the input terminal of the element to which the branch wiring is connected or the input terminal into which the transition signal flows. Therefore, the present invention uses means for calculating and holding a numerical value corresponding to the propagation time for determining the priority of selection for each input terminal of the element. As a result, the process of selecting a route having a longer propagation time can be simplified and the processing time can be reduced.

The fault detection / judgment means determines that the difference between the time required for the transition signal passing through the fault assumed part to propagate from the transition occurrence point to the propagation destination observation point and the test time interval is the delay caused by the assumed fault. If it is smaller than the time increase, it is determined that detection is possible. The failure detection rate varies depending on a numerical value defining the increase. By using the means for obtaining and displaying the detection rate corresponding to the plurality of numerical values of the increase amount, it is possible to grasp how much the delay fault can be detected and how much, and manage the test quality. .

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flowchart for explaining the outline of a test sequence generation processing operation according to an embodiment of the present invention, and FIG. FIG. 3 is a diagram showing an equivalent circuit that defines the operation of the flip-flop (FF), which is a storage element shown in FIG. 2, and FIG. 4 is a truth defining the operation of a basic element in the equivalent circuit shown in FIG. FIG. 5 shows a value table, and FIG.
FIG. 6 is a diagram showing a truth table defining the operation of the address decoder shown in FIG. 6, FIG. 6 is a diagram for explaining the structure of information when the circuit example shown in FIG. 2 is stored in a storage device, and FIG. FIG. 8 is a table showing the correspondence between element numbers and scan addresses in FIG. 8, and FIG. 8 is a view showing examples of numerical values corresponding to transition signal propagation times from input terminals to output terminals for each element function name shown in FIG. 9 is a diagram showing an example of a numerical value corresponding to a transition signal propagation time for each wiring in the circuit example shown in FIG. 2, and FIG. FIG. 11 illustrates an example of the internal state of FIG.
FIG. 12 is a diagram for explaining a time chart of a test sequence derived from the first internal state shown in FIG. 12, FIG. 12 is a flowchart for explaining details of the processing in step 108 in the flow shown in FIG. 1, and FIG. FIG. 4 is a diagram illustrating a relationship between a test time interval at an external clock input terminal and a signal propagation time from a data output terminal of a transition signal generation flip-flop to a data input terminal of a transition signal arrival flip-flop. 2 and 3, 201 to 212 are input terminals, 213 to 226 are flip-flops (FF),
227 to 245 are gate elements, 246 is a decoder, 24
7 is an OR gate, 248 to 252 are output terminals, and 302 is an FF element.

First, an example of a test target circuit used for describing the embodiment of the present invention will be described. The circuit example illustrated in FIG. 2 is configured to be able to write and read data to and from the FFs 213 to 226, which are storage elements in the circuit, through a scan circuit. The scan circuit includes an address decoder 246 for writing data and a gate 247 for reading data. The numbers shown in the circles in FIG. 2 are the element numbers in the following description and drawings.

In the circuit example shown in FIG. 2, a scan address of a flip-flop to be written is applied to scan address input terminals P12 to P15 (209 to 212), and a system clock input terminal P11 (208) is set to an inactive side value. In the example shown in FIG. 2, when data is applied to the scan data input terminal P10 (207) and a clock pulse is applied to the scan clock input terminal P9 (206) in the state of "0", the data is written into the flip-flop to be written. Is written to. When the scan address of the flip-flop to be read is applied to the scan address input terminals 209 to 212, data held by the flip-flop to be read can be observed from the scan data output terminal P16 (252).

Each of the FFs 213 to 226 is an element having a function represented by the logical equivalent circuit of FIG.
The input / output terminals D, C, S, R, and Q of FIG.
Correspond to the D, C, S, R, and Q signals in the description of the truth table shown in FIG. The input C3 of the boundary 301 shown in FIG.
When the input SD 308 is set to “1” and the input SC 307 is temporarily set to “1” while “06” is set to “0”, “1” is written to the element 302 and the output Q 303 becomes “1”. When the input SD308 is set to "0" and the input SC307 is temporarily set to "1" while the input C306 is set to "0", "0" is written into the element 302, and the output Q303 is set to "0". Become. Output q304 is input A3
When "09" is "0", it is always "0", and the input A309
Is "1", the same value as the output Q303 is output.

The FFs 213 to 2 in the circuit example shown in FIG.
The 26 input / output terminals D, C, SC, SD, A, Q, and q are signal lines D305,
C306, SC307, SD308, A309, Q30
3, q304. Terminal SC3 of each storage element
07, the value of the scan clock input terminal P9 (206) is distributed via the output signal line sc of the gate 243,
The terminal SD308 has a scan data input terminal P10.
The value of (207) is distributed via the output signal line sd of the gate 244, and the value of the system clock input terminal P11 (208) is distributed to the terminal C306 via the output signal line c0 of the gate 245. In addition, terminal A309 has
Scan address input terminals P12 to P15 (209 to 2)
12) is decoded by the address decoder 246, and the corresponding one of the 14 address selection signal lines s0 to s13 is connected. For example, the FF 213 is connected to the address selection signal line s0. FF213-2
The output q304 of all 26 is connected to the input terminal of the gate 247, and the value held by the FF selected by the address selection signal line is stored in the scan data output terminal P16 (2
52).

The operation of the decoder 246 is defined by a truth table shown in FIG. In other words, the address is assigned to the input terminal by setting the least significant 2 0th bit when the address is expressed in a binary number to A0, and setting the 1st bit to A0 in order.
The first and second power bits correspond to A2 and the third power bit corresponds to A3, respectively. Addresses 0 to 15 correspond to output terminals d0 to d15 in ascending order. For example, writing and reading to and from the FF 218 are performed by setting A0, A1, A2, and A3 to “1”,
This can be performed by applying “0”, “1”, and “0”.

By using the scan function in the circuit example shown in FIG. 2, it is possible to recognize the setting of an arbitrary internal state for the FF as the storage element and the pattern of the operation of observation, and the correspondence between each storage element and the address. It can be generated just by doing. Therefore, in the example of the connection table of FIG. 6 created in step 2 of the flow shown in FIG. 1 described below, the scan-related logic part is not described, and instead, the scan address list of the storage element as shown in FIG. Create it and refer to it in a later step. The scan address list shown in FIG. 7 is a table listing scan addresses corresponding to the element numbers 7 to 11, 18 to 22, and 34 to 37 of the FFs 213 to 226 in the circuit example shown in FIG.

The connection diagram of the circuit example shown in FIG.
It is created in step 102 in the processing flow of FIG. 1 described later, and includes an element table 601, an input destination table 602,
The output destination table 603 has a known format including three parts. The element table 601 is a table in which elements are assigned serial numbers and are arranged in the order of the serial numbers.
"FF" for F, "and" for an AND gate that is a logical AND element, OR that is a logical OR element
"Or" for a gate, "e" for an external input / output terminal
dge ". The connection destination of the input terminal of each element is described in the input destination table 602. The portion corresponding to each element in the input destination table 602 is the start position of the input destination table of the element table and the input. For example, the 7th element is “FF” because it is FF, and there are two input terminals that are connected except for scan-related logic, and the first two rows of the input destination table 602 are described in these descriptions. Referring to the corresponding range of the input destination table 602, it can be seen that the first terminal of the FF is connected to the eleventh terminal of the first element, and the second terminal is connected to the eleventh terminal of the twelfth element. .

The connection destination of the output terminal of each element is shown in Table 6 of the output destination.
03 is described. The part corresponding to each element in the output destination table 603 is identified by the output destination table head position of the element table 601 and the number of output destinations. For example, the seventh element has one connection destination other than the scan-related logic, and the seventh element in the output destination table 603
It can be seen that the first line corresponds to this description. Referring to the corresponding range in the output destination table, the 11th terminal of the FF is 13
The information related to the input terminal of the connected element connected to the #th element is described in the twelfth row of the input destination table 602,
It can be seen that the connection destination input terminal is No. 1.

In the above description, the number of the input terminal is
The numbers of the output terminals are numbered from No. 1 in order from the upper left of each element shown in FIG.

Next, referring to FIGS. 8 and 9, examples of numerical values corresponding to transition signal propagation times from input terminals to output terminals for each element function name in the circuit example shown in FIG. Examples of numerical values corresponding to the transition signal propagation time will be described. The tables of transition signal propagation times shown in FIGS.
It is created in step 104 in the processing flow of FIG. 1 described later.

The table shown in FIG. 8 stores the propagation time of signal transition from each input terminal to each output terminal for each element, and a set of one input terminal and one output terminal of each element function name. Is defined for the propagation time. For example, in FIG. 8, the propagation time from the second terminal to the eleventh terminal of the FF (fifth row) is different from the held value in the data input D.
Is a time interval from the moment when the transition signal from “0” to “1” is applied to the clock input C until the change in the value held at the output terminal Q appears.
In addition, the propagation time from the first terminal to the eleventh terminal of the FF (the sixth row) is such that the transition signal from “0” to “1” is applied to the clock input C after the transition signal arrives at the data input D. This is a value indicating how much the transition signal of the data input D must be delayed from the arrival time of the transition signal of the clock input C in order to apply the value after the transition of the data input D into the device. The absolute value of this value is shown as a negative value because it has the property of offsetting the other propagation time values described here.

The table shown in FIG. 9 is a table describing the propagation time of the transition signal of the wiring between the elements, and each propagation time is stored corresponding to the input terminal of the connected element of each signal line. The serial number of each propagation time matches the serial number of the input destination table 602 corresponding to the input terminal described with reference to FIG. And
The propagation time of the transition signal of the wiring is defined for each wiring path from the external input terminal or the output terminal of the element to the external output terminal or the input terminal of the element.

An example of the first internal state obtained when the test sequence is generated for the circuit example shown in FIG. 2 shown in FIG. 2 is shown in FIG.
5, and the assigned logical value is F
It is defined corresponding to the element number of F. In FIG. 10, the logical value “X” means unallocated (status unknown). Also, the first shown in FIG. 10 shown in FIG.
The time chart of the inspection series derived from the internal state of
It is created in step 106 in the processing flow of FIG. 1 described later, and the details thereof will be described in the description of the flow shown in FIG.

Next, with reference to the flow shown in FIG. 1, an outline of the processing operation of test sequence generation using one embodiment of the present invention will be described.

(1) Processing in Steps 101 and 102 First, information on elements constituting the circuit to be tested as described with reference to FIG. 2 and wiring between the elements is input.
The input information is stored in the connection table. When the circuit example shown in FIG. 2 is input, the connection table is as described with reference to FIG.

(2) Processing in Steps 103 and 104 Next, information on the signal propagation time of each element and wiring between the elements is input, and a table of signal propagation time values is created. As a result, a table storing numerical values corresponding to the transition signal propagation time from each input terminal to the output terminal for each element function name and numerical values corresponding to the transition signal propagation time for each wiring described with reference to FIGS. Created.

(3) Processing in Step 105 Next, a logical value is allocated to the storage element in the test target circuit, the first internal state as described with reference to FIG. Are defined in correspondence with the element numbers.

(4) Processing in Step 106 Next, a test sequence for setting the first internal state allocated to the storage element in Step 105 in the test target circuit is generated. A time chart of an example of a test sequence generated from the first internal state defined in FIG. 10 is shown in FIG. 11, which will be described below.

As shown in FIG. 11, the test sequence generated from the example of the first internal state defined in FIG. 10 has 30 patterns. 14 patterns from the beginning (serial numbers 0 to
13) refers to the scan address list of the storage element described with reference to FIG.
12 to P15, and the assigned logical value of the element number of the FF of the corresponding address in the first internal state is shown in FIG.
In this pattern, a first state is created in the FF by setting this value to the external input terminal P10 of the scan data and setting a pulse to the external input terminal P9 of the scan clock. Since no logical value is assigned to the four FFs corresponding to the addresses 10 to 13 and "X" is described in the internal state table, the value of the external input terminal P10 is set to " Fixed to 0 ".

The following two patterns (serial numbers 14, 15)
Are external input terminals P11 of the system clock, respectively.
This is a pattern in which a pulse is applied to. The operation at the time of testing the example of the test target circuit shown in FIG. 2 is based on the signal propagation time of the element shown in FIG. After the propagation time of the fifth row has elapsed, the FF in a state where a value different from the held value exists in the data input D
, A signal transition occurs at the output terminal Q and propagates through the circuit.

The time obtained by adding the propagation time in the sixth row of the signal propagation time table of the element shown in FIG. 8 to the time when the rising edge of the pulse in the pattern of serial number 15 arrives at the clock input terminal C of each FF. In other words, in this example, by the time that is advanced by 0.1 unit time, the value held by the FF where the transition signal has arrived at the data input D is inverted to the value after the transition, and the test target circuit is switched to the second circuit. Reach internal state. If the propagation time of the transition signal in the actual circuit exceeds the propagation time shown in FIGS. 8 and 9 which is the design value due to the existence of the delay fault, the arrival of the transition signal to the data input D is delayed. The internal state 2 is different from the normal state.

The next 14 patterns (serial numbers 16 to 29) of the test sequence shown in FIG. 11 are patterns for the purpose of observing the second internal state. As in the case, the address is sequentially set, but the scan data external output terminal P16 is observed while the scan clock external input terminal P9 is set to “0”.

(5) Processing in Step 107 Next, a delay fault is assumed in the test target circuit. As an example, a delay fault is assumed at the second input terminal of the 28th element in the circuit example of FIG. In this case, the 35th line on the input destination table 602 is the assumed failure point.

(6) Processing in Step 108 Next, the output signal values of each element in the first internal state and the second internal state are obtained. In the described embodiment of the present invention, the first internal state can be set and the second internal state can be observed using the scan circuit. Therefore, it is not necessary to simulate the response of the circuit under test for the test sequence portion for setting the first internal state and observing the second internal state. The occurrence of the transition relating to the manifestation and propagation of the delay fault occurs only at the rise of the pulse of the system clock having the serial number 14 pattern. Therefore, in order to determine the detectability of the assumed failure, the values of the signal lines of the respective elements in the first internal state before the rise of the pulse and in the second internal state after the pulse may be obtained. Will be. Details of the processing here will be described later with reference to the flow shown in FIG. That is, the external input terminals P0 to P1
Up to 1, assuming that all are fixed to "0" during the test,
The processing here is executed using the first internal state shown in FIG. 10, and the result of obtaining the output value of each element in the first and second internal states is stored in the corresponding column of FIG.

(7) Processing at Step 109 Next, the manifestation and propagation of the assumed fault are examined to determine whether the signal transition does not pass through the assumed fault point or does not propagate to the storage element. The failure assumption point is, as described above, the second
Since it is the second input terminal of the eighth element, the input destination is first traced in the input destination table 602 to become the twenty-sixth element. 26th
The element No. 601 is “0” in the first internal state and “1” in the second internal state from the element table 601, and it can be seen that the transition has passed the fault assumption point and is now manifested. Next, when the propagation is examined, the output value of the twenty-eighth element has transitioned from “0” to “1”, and the output destination is set in the output destination table 603.
It can be seen that the signal propagates to the 29th element and the 30th element. From the element table 601, both outputs of the 29th element and the 30th element have transitioned from “0” to “1”, so the output destination is further traced in the output destination table 603.
As a result, the propagation destination is each of the 32nd, 35th, and 36th elements, but since the output of the 32nd element has not changed, it does not follow further. Since the No. 35 element and the No. 36 element are FFs, the above-mentioned hypothetical fault may be detected, and the individual judgment is no.

(8) Processing in Step 110 Since it is determined in Step 109 that the hypothetical fault has a possibility of being detected, next, an FF as a source of a signal transition passing through the hypothetical fault point is searched for. . The second input terminal of the twenty-eighth element is connected to the output of the twenty-sixth element. Input destination table 60
2, it can be seen that the connection destinations of the two input terminals of the 26th element are the 24th element and the 21st element. 21st
Since the element No. has not transitioned, only the input of the element No. 24 is followed. The input terminal of the 24th element is the 20th
The search is terminated here because the element is connected to the FF element.

Then, for each combination of the FF of the transition signal generation source recognized as described above and the transition signal arrival FF recognized in step 108, each signal line and each element on the signal propagation path existing therebetween The maximum value of the sum of the propagation times is calculated from the values shown in FIGS. In the case of the illustrated embodiment, the transition signal source FF passing through the fault assumption point is the FF 220 of the twentieth element, and the transition signal destination FF 220
Are FF224 of the 35th element and FF2 of the 36th element
25. FF2
24 to the data input terminal D, 1.5 unit time, FF22
5 is a value that propagates in 1.3 unit time.

As shown in FIG. 13, the numerical values of the signal propagation time described above are the propagation times 1314 and 1315 from the output terminal Q to the input terminal D of the FF, and correspond to the test time interval 1303 in the test sequence example of FIG. Is different. FF220
8 occurs after the rising edge 1301 of the clock pulse applied to the clock external input terminal P11 reaches the clock input C of the FF 220 through the element 245, as shown in FIG. This is after the elapse of the delay time defined in the fifth row of the table, that is, the delay time 1307 of the FF. FF220 to FF
The propagation of each signal transition to 224, 225 corresponds to a time interval 1314, 1315, respectively.

The second internal state when the test target circuit is normal is based on the premise that the values after the transition of each signal described above are taken into the FF of each propagation destination. Therefore,
Each end of the above-mentioned time intervals 1314 and 1315 needs to be within a time range in which the external clock pulse 1302 of the FFs 224 and 225 can take in data from the data input terminal D. The time when the external clock pulse 1302 arrives at the clock input terminal C of each of the FFs 224 and 225 is determined by the delay time 1 of the clock signal distribution logic.
After 310, 1319, the transition arrival at the data input terminal D is before the point in time further back by the delay time 1311, 1318 of the FF defined in the sixth row of the table shown in FIG. , Must be in the time range 1312, 1317.

In a synchronous sequential circuit like the circuit example shown in FIG. 2, the signal propagation time from the external clock input terminal to each FF is uniform so that data transfer between FFs can be designed at a constant time interval as much as possible. Designed to be. For the same reason, FFs of the type having the same delay time are used. By considering a certain error range, the delay time 13
06, 1310, and 1319 are equal to each other, and the delay times 1307, 1311, and 1318 can be considered constant for each type of element. Therefore, by executing the processing for determining the detectability of a hypothetical fault and generating the test sequence in the propagation times 1314 and 1315 from the output terminal Q to the input terminal D of the FF, the processing amount can be reduced without any particular decrease in accuracy. Reduction can be achieved.

The described embodiment of the invention is illustrated in FIG.
Is a unit time of 0.4, and the absolute values of the delay times 1307 and 1311 are equal to each other, that is, 0.1 unit time. The test time interval 1303 at the external clock input terminal P11 can be obtained by adding 0.2 unit time to the upper limit 1312 of the propagation time from the output terminal Q of the FF to the input terminal D.

(9) Processing in Steps 111 and 112 Next, using the first parameter representing the degree of signal propagation delay of the assumed delay fault, a value for determining the detectability of the assumed fault is obtained. It is determined whether detection or non-detection is based on the obtained determination value.

For example, in the case of the circuit example shown in FIG. 2, the maximum value of the propagation time of all types of paths from the output terminal Q to the input terminal D of the FF is 1.8 unit time, It is conceivable to use 2.0 unit time as a test time interval corresponding to all possible transition signal propagations, adding time. In this case, the test time interval is 0.3 unit time longer than the propagation time of the path to the FF 224 of 1.5 unit time, and the test time interval is longer than the propagation time of the unit FF 225 of 1.3 unit time. 0.5 unit time longer. As a result, even if a fault having a degree of delay smaller than 0.3 unit time exists in the assumed part, the fault cannot be detected by the test sequence shown in FIG. Then, when a fault whose degree of delay is larger than 0.5 unit time exists in the assumed part, the fault can be detected by reading any of the FFs 224 and 225. In addition, when a failure with a delay of about 0.4 unit time exists in the assumed part, the failure can be detected by reading the FF 224, but cannot be detected by reading the FF 225.

According to the embodiment of the present invention, the first internal state candidate is selected by introducing a test time interval accuracy parameter and determining that the signal transition is detected when the signal transition passes through a path having a long propagation time. In addition, the magnitude of the delay of the fault that can be detected is reduced. In FIG. 13 described above, the first
Parameter values are 0.4 unit times 1313 and 1316
Then, a fault can be detected on the path propagating to the FF 224, but is not determined to be detected on the path propagating to the FF 225. In this case, another first internal state in which the value held by the seventh element is replaced with “0”,
Since the path propagating to the FF 224 is interrupted at the 29th element 238, the assumed failure cannot be detected and cannot be adopted as a test sequence.

When the propagation path of the signal transition to the storage element is established, any fault assumed for the signal line or the terminal of the element on the propagation path can be detected if the delay due to the fault is large. When the first parameter described above is introduced, a failure may not be detected depending on the test time interval. For example, when a signal transition passes through the output terminal of the thirtieth element 239, the transition propagates to the storage element 225 in a time unit of propagation time 1.3, so that it is detected that a delay fault is assumed at the output terminal. May be However, when 2.0 unit time is used as the test time interval and the value of the first parameter is 0.4 unit time, failure detection is performed if the time length of the propagation path is not more than 1.4 unit time. Not determined. Under the above-described conditions, in order to detect a delay fault at the output terminal of the element 239, it
It is necessary to add a test sequence that uses a propagation path with a propagation time of 1.5 hours to 25.

It is also conceivable to change the test time interval for each test sequence. When the reading of the contents of the storage element in the second internal state is limited to the FFs 224 and 225, the signal transition affecting the observation result is 1.5 unit times from the FF 220 to the FF 224 and 1.3 unit times from the FF 225 to the FF 225. Only the propagation path. Therefore, it is conceivable to add 0.2 unit time and use 1.7 unit time as the test time interval. In this case, the value of the above-described first parameter can be reduced. For example, when the value of the first parameter is set to 0.1 unit time, the output Q of the FF determined to be detected is applied to the data input D. Has a propagation time range from 1.4 to 1.5 unit time, and the second
The failure of the No. 30 input terminal is determined to be detected, while the failure of the output terminal of the No. 30 element 239 is determined to be undetected.

(10) Processing in Steps 113 and 114 Next, processing for determining termination is performed. Step 105 described above
If there is an untried hypothetical fault for which the detectability should be determined for the test sequence in process generated in the process of step 106 and step 106, the process returns to step 107 and returns to step 1
After the repetition of the processing from 07 to 113, and the repetition is completed, it is determined whether or not another test sequence for detecting the undetected remaining fault is necessary. Then, the processing of steps 105 to 114 is repeated. If there is no hypothetical fault to be determined, the process ends.

Next, the details of the processing in step 108 described above will be described with reference to the flow shown in FIG.

(1) When the processing of step 108 is started, it is first checked whether or not this processing is the processing of the first step 108. If this processing is the first processing, the output values of the elements other than the storage element are determined. Is set to an undefined value “X” (steps 1201 and 1202).

(2) If the processing is not the first processing in step 1201 or if the value of each storage element in the first internal state differs from the storage logical value in the element table after the processing in step 1202, The values of the fields are exchanged (step 1203).

(3) Referring to the logical function name of the element to which the signal line whose value has been replaced is connected, it is determined whether the element is an FF, an external output terminal, or any other. (Steps 1204 and 1205).

(4) If it is determined in step 1205 that the element to which the signal line is connected is neither FF nor an external output terminal, the value of the output terminal of the element is calculated based on the logic of the element. If the logical value is different from the described logical value in the table, the value of the field of the internal state is replaced (step 120).
6).

(5) After the processing in step 1206 or, in the judgment in step 1205, if the element to which the signal line is connected is an FF or an external output terminal, the connection destination of the signal line whose value has been replaced is Determine if there are more elements. If there is still an element to which the signal line is connected, the processing from step 1204 is repeated (step 120).
7).

(6) If it is determined in step 1207 that there is no element to which the signal line is connected, the value of each storage element in the first internal state is stored in the field of the value of each storage element in the second internal state. Copy. When the value transmitted to the data input terminal D and the held value Q are different for each FF, the value of the field in the second internal state is changed to the value transmitted to the data input terminal D. (Step 12
08, 1209).

(7) Steps 1204 to 120 described above
6 is repeated for the field in the second internal state, and it is checked whether there is an element to which the signal line whose value has been exchanged is connected. Steps 1204-120 while the element is present
6 is repeated for the field in the second internal state, and the process ends when there is no longer any element to which the signal line whose value has been replaced is connected (step 1210).
1211).

Next, a description will be given of a method of another embodiment of the present invention for obtaining a logical value to be allocated to the storage element in the flow shown in FIG.

There are many known methods for obtaining a practical pseudo-random number sequence by a simple algorithm. For example, Paul H. Ba
Built-In Test for VLSI: Pseudorandom Te by rdell
chniques (1987) describes a method using a feedback register. The method using a random number cannot limit a signal transition to a specific propagation path, and there is always a possibility that the signal transition propagates along a path that requires the longest time. In this case, the test time interval may be the maximum value of the path through which the signal transition can propagate, and a value obtained by subtracting the time interval accuracy parameter from the test time interval may be used as the determination value in step 111 shown in FIG. In the case of the circuit example shown in FIG.
The path from the element 220 to the element 223 is the longest, and the value is in units of 1.8 hours.

When a test is performed using a random number sequence or a pseudo-random number generation circuit that is easy to perform a test generation process, by applying the present invention, a fault supposed portion that can detect only a fault with a large delay is detected. It can be recognized as undetected. That is, if a test pattern in which the signal transition propagates only to the signal propagation path including the undetected fault assumption part is generated and tested at a necessary test time interval, a fault with a small delay is detected for all the fault assumption parts. Can be detected. The number of times of test generation requiring a large amount of calculation can be reduced by reducing the number of target fault assumed parts, and the degree of detectable delay can be reduced.

FIG. 14 is a flowchart for explaining a processing operation of still another embodiment of the present invention for obtaining a logical value to be allocated to a storage element in step 105 in the flow shown in FIG. 1, and FIG. 15 is a step 1404 in the flow shown in FIG. ~
FIG. 16 is a view for explaining an example of path information stored and ordered in 1406. FIG. 16 is a view for explaining means for obtaining a condition of transition signal propagation using the D algorithm in step 1407 of the flow shown in FIG. FIG. 17 is a diagram illustrating an example of a first internal state obtained based on the inspection cube shown in FIG. 16. Hereinafter, FIG. 1 will be described with reference to FIGS.
4 will be described. In the example described with reference to FIG. 14, in order to suppress the processing time due to the repetitive processing in the search for the transition signal propagation path to be within a certain range, a determination to abandon each search processing and a reference for determination are provided. Things.

(1) Processing in Steps 1401 to 1403 It is determined whether or not to perform the processing first, and if the processing is to be performed first, the type of the transition signal propagation path to be searched for one fault Enter a number. If it is not the first processing, or in the processing of step 1409 described later,
If a decision is made to repeat the search by selecting a different type of route for the fault under trial or to proceed to the route search process for another fault, the search for a route for another fault has not yet been completed. Upon detection, a failure is assumed at an untried failure hypothesis point. Here, the second input of the twenty-eighth element 237 in the circuit example of FIG.
Consider a case where a failure is assumed to be the 35th of No. 02.

(2) Processing in Step 1404 Next, the propagation time of the signal propagating path from the assumed fault point to the input side and the output of the storage element is determined, and the numerical value and information for specifying the path are obtained. Store. That is, when a possible propagation source and a propagation path of the transition signal are searched from the fault assumption point toward the input side, information is obtained as shown in FIG. There are two propagation paths, and path numbers 1501 are numbered s1 and s2, respectively. The storage element numbers 1502 as starting points are the twentieth element 220 and the twenty-first element 221, respectively, and the wiring numbers and element numbers of the paths are as shown in the figure. FIG.
In FIG. 5, a column 15 showing the wiring number and the element number of the path
03 wiring numbers are enclosed in parentheses to distinguish them from element numbers. The wiring number corresponds to the number described in the first column of the input destination table 602. The path s1 starts from the 20th element 220, passes through the 24th element 233 and the 26th element 235, and reaches the second terminal of the 28th element 237. The propagation time of each path can be obtained by referring to the propagation times shown in FIGS. 9 and 8, and each is described in the column 1504 of the propagation time.

(3) Processing in Step 1405 Next, the path from the assumed fault point to the output side is calculated, the propagation time of the signal propagable path from the output of the storage element is determined, and the numerical value and information for specifying the path are obtained. Store. That is, a possible transmission destination and a propagation path of the transition signal are searched from the 35th wiring having the above-mentioned fault assumption point toward the output side. The result is as shown in FIG. In the example described, three types of propagation paths are possible, numbered k1, k2 and k3, respectively.

(4) Processing in Step 1406 Next, the route stored in Step 1404 and Step 1
Regarding the pair with the path stored at 405, the propagation time of the path from the output of the storage element to the input terminal of the storage element through the fault assumption point is ordered from the longest. FIG.
The combination of the path shown in FIG. 15A and the paths shown in FIG. 15B, that is, the path from the output terminal of the storage element to the input terminal of the storage element through the assumed fault point is ordered in descending order of the propagation time. You. The result is shown in FIG. 15C, and there are six possible combinations.

(5) Processing in step 1407 Next, among the untried ones of the set of propagation paths ordered in step 1406, the one with the largest propagation time is selected, and the transition signal is propagated through that path. A search is made for the assignment of a logical value to a storage element that satisfies the condition. That is,
A transition signal propagation condition is searched for a set that requires the longest propagation time among a set of circuits that have not yet been searched for whether the transition signal propagation condition is satisfied. In this search, a pulse is applied to the system clock input terminal P11 (208), a signal transition occurs at the output terminal of the storage element at the start point of the path, and this transition propagates through the selected propagation path and the storage element at the end point. Is to allocate a logical value to each storage element to reach the input terminal of the first path, that is, to obtain a first internal state satisfying the path activation condition. This search can be performed by applying the D algorithm and the like described in “Digital Circuit Fault Diagnosis (above)” by Yukizo Kinoshita.

The D algorithm has a logic value “D” representing a state of being logical “1” in a normal state and a logical “0” in a failure state and a logically inverted value thereof, that is, a logical “0” in a normal state and a logic “0” in a failure state. A check cube, which is a condition for propagating a logical value “＾ D” representing a state of logical “1” to an external output terminal, is obtained. For example, a signal transition from “0” to “1” is “D”, and a signal transition from “1” to “0” is “＾”.
By applying the D algorithm instead of "D", the propagation condition of the signal transition can be obtained.As an example, a method of obtaining the condition for propagating the signal transition from "0" to "1" is shown in FIG. The first route, which is the longest route shown in FIG.
The process of selecting the number set (s1, k1) and obtaining the inspection cube is shown in FIG. 16A, and this will be described.

First, an element number 26, which is an element on the path,
The D intersection of the propagation D cubes 24, 28, 29 and 32 is taken. The result of the D intersection is described for each wiring number, and the inspection cube of the intermediate result is shown in the sixth row. The D algorithm is
This corresponds to a state where the D drive is completed. Next, D intersections are taken with the basic cubes of the elements (element numbers 23 and 27) connected to the wires of the numbers described in FIG. 16 and whose input / output values have not yet been determined. As a result, D for element number 23
The intersection is successful, but the D intersection for element number 27 is
It can be seen that the wiring number 33 is inconsistent. this is,
This means that there is no logical value assignment that satisfies the condition for activating the first set of paths.

(6) Processing in Steps 1408 and 1409 It is determined whether there is no logical value allocation satisfying the condition for activating the route in the search in Step 1407. If there is no logical value allocation that satisfies the condition, the processing moves to "yes" to determine whether to assume another fault or to try a path with the next longer propagation time.

(7) Reprocessing in Steps 1407 and 1408 and Processing in Step 1410 If it is determined in step 1409 that the upper limit number of trial propagation path types per fault has not been reached, the next path is used. Then, the second set (s1, k2) in FIG. 15C is selected, and the process returns to step 1407 to obtain the inspection cube again. FIG. 16B shows the process of obtaining the inspection cube in this case. D between the intermediate inspection cube corresponding to the state after completion of the D drive and the basic cube of the 23rd element
By taking the intersection, an inspection cube on the fourth row in FIG. 16B is obtained. The wiring numbers 32, 34, and 28 are respectively connected to the 21st, 19th, and 18th output terminals of the storage element, and the required values “0”, “1”, and “1” for each wiring are kept as they are. The value is taken in the first internal state of each storage element. Since no inconsistency has occurred at this stage, next, a signal transition from "0" to "1" is generated in the twentieth storage element which is the start point of the transition signal, and the other storage element to which the value is assigned is generated. (No. 21, 19, 18) The condition that the value does not change is determined. Since the output of the twentieth storage element is "0" in the first internal state, the value allocation to the twentieth storage element is "0".

Since it becomes "1" after a pulse is applied to the clock input, in the first internal state,
"1" needs to be propagated to the data input terminal of the twentieth storage element. Other storage elements (21st, 19th, 18th)
Regarding (number), no transition occurs if the same value as the value assigned in the first state has propagated to each data input terminal. Therefore, "1", "1", "1", and "0" are requested and connected to the wiring numbers 18, 20, 22, and 24 connected to the data inputs of these storage elements, respectively. An elementary cube is selected, and D intersection is repeated to obtain an inspection cube.

FIG. 16C shows the result of the above processing. "1", "1", "1",
It is sufficient that “0” and “0” propagate, which are transmitted to the connected storage elements No. 7 to No. 10 respectively, “1”, “1”, “1”,
This indicates that it is only necessary to write “0”. By the processing of step 1407 described above, 6
Among the types of transition signal propagation paths, one of the paths having the longest propagation time capable of detecting the assumed fault is the second (s1, k
FIG. 17 shows the first internal state which is written by scanning with a propagation time of 1.5 hours.

According to the above-described processing according to the embodiment of the present invention, among the transition signal propagation paths for fault detection that can be given as candidates, the propagation time that can be found within a certain processing time range Test sequences that use long paths,
It is possible to increase the probability of detecting a failure with a smaller degree of delay in all the fault assumption parts. When a test sequence for detecting a certain fault is generated according to the above-described embodiment of the present invention, if the degree of detectable delay is a certain value, generation of the test sequence is abandoned to save processing time. This is also easy. In this case, an element having a total propagation time smaller than a certain value in the table illustrated in FIG. 15C may be invalidated.

FIG. 18 is a flowchart for explaining the processing operation of still another embodiment of the present invention for obtaining the logical value to be allocated to the storage element in step 105 in the flow shown in FIG. 1, and FIG. 19 is the processing in step 1803 in FIG. FIG. 20 illustrates an example of the obtained information.
FIG. 21 is a diagram for explaining a generation process of an inspection cube in the processes of 805 to 1819, and FIG. 21 is a diagram showing an example of a first internal state obtained by the process shown in FIG.

According to the present invention, in the test generation process, by searching for a path having the largest possible transition signal propagation time value, a test sequence having a small delay time and a high fault detection capability can be obtained. . Regarding the processing in this case, the flow shown in FIG. 18 will be described with reference to FIGS.

(1) Processing in Steps 1801 to 1803 When the processing in step 105 is started, it is checked whether or not the processing is the first processing. A maximum value T1 of the propagation time of the propagation path of the transition signal to the storage element for all the input terminals of the element,
The maximum value T2 of the propagation time of the propagation path of the transition signal from the storage element is obtained, and the sum T of these values is stored. The processing in steps 1802 and 1803 here may be performed once prior to the processing in step 1804 after searching for a detection path assuming a failure.

Referring to FIG. 19, an example in which step 1803 is executed using the element delay time shown in FIG. 8 and the wiring delay time shown in FIG. 9 for the circuit example shown in FIG. I do.

The maximum value T1 of the propagation time of the propagation path of the transition signal to the storage element at the input terminal of each element is determined by following the wiring from the data input terminal of the storage element to its input terminal,
It can be obtained by summing the delay time of each wiring on the path and the delay time of each element. If there are multiple routes, select the one with the larger value. For example, in the case of the input terminal of the twenty-ninth element 238 in FIG. 2, the delay time of the path to the thirty-fifth storage element is in units of 0.3 hours, but the delay time of the path to the thirty-fourth storage element is zero. .6 time unit, and 0.6 time unit is used as the maximum value T1 of the propagation time. The maximum value T1 of the propagation time has the same value for the input terminals of the same element.

The maximum value T2 of the propagation time of the propagation path of the transition signal from the storage element at the input terminal of each element is determined by following the wiring from the output terminal of the storage element to its input terminal, and the delay time of each wiring on the path. The delay time of each element can be obtained in total. If there are multiple routes, select the one with the larger value. For example, the 29th element 2 in FIG.
38, the 19th, 20th, and 2nd input terminals
There are paths from the first storage element, 0.6, respectively.
1.2, 0.9 hours. Therefore, a 1.2-hour unit is used as the maximum value T2 of the propagation time. In the example shown in FIG. 19, a total value T1904 of T1 and T2 is also shown. Since the input terminals of each element correspond to the wiring numbers on a one-to-one basis, each value is stored in association with the wiring number.

(2) Processing in Step 1804 A portion where input / output terminals of the element have not been tried to assume a failure is searched for and selected, and a failure is assumed. Once a fault has been selected, it is assumed to have been tried. In the example described, FIG.
It is assumed that the second terminal of the 28th element in the circuit example shown in FIG. The second terminal of the 28th element corresponds to the 35th wiring number. Here, it is assumed that a type of fault delays the propagation of the transition signal from “0” to “1”.

(3) Processing in step 1805 In the subsequent processing, the signal transition is made to correspond to the logical value “D” or “＾ D” (inverted value of D), and the element is assumed to be faulty using the D algorithm. Search for the first internal state that propagates the longest possible path through which the signal transitions pass through the input terminal of. That is, first, the signal transition from “0” to “1” is made to correspond to the logical value “D”, and “D” or “ΔD” propagates from the input terminal to the output terminal of the device assuming the failure. Select the D cube. If there are a plurality of untried cubes that satisfy this condition, “D” or “＾
The input terminal to which D "is allocated is within the range of the options, and the cube having the largest sum T1904 of the propagation times T1 and T2 is selected.

In the case of the conventional D algorithm for the stuck-at fault, a basic D-cube of the element assuming the fault is selected. In the embodiment of the present invention described here, the output terminal of the storage element is stored at the starting point. Since “D” or “ΔD” is propagated through the path passing through the assumed fault point to the input terminal of the element, the propagation D cube is also selected for the assumed fault element. Using the propagation D cube as an inspection cube, the cube of each element required in step 1806 and thereafter to be
The intersection is repeated to find a test cube corresponding to the first state of interest.

(4) Processing in Steps 1806 to 1808 In the processing in this step, the implication operation, that is, the D of the uniquely selected basic cube and inspection cube
Make an intersection. If a contradiction occurs, an untried option in the last non-unique selection is selected and the process is repeated.

(5) Processing in Step 1809 The untested propagation D-cube is selected from the one with the highest priority and crossed with the inspection cube. At this time, it is assumed that the cube selected once has been tried until another selection is made in step 1804 or 1805 described above. The above selection is, if you choose D frontier,
The selection is made so that the propagation D cube having the longer propagation time T of the input terminal to which “D” or “ま た は D” is assigned is selected, and when the extended D frontier is selected, the connection destination of the output terminal of the element is selected. Select the extended D frontier in which the propagation time T of the input terminal to which “D” or “ΔD” is assigned is a large value, or “D” or “ΔD”
Is selected to select a propagation cube whose propagation time T at the input terminal of the element to which is assigned a large value.

That is, “D” or “ΔD” is propagated from the assumed fault location to the input / output terminal of the storage element. The operation of propagating to the input terminal of the storage element corresponds to the D drive of the conventional D algorithm for the stuck-at fault. There is no operation equivalent to the conventional algorithm for the operation of propagating back to the output terminal of the storage element, but "D" or "$ D" is allocated to the connection destination of the output terminal, and the input terminal is not allocated yet. Elements other than the storage element that has not been made are regarded as an extended D frontier corresponding to the conventional D frontier, a propagation D cube is selected so that "D" or "$ D" is allocated to the input terminal, and a D intersection is taken. The operation can be repeated and propagated back. When selecting the D frontier and extended D frontier and selecting the propagation D cube, "D" or "ま た は
The propagation time T1904 of the input terminal through which D ″ propagates is maximized for untried options.

(6) Processing in Step 1810 It is checked whether or not the processing in Step 1809 is inconsistent, that is, whether or not the D intersection has failed. An untried option in the last non-unique selection is selected and the process is repeated.

(7) Processing in Steps 1811 to 1813 In the processing in the steps in this step, the implication operation, that is, the D of the uniquely selected basic cube and inspection cube
Make an intersection. If a contradiction occurs, an untried option in the immediately preceding non-unique selection is selected and the process is repeated, but in step 1819 described later, step 1
If the number of consecutive inconsistency recognitions in step 812 and step 1816 to be described later exceeds the numerical value input in step 1802, the process does not return to step 0809, but returns to step 1804.
The process is repeated by adopting an untried option in the last selection of or 1805.

(8) Processing in Step 1814 It is checked whether or not the D frontier or the extended D frontier exists. "D" or "$ D" from 1804 to 1813
Continue searching for the propagation path of.

(9) Processing in Steps 1815 to 1817 When it is confirmed in Step 1814 that the D frontier and the extended D frontier have reached the storage element and have disappeared, first, the matching operation, that is, the basic cube and the test cube In the process of taking the D intersection, as in the conventional D algorithm, a value is assigned to the connection destination wiring of the output terminal, but an element having an input terminal to which no value is assigned is uniquely selected. The D intersection of the basic cube and the inspection cube is taken. If the number of consecutive inconsistencies in steps 1812 and 1816 exceeds the numerical value input in step 1802, the process does not return to step 1809, and an untried option is adopted in the last one of steps 1804 and 1805. And repeat the process. The process ends when there are no more cubes that can be selected due to the D intersection.

In the processing of steps 1805 to 1819, a failure of the type that delays the propagation of the transition signal from “0” to “1” is assumed to be at the second terminal of the 28th element. The generation process is shown in FIG. In the inspection cube of the last row, the wiring numbers 28, 29, 30, 32, and 33 have logical values “1”,
“D”, “0”, “0”, and “1” are allocated. The logical value “D” assigned to the wiring number 29 is
This means that the 0th storage element holds “0” in the first internal state and “1” propagates to the data input terminal. Therefore, the first of the storage elements at each connection destination
8, 20, 22, 21, and 19 input terminals, that is,
Requesting the logical values “1”, “1”, “0”, “0”, and “1” to the wiring numbers 18, 22, 26, 24, and 20, respectively, and performing the matching operation shown in FIG. The value held by the necessary storage element can be obtained, and an inspection cube as shown in FIG. From the above results,
The first internal state is determined as shown in FIG.

According to the embodiment of the present invention which performs the processing shown in FIG. 18, it is possible to perform an inspection using a path having the longest possible propagation time through which a signal transition passes through a fault assumption point.
According to this example, even with a test method in which the test time interval is not adjusted for each fault, a test with the highest time accuracy within a practically feasible range can be performed for all faults.

FIG. 22 is a flowchart for explaining the processing operation of still another embodiment of the present invention for obtaining the logical value to be allocated to the storage element in step 105 in the flow shown in FIG. 1, and FIG. 23 is the processing in step 2217 in FIG. FIG. 9 is a diagram illustrating an example of a first internal state obtained. Hereinafter, this will be described.

(1) Processing in Steps 2201 to 2219 The processing in Steps 2201 to 2219 in the flow shown in FIG. 22 is the same as the processing in Steps 1801 to 1819 in the flow shown in FIG. In the flow shown in FIG. 18 described above, if there is no basic cube to be subjected to the matching operation in step 1817, the logical value at that time is set to 1
As a result of obtaining the first internal states, one process of step 105 in the flow shown in FIG. 1 is completed. On the other hand, in the case of the flow shown in FIG.
Therefore, the processing after it is determined that there is no basic cube to be subjected to the matching operation is different from that in the case of FIG.

(2) Processing in Steps 2220 to 2222 After it is determined in Step 2217 that there is no basic cube to be subjected to the matching operation, in Step 2220 a cube already intersected with the inspection cube by a D intersection is determined. It is determined whether there is an undetected and unsuccessful failure assumption point for an element that does not belong. If so, the process proceeds to step 2221 and a failure is assumed. Next, in step 2222, the signal transition is made to correspond to the logical value “D”, and “D” or “＾ D” propagates from the input terminal to the output terminal of the element that has assumed the failure via the failure assumption point. Propagation D that satisfies the condition
Select a cube. If there are a plurality of untried cubes satisfying the above conditions, the input terminal to which "D" or "$ D" is allocated is within the range of the option and the propagation time T
The cube having the maximum sum 1904 of 1 and T2 is selected. The processing of the step here is similar to that of step 2205, but the processing of step 2205 makes the selected propagation D cube a new another inspection cube, while the propagation D cube selected in step 2221 Take the D intersection with the test cube.

The processing then merges with step 2206, and the propagation of the logical value “D” or “＾ D” (the inverted value of D) and the propagation Logical values are allocated to the storage elements that enable After step 2220 is established, step 2218 is executed.
Even if the condition of (2) is not satisfied,
04, no feedback is given to step 2205, and another option in the immediately preceding selection including step 2221 is selected.

The first internal state obtained by the processing shown in FIG. 22 described above has a detection capability for a plurality of types of faults, and selects and tests a path that requires the longest time for each fault. Therefore, even when a test is performed with a wider test time interval, a failure with a small delay can be detected.

Considering a case where a failure in which the signal transition from “0” to “1” is delayed at the output terminal of the 23rd element 232 in the circuit example shown in FIG. 2 is considered, the processing of the flow shown in FIG. , A first internal state for propagating signal transitions from the eighteenth storage element 218 to the thirty-fifth storage element 224 is determined. FIG. 23 (a) shows the values to be stored in the respective storage elements obtained in this way. At this point, in the processing, the condition of step 2216 is not satisfied. “1” is assigned to the first input terminal of the thirtieth element, but since there is no request for the output terminal, it is not subjected to the matching operation. Therefore, none of the element No. 25 has a corresponding D-cross with the inspection cube at this time.

The next process proceeds to step 2220. Further, in step 2221, it is assumed that a fault whose signal transition from "0" to "1" is delayed is selected at the output terminal of the twenty-fifth element. The 30th element 239 and the 31st element 240 are the propagation destinations of the transition signal passing through the 25th element, but the propagation to the 30th element having the larger value of the propagation time T1904 is selected. This is the first of the 30 th element 239
This means that a propagation D cube to which "1" is assigned to the No. 1 input terminal is selected. However, as described above, the process is continued because it does not conflict with the assignment of the inspection cube at this time. Next, when the process proceeds to step 2220, if there is no fault that can be assumed, the process ends. The first internal state obtained at the end of this processing is shown in FIG.

Step 103 in the flow shown in FIG.
The description format of the information of the signal delay time held by each part of the normal circuit to be tested which is input in step (1) can be further simplified, and the capacity of the storage device required to hold the information can be reduced.

FIG. 24 is a view for explaining a description example of information of signal delay time for the circuit example shown in FIG. 2, and FIG. 25 shows a propagation time value referred to for each input terminal when a path is selected.
FIG. 5 is a diagram showing an example created from the information of FIG.

The row numbers in FIG. 24 correspond to the row numbers in the input destination table 602 in FIG. Input destination table 602
Each row corresponds to each input terminal of each element. The signal propagation time shown in FIG. 24 is the time required for the signal transition to propagate from each input terminal illustrated in FIG. 8 to the output terminal of the element to which the signal belongs, and the signal transmission time connected to the ship destination of each input terminal illustrated in FIG. And the time required for the signal transition to propagate from the output terminal to the corresponding input terminal. The calculation of the signal transition propagation time of the selected path from the output terminal of the storage element to the input terminal of the storage element can be obtained by summing up the corresponding values on the path.

In the example in which the propagation time value referred to for each input terminal at the time of selecting the path shown in FIG. 25 is created from the information in FIG. 24, the wiring number 2501, the propagation time T1 (2502) to the storage element, the storage Propagation time T2 (25
03), the total propagation time T2504 between the storage elements is the wiring number 1901, the propagation time T1 to the storage element T1 (1902), and the propagation time T2 from the storage element shown in FIG.
(1903), which corresponds to the total inter-storage-element propagation time T1904 and is referred to in the same manner as in FIG. For example, the propagation time T1 (2502) is determined by determining the input terminal of any storage element from the output terminal connected to the wiring of the wiring number to the output terminal of the element to which the input terminal connected to the wiring of the wiring number belongs. The path to the terminal can be obtained by adding the numerical values in the corresponding row of FIG. 24 each time the signal passes through the input terminal.

FIG. 26 is a flowchart for explaining the outline of the processing operation of test sequence generation using another embodiment of the present invention, which will be described below.

In the flow shown in FIG.
The processing from step 601 to step 2604 is the same as the processing from step 101 to step 104 in the flow shown in FIG. 1 in order, and the processing from step 2606 to step 2614 is in order from step 106
To 114 are the same. The function of determining the first internal state held in step 105 shown in FIG.
Holds four.

In the flow shown in FIG.
After the processing of 604 is completed, the first internal state is obtained by using the random number sequence in the processing of step 2605. Then, in the processing from step 2606 to step 2613, the detection possibility of the undetected failure at that time is determined. If there is a failure determined to be undetected, the processing in step 2614 determines
The process moves to step 2615. In the last first internal state generated in the process of step 15, if the number of faults determined to be detected is small and the fault detection efficiency is not sufficient, the process proceeds from step 2615 to step 2616. The failure detection efficiency can be determined, for example, by the number of detected failures in the last first internal state with respect to the assumed number of overall failures.

In the process of step 2616, the first internal state is obtained according to steps 1801 to 1819 of the flow shown in FIG. 18. However, in the process of step 2616, the first internal state cannot always be obtained. If the first internal state cannot be obtained, it is determined that the test generation has failed, and the processing in step 2617 ends.

When the test sequence is obtained by the above-described embodiment of the present invention, if the processing time is too long, the present invention uses a random number sequence without impairing the ability to detect a fault with a small delay. , The processing time of the processing for determining the first internal state can be saved.

Even if the test sequence is the same for the same circuit, a fault determined to be detected by the difference between the test time interval and the first parameter value representing the degree of signal propagation delay of the assumed delay fault. Are different. In such a case, if the ratio of the number of detectable faults to the total number of assumed faults at each value is displayed using a plurality of first parameter values, it is possible to detect the test sequence for the distribution of the degree of delay of the delay fault. Ability can be evaluated.

FIG. 27 is a flow chart for explaining the outline of the processing operation of test sequence generation using still another embodiment of the present invention, which will be described below.

In the flow shown in FIG.
The processing of steps 701 to 2710 is the same as the processing of steps 101 to 110 of the flow shown in FIG. 1, and the processing of steps 2713 and 2714 is the processing of steps 113 to 114 of the flow shown in FIG. Is the same as Then, in the process of step 2711 in FIG. 27, a plurality of first parameters are used, and a detection determination value is obtained for each first parameter. In the process of step 2712, the detection possibility is determined for each detection determination value. In the case where control is performed without assuming a fault determined to be detected in subsequent processing, a fault determined to be undetected for at least one determination value in the processing in step 2707 is assumed.

As can be seen from the description of the embodiment of the present invention described above, the essence of the present invention is to combine the value of the delay time increase due to the fault with the model of the delay fault to set conditions for the manifestation of the fault. It is in. When the test sequence is obtained, a fault having a small increase in delay time is detected by selecting a route having a longest propagation time as much as possible in the search for a transition signal propagation route involved in the detection, passing through the fault assumption point. Be able to do it.

When a detectable fault is determined by a test sequence, the propagation path from the point of occurrence of a signal transition passing through the fault assumption point to the observation point is defined as the difference between the propagation time when no fault is assumed and the test time interval. The detection is determined only when the difference is sufficiently smaller than the value of the increase in the delay time due to the fault, and the circuit portion capable of detecting the fault with a small increase in the delay time is distinguished from the circuit portion that cannot detect the fault, and the detection capability is evaluated. It can be performed.

When a test sequence is obtained or a detectable fault is determined, a set of effective transition signal propagation paths includes the value of the delay time increase due to the fault, the circuit delay time, and the test time interval. Such information can be obtained independently of the generation of the test sequence.

According to the present invention, by preliminarily retaining information on a set of propagation paths effective for detection, it is possible to simplify a process for obtaining a test sequence or determining a detectable fault.

FIG. 28 is a flow chart for explaining the outline of the processing operation of test sequence generation using still another embodiment of the present invention, which will be described below. This figure 2
The flow shown in FIG. 8 simplifies the process of obtaining a test sequence or determining a detectable fault by holding information on a set of propagation paths effective for detection in advance.

In the flow shown in FIG.
Steps 801 and 2802 correspond to steps 101 and 102 in the flow shown in FIG. When it is determined in step 2803 that a failure can be detected, a set of valid transition signal propagation paths is input. If the propagation and observation of the transition signal are established for each path, information for specifying a fault to be detected is also input. Step 2804, Step 2805, Step 2
The processing of 806 corresponds to the processing of steps 105, 106, and 108 in the flow shown in FIG. 1, respectively. Further, the processes corresponding to Step 103, Step 104, and Step 107 in the flow shown in FIG. 1 are unnecessary.

In the process of step 2807 in FIG. 28, the transition signal propagation path recorded in step 2806 is
It is determined whether or not it is included in the set of effective propagation paths input in step 2803. A plurality of propagation paths are defined for each combination of a transition signal generation point and an observation point. In the processing from step 2808 to step 2809, the possibility of failure detection is determined. In the recording in step 2807, a transition signal is propagated from the output terminal of a certain storage element to the input terminal of a certain storage element, and the element group on the propagation path is the propagation path set input in step 2803. In the case of the same element group on the path of the propagation path portion having the same storage element as the transition occurrence point and the storage element as the observation point, the failure of the propagation path portion is determined to be detected. Since the failure is processed as a representative of the propagation path linked by the input information of step 2803, in the processing of step 2810 corresponding to step 113 in the flow shown in FIG. It is determined whether or not there is. The processing in step 2811 is
This corresponds to the processing of step 114 in the flow shown in FIG.

Since the test sequence generation means according to the prior art determines that a delay fault can be detected regardless of the degree of delay, the test sequence is added so that the test sequence can detect a fault with a small delay. I couldn't go. For this reason, conventionally, even if a test sequence determined to be detectable for all of the assumed fault parts is generated, the integrated circuit is tested using the test sequence, and the apparatus is assembled from only those determined to be non-defective, the degree of delay is small. In some cases, small failures were missed without being detected by the integrated circuit test, thereby deteriorating the performance of the device.

According to the above-described embodiments of the present invention, in any of the embodiments, a test sequence is detected for all the assumed fault parts through the transition signal propagation path that most affects the performance. Is small,
Failures that affect the performance of the device can be prevented from being overlooked.

When an integrated circuit is used near the design limit of operation speed, even a very small delay becomes a problem, and the failure density, which is an expected value that appears per unit area of the integrated circuit, becomes a problem. Becomes relatively large. To keep the number of missed high-density failures low,
A test sequence with a high detection rate for the failure model is indispensable. However, the prior art selects delay paths such as selecting some of the paths having the longest propagation times or creating a test sequence that enables a logic designer to test the part that affects performance. There was no means to guarantee the detection rate for minor faults.

According to the above-described embodiments of the present invention, in any of the embodiments, a fault assumption site that cannot be detected if a fault with a small delay is present is identified, and a fault with a small delay at that site is identified. A test sequence can be generated, and the performance of a device where high speed is important can be guaranteed.

While the invention has been described in conjunction with the drawings by way of the foregoing detailed description, various modifications in form or detail may occur to those skilled in the art. And can be implemented without departing from the scope. Hereinafter, the above-mentioned changed items will be disclosed.

(1) The connection information of the logic elements of the logic circuit to be tested and the wiring between the elements, and the information of the signal propagation time of each element and each wiring, are input to the first logic circuit included in the logic circuit to be tested. Initializing the storage element group to a first internal state, and then applying a plurality of transition signals at test time intervals from a test apparatus to change the first storage element group to a second internal state; A test apparatus reads a value held by a first storage element group, generates a test sequence to be compared with an expected value, and uses the test sequence to detect a fault in the circuit. A first memory element group is initialized to a first state by using design information of a logic element constituting a target logic circuit and wiring between elements, a plurality of transition signals at test time intervals are applied, and a second memory element group is applied. Holding the storage element in the state A first means for reading a value and generating a test sequence for comparison with an expected value; and assuming a delay fault in the test target logic circuit, simulating a logical operation of the test target logic circuit with respect to the test sequence, A transition from the first internal state to the second internal state of the storage element group causes a signal transition at an output terminal, propagates the signal transition into a circuit under test, and causes the propagation path to assume the fault. From the second storage element or a subgroup of external input terminals at the time of testing, such that the signal transition at the fault assumption site propagates through the circuit under test, and the propagation reaches the input terminal. , Whether there is a path to a third storage element or a subgroup of external output terminals during a test, and when the path exists, an output terminal of the second storage element subgroup or the external input terminal subgroup. From the third A value corresponding to the propagation time of the propagation path of the transition signal to the input terminal of the storage element subgroup or the external output terminal subgroup is calculated, and the maximum value of the signal propagation time is a threshold value corresponding to the test time interval. And a second means for determining that detection is possible when the difference is between a value obtained by subtracting a first parameter value representing a degree of signal propagation delay of a delay fault assumed from the threshold value, or the first means. The signal transition propagates from a storage element or a partial group of the external input terminals that causes a signal transition to an output terminal between a first internal state and a second internal state, and reaches the input terminal. Between the threshold value corresponding to the maximum value of the transition signal propagation time of the storage element or the test target path to the partial group of the external output terminals, and a value obtained by subtracting the first parameter value from the threshold value. Detectable in some cases A delay fault detection method for a logic circuit, comprising: generating a test sequence by performing a fault simulation including the third means for determining that a logic circuit has failed; and detecting a fault in the logic circuit by using the generated test sequence.

(2) In the method for detecting a delay fault in a logic circuit according to the item (1), the first means may include a first internal state, that is, a logic held in each storage element related to the test or an external input terminal at the time of the test. Values are obtained in correspondence with each term of the random number sequence, and the third means includes a threshold value corresponding to a maximum value of a signal propagation time between all the storage elements to be tested and the external input / output terminals; A method for detecting a delay fault in a logic circuit, comprising determining that detection is possible when the difference is between a threshold value and a value obtained by subtracting a first parameter value.

(3) In the method for detecting a delay fault in a logic circuit according to the item (1), the first means inputs a second parameter defining an upper limit of a calculation amount for obtaining the first internal state. Means, a fifth means for assuming a delay fault in the circuit under test, and a first storage included in a sub-group of fourth storage elements having a circuit connection relationship affecting signal transition at the fault assumed part. A path from an element or an external input terminal at the time of a test to a second storage element included in a fifth storage element subgroup having a circuit connection relationship through which a signal transition of the fault site can propagate or an external output terminal at the time of a test Sixth means for calculating the signal propagation time of the first storage element or the external storage terminal or the second storage element or the external output terminal from the fourth and fifth subgroups. If there is a combination, Select a longer set of time, the first
By the application of the first transition signal in the internal state of
Causes a signal transition in which the value held by the storage element or the external input terminal is logically inverted, and the value of the fault assumed part in the second state is a logically inverted value of the value of the same part in the first state. In the second state, the condition for the signal transition of the fault assumed part to propagate to the second storage element or the external output terminal is satisfied, and the first storage element subgroup or the external input terminal Searching for an assignment of logical values, and if there is a logical inconsistency in said assignment,
Alternatively, when the amount of calculation required for the search exceeds the value of the second parameter, a seventh unit that selects the next longest set of the time and repeats the search is provided.
A method for detecting a delay fault in a logic circuit, comprising determining a first internal state.

(4) In the method for detecting a delay fault in a logic circuit according to the first aspect, the first means inputs a second parameter defining an upper limit of a calculation amount for obtaining the first internal state. Means, fifth means for assuming a delay fault in the circuit under test, and input terminals of all elements included in the transition signal propagation path between the storage element and the external input / output terminal at the time of testing. The maximum value of the numerical values corresponding to the respective propagation times of the plurality of paths that propagate to the storage element or the external output terminal, and the signal transition propagates to each of the input terminals. A first value corresponding to a maximum value among numerical values corresponding to respective propagation times of a plurality of paths from the output terminal or the external input terminal of the storage element having a connection relationship capable of being connected to each of the input terminals. Eighth to hold numerical value Means, signal transition occurs in the fault assumption site, the signal transition propagates in the test object circuit,
In a process of searching for a possible first internal state in which a transition signal propagation path is activated, which reaches an input terminal of a storage element or the external output terminal, the transition at an arbitrary element output terminal is determined by a plurality of element inputs. When propagating to the terminal, the first input terminal having a larger first numerical value of the input terminal, which is held by the eighth means, is set as a higher priority candidate of the propagation path, and the output terminal is set to the output terminal. In the case where the element causing the transition has a plurality of input terminals, the input terminal having the first numerical value of the input terminal, which is held by the eighth means, having a larger value is regarded as a higher priority candidate of the propagation path. A value that enables propagation is assigned to an input terminal of an element on the propagation path, and the logical value assignment in the search for the propagation path is determined to be infeasible inconsistent with the operation of the logic circuit to be tested, or Rino calculation amount of the search processing is the second
Ninth means for repeating selection of a path having the next highest priority next to the propagation path candidate when it is determined that the parameter is larger than the parameter of the first path, and obtaining a first internal state. A method for detecting a delay fault in a logic circuit.

(5) The method for detecting a delay fault in a logic circuit according to the third or fourth item, wherein the fifth, sixth or eighth,
Repeating the seventh or ninth means to obtain a plurality of different first internal state candidates, and between each one internal state candidate, the same storage element in the test target circuit or an external input during the test. If there is no assignment to the terminals where the logical values “0” and “1” contradict each other, a logical '1' is set between the first internal state candidates for the same storage element or the external input terminal. Is assigned and logical “0” is not assigned, a logical “1” is assigned to the storage element or the external input terminal, and a logical “1” is assigned to the same storage element or the external input terminal. When the logical "0" is allocated and the logical "1" is not allocated, by assigning a logical "0" to the storage element or the external input terminal, the first internal state is obtained. Have a means to seek Delay fault detection method of the logic circuit according to claim Rukoto.

(6) In the method for detecting a delay fault in a logic circuit according to the item (1), the information on the signal propagation time of each element and each wiring is transferred to the signal transition propagation of the signal line from the output terminal of the element to the input terminal of the element. The value of the time and the value of the sum of the value of the time when the signal transition propagates from the input terminal to the output terminal of the element to which the input terminal belongs, and the input terminal is selected as the path through which the signal transition propagates A method for detecting a delay fault in a logic circuit, comprising: means for referring to a value of a propagation time of a corresponding part in a case.

(7) In the method for detecting a delay fault in a logic circuit according to the third or fourth item, the first internal state, that is, the logical value held by each storage element related to the test or the external input terminal at the time of the test. And generating a first test sequence for the first test sequence. For the first test sequence, the third unit performs processing for all the storage elements to be tested and at the time of the test. Using the threshold value corresponding to the maximum value of the signal propagation time between the external input / output terminals, the second or third means determines the detectability of the hypothetical fault, and determines that the detection is impossible in the determination. The first means generates the second test sequence only for the
A delay fault detection method for a logic circuit, comprising: testing a test target logic circuit by combining the test sequence of (1) and the second test sequence.

(8) In the fault simulation or test sequence generation method used in the method for detecting a delay fault of a logic circuit according to any one of the first to seventh terms, this corresponds to an assumed delay fault delay time. One or more numerical values of the first parameter are input, and the detectability of a hypothetical fault is determined for each of the numerical values, and it is determined that the detectability of each of the first parameters for all the number of hypothetical faults is detectable. A fault simulation or test sequence generation method, comprising means for obtaining and displaying a ratio of the number of faults.

(9) In the fault simulation or test sequence generation method described in the paragraph (8), the numerical value of the first parameter corresponding to the assumed delay time of the delay fault is set to 1
One or more inputs, assuming a delay fault in the test target logic circuit, simulating the logical operation of the test target logic circuit with respect to the test sequence, and when the transition signal passing through the fault assumption part does not assume the delay due to the fault. , When the observation point is arrived before the observation time, and the condition for arriving at the observation point later than the observation time is satisfied when assuming a delay due to a failure corresponding to the numerical value of each of the first parameters in the part. Means for judging that the hypothetical fault is detectable, and obtaining and displaying a ratio of the number of faults judged to be detectable for each of the first parameters to all the number of hypothetical faults. Simulation or test sequence generation method.

[0150]

As described above, according to the present invention, a random number sequence is used, or a test sequence that activates a sufficiently small number of paths compared with the number of all existing paths is used.
A delay fault detection method for a logic circuit capable of detecting a slight delay of each logic element can be provided.Furthermore, a fault assumption point where a slight delay cannot be detected is identified,
It is possible to provide not only a means for generating a test sequence for the fault, but also a method for detecting a delay fault of a logic circuit, which enables management of test quality and improvement of required performance.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an outline of a processing operation of test sequence generation using one embodiment of the present invention.

FIG. 2 is a diagram illustrating a logical configuration of a test target circuit example used for describing the embodiment of the present invention.

FIG. 3 is a diagram showing an equivalent circuit that defines the operation of a flip-flop (FF) that is a storage element shown in FIG.

FIG. 4 is a diagram showing a truth table defining the operation of a basic element in the equivalent circuit shown in FIG. 3;

FIG. 5 is a diagram showing a truth table defining the operation of the address decoder shown in FIG. 2;

FIG. 6 is a diagram illustrating a structure of information when the circuit example shown in FIG. 2 is stored in a storage device.

FIG. 7 is a table showing a correspondence between an element number of a storage element and a scan address in FIG. 6;

8 is a diagram showing an example of a numerical value corresponding to a transition signal propagation time from each input terminal to an output terminal for each element function name shown in FIG. 6;

9 is a diagram showing an example of a numerical value corresponding to a transition signal propagation time for each wiring in the circuit example shown in FIG. 2;

10 is a diagram illustrating an example of a first internal state obtained when test sequence generation is performed on the circuit example illustrated in FIG. 2;

11 is a diagram illustrating a time chart of a test sequence derived from the first internal state shown in FIG.

FIG. 12 is a flowchart illustrating details of a process in step 108 in the flow shown in FIG. 1;

FIG. 13 is a diagram illustrating a relationship between a test time interval and a signal propagation time from a data output terminal of a transition signal generation FF to a data input terminal of a transition signal arrival FF.

FIG. 14 is a flowchart illustrating a processing operation of still another embodiment of the present invention for obtaining a logical value to be allocated to a storage element in step 105 in the flow shown in FIG. 1;

FIG. 15 shows steps 1404 to 1404 of the flow shown in FIG.
FIG. 406 illustrates an example of path information stored and ordered at 406.

FIG. 16 is a flowchart showing a process of step 1407 of the flow shown in FIG.
FIG. 9 is a diagram illustrating a means for obtaining a transition signal propagation condition using a D algorithm.

17 is a diagram illustrating an example of a first internal state obtained based on the inspection cube shown in FIG.

FIG. 18 is a flowchart illustrating a processing operation of still another embodiment of the present invention for obtaining a logical value to be allocated to a storage element in step 105 in the flow shown in FIG. 1;

FIG. 19 is a diagram illustrating an example of information obtained by the process of step 1803 in FIG. 18;

20 is a diagram illustrating a process of generating a check cube in the processing in steps 1805 to 1819 in FIG.

FIG. 21 is a diagram showing an example of a first internal state obtained by the processing shown in FIG. 18;

FIG. 22 is a flowchart illustrating a processing operation of still another embodiment of the present invention for obtaining a logical value to be allocated to a storage element in step 105 in the flow shown in FIG. 1;

FIG. 23 is a diagram illustrating an example of a first internal state obtained in the process of step 2217 in FIG. 22;

24 is a diagram illustrating a description example of signal delay time information for the circuit example shown in FIG. 2;

FIG. 25 is a diagram illustrating an example in which a propagation time value referred to for each input terminal when a route is selected is created from the information in FIG. 24;

FIG. 26 is a flowchart illustrating an outline of a processing operation of test sequence generation using another embodiment of the present invention.

FIG. 27 is a flowchart illustrating an outline of a processing operation of test sequence generation using still another embodiment of the present invention.

FIG. 28 is a flowchart illustrating an outline of a processing operation of test sequence generation using still another embodiment of the present invention.

[Explanation of symbols]

 201 to 212 input terminal 213 to 226 flip-flop (FF) 227 to 245 gate element 246 decoder 247 OR gate 248 to 252 output terminal 302 FF element

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Nobunobu Nakao 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratory, Hitachi Ltd. 2G032 AA01 AA07 AC03 AD06 5B046 AA08 BA09 JA04

Claims (5)

[Claims] 1. A first storage element included in a logic circuit to be tested, which receives connection information of a logic element of the logic circuit to be tested and wiring between the elements, and information of a signal propagation time of each element and each wiring. A first internal state is set for the group, a plurality of transition signals at test time intervals are applied from the test apparatus, and the first storage element group is changed to the second internal state,
Reading a value held by the storage element group of the above, generating a test sequence to be compared with an expected value, and detecting a fault in the circuit by using the test sequence. Assumes a delay fault in a logic circuit to be tested, sets a first parameter value to the degree of signal propagation delay of the assumed delay fault, and sets the first storage element group from a first internal state to a second A signal transition is caused at the output terminal by causing the transition to the internal state, and the signal transition is propagated to a propagation path in the circuit under test. Propagates to a subgroup of external output terminals, or the signal transition propagates from a subgroup of external input terminals to a third storage element or a subgroup of external output terminals that reaches the input terminal through the assumed fault site And a signal propagation time of the transition signal on the searched path is calculated, and a maximum value of the signal propagation time is determined based on a threshold value corresponding to the test time interval and the first value based on the threshold value. A logic circuit characterized in that one test sequence is selected from a plurality of possible test sequences so as to be able to detect a supposed fault so that the test value is between a value obtained by subtracting the parameter value of Delay fault detection method. 2. A first memory element included in a test target logic circuit, which receives connection information of a logic element of a test target logic circuit and wiring between elements and information of a signal propagation time of each element and each wiring. A first internal state is set for the group, a plurality of transition signals at test time intervals are applied from the test apparatus, and the first storage element group is changed to the second internal state,
Reading a value held by the storage element group of the above, generating a test sequence to be compared with an expected value, and detecting a fault in the circuit by using the test sequence. Assumes a delay fault in the test target logic circuit, sets a first parameter value representing a degree of signal propagation delay of the assumed delay fault, and resets the first storage element group from a first internal state to a first internal state. 2 to cause the signal transition to occur at the output terminal, propagate the signal transition to the propagation path in the circuit under test, and cause the signal transition to pass through the fault assumption site and to the second storage element. Or to a third storage element or a subgroup of external output terminals where the signal transition propagates to a subgroup of external output terminals, or wherein the signal transitions reach the input terminal from the subgroup of external input terminals through the assumed fault site. Searches for a route to transportable, calculates the signal propagation time on said searched route to the transition signal,
It is assumed that the test time interval is set so that the maximum value of the signal propagation time is between a threshold value corresponding to the test time interval and a value obtained by subtracting the first parameter value from the threshold value. A method for detecting a delay fault in a logic circuit, wherein the method is performed so that a fault can be detected. 3. The search for a path through which the transition signal propagates,
Propagation of a logical value in the circuit under test;
The propagation of a signal transition caused by the transition from the internal state to the second internal state and the propagation path thereof are recorded, and the signal transition is performed by searching for a path passing through the assumed failure point. 3. The method according to claim 1, wherein the delay fault is detected. 4. The method according to claim 1, wherein the setting of the first internal state in the first storage element group is performed by obtaining a logical value to be set corresponding to each item of the random number sequence. Or the delay fault detection method for a logic circuit according to 3. 5. A method for specifying connection information of a logic element of a logic circuit to be tested and wiring between the elements, and a set of propagation paths of signal transition from an output terminal of the storage element to be tested to an input terminal of the storage element. Information, a first internal state is set in a first storage element group included in the logic circuit to be tested, and a plurality of transition signals at test time intervals are applied from a test device to the first storage element. After changing the group to the second internal state, a value held in the first storage element group is read, a test sequence is generated to be compared with an expected value, and a fault of the circuit is detected using the test sequence. In the method for detecting a delay fault of a logic circuit, a first state is set in the first storage element group using design information of a logic element constituting the test target logic circuit and wiring between the elements, and a test time is set. Of multiple transition signals in the interval After the application, first means for reading a value held by the storage element in a second state and generating a test sequence for comparison with an expected value, and by shifting from the first internal state to a second internal state The signal transition propagates through the circuit under test from the second subgroup in the first storage element group or the external input terminal at the time of testing, which causes a signal transition at the output terminal, and the propagation reaches the input terminal. It is determined whether there is a path to a third group of storage elements or an external output terminal at the time of testing, and if the path exists, it is determined whether the path is included in the signal transition propagation path set. And when it is recognized that the fault is involved in the determination, a fault in the logic circuit is determined using the test sequence generated by the test sequence generating unit including: a unit that determines that a fault related to the delay of the path can be detected. Detect Delay fault detection method of the logic circuit, characterized in that.