JP2004241563A - Semiconductor device for static electricity protection and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new semiconductor device for static electricity protection and a semiconductor device containing the semiconductor device for static electricity protection. <P>SOLUTION: The semiconductor device 100 for static electricity protection contains a second-conductivity first well 51 and a first-conductivity second well 14 formed in a first-conductivity semiconductor substrate 10. The first well 51 contains a first-conductivity third well 24. The third well 24 contains a first-conductivity first impurity diffusing layer 22. The second well 14 contains a first-conductivity second impurity diffusing layer 26. The third well 24 is formed so that a depletion layer 24a may be formed under the well 24, and the well 24 may be connected to the semiconductor substrate 10 through the depletion layer 24a when a positive voltage of a prescribed value is impressed upon the first impurity diffusing layer 22. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a novel semiconductor device for electrostatic protection and a semiconductor device including the semiconductor device for electrostatic protection.
[0002]
[Background Art]
In a semiconductor device, a surge such as static electricity may be applied to a signal input terminal, a signal output terminal, or a signal input / output terminal, and an internal circuit may be electrostatically damaged. In order to prevent such an electrostatic breakdown, an electrostatic protection circuit is generally connected to the above-described terminal.
[0003]
[Problems to be solved by the invention]
An object of the present invention is to provide a novel semiconductor device for electrostatic protection and a semiconductor device including the semiconductor device for electrostatic protection.
[0004]
[Means for Solving the Problems]
1. The semiconductor device for electrostatic protection of the present invention
A first well of a second conductivity type and a second well of a first conductivity type, formed on a semiconductor substrate of the first conductivity type;
The first well includes a third well of a first conductivity type,
The third well includes a first impurity diffusion layer of a first conductivity type,
The second well includes a second impurity diffusion layer of a first conductivity type,
When a predetermined positive voltage is applied to the first impurity diffusion layer, a depletion layer is formed below the third well, and the third well is connected to the semiconductor substrate via the depletion layer. Thus, the third well is formed.
[0005]
According to the semiconductor device for electrostatic protection of the present invention, when a predetermined positive voltage is applied to the first impurity diffusion layer, charges (holes or electrons) are transferred from the third well to the first impurity diffusion layer. As a result, a depletion layer is formed below the third well. The third well and the semiconductor substrate are connected via the depletion layer. As a result, a charge transfer path from the first impurity diffusion layer to the second impurity diffusion layer through the third well, the depletion layer, the semiconductor substrate, and the second well is formed. Thus, the positive voltage pulse applied to the first impurity diffusion layer can be discharged to the second impurity diffusion layer via the charge transfer path. Thus, the protected circuit can be reliably protected from surges such as static electricity.
[0006]
The semiconductor device for electrostatic protection according to the present invention can have the following aspects (1) to (4).
[0007]
(1) The first impurity diffusion layer can be connected to a predetermined signal input terminal, signal output terminal, or signal input / output terminal.
[0008]
(2) The second impurity diffusion layer can be connected to a reference power supply voltage. In this case, the reference power supply voltage may be ground.
[0009]
(3) The first impurity diffusion layer and the second impurity diffusion layer can be electrically separated by an element isolation region provided in a semiconductor substrate. According to this configuration, the charge transfer path can be reliably formed.
[0010]
(4) The second well can be formed near an end of the first well, and the third well can be formed near the second well. According to this configuration, since the charge transfer path can be made shorter, the positive voltage pulse applied to the first impurity diffusion layer can be quickly discharged to the second impurity diffusion layer. Can be.
[0011]
2. The semiconductor device of the present invention includes the semiconductor device for electrostatic protection described above,
The semiconductor substrate further includes an insulated gate high voltage transistor and a low voltage transistor.
[0012]
The semiconductor device of the present invention can have the following modes (A) to (C).
[0013]
(A) The high breakdown voltage transistor can be formed in the first well.
[0014]
In this case, the high breakdown voltage transistor can be formed in a first well of the first conductivity type formed in the first well.
[0015]
(B) The first impurity diffusion layer and the source / drain layers of the high breakdown voltage transistor can be formed in the same step.
[0016]
(C) The second impurity diffusion layer and the source / drain layers of the high breakdown voltage transistor can be formed in the same step.
[0017]
In the above aspects (A) to (C), the electrostatic protection semiconductor device of the present invention is formed by utilizing the manufacturing process of the high breakdown voltage transistor or the low breakdown voltage transistor. Since it is not necessary to separately provide a manufacturing process for performing the manufacturing, the manufacturing process can be simplified and the production cost can be reduced. As a result, a less expensive semiconductor device can be obtained.
[0018]
Further, when the electrostatic protection semiconductor device of the present invention is formed by using the manufacturing process of the high breakdown voltage transistor, each layer configuring the electrostatic protection semiconductor device is the same as each layer configuring the high breakdown voltage transistor. With this structure, it has excellent withstand voltage. Therefore, a large voltage pulse can be more reliably discharged.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0020]
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment, and FIG. 2 is a cross-sectional view for explaining the operation of the electrostatic protection semiconductor device 100 shown in FIG.
[0021]
In this embodiment, a case is described in which an insulated gate high voltage transistor and a low voltage transistor having different source-drain withstand voltages are formed on the same substrate as the semiconductor substrate 10 on which the electrostatic protection semiconductor device 100 is formed. (See FIG. 2). The high breakdown voltage transistor 200 shown in FIG. 2 is a part of the semiconductor device shown in FIG. In this embodiment, an example in which the first conductivity type is P-type and the second conductivity type is N-type will be described.
[0022]
1. Device Structure The semiconductor device of the present embodiment includes a semiconductor device 100 for electrostatic protection, high breakdown voltage transistors 200 and 400, and low breakdown voltage transistors 300 and 500 (see FIGS. 1 to 3). These are all formed on the semiconductor substrate 10.
[0023]
The static electricity protection semiconductor device 100 has a discharge element constituting a static electricity protection circuit. As shown in FIG. 1, in the semiconductor device 100 for electrostatic protection, an N-type first well 51 and a P-type second well 14 are formed on a semiconductor substrate 10 made of a P-type silicon substrate. In the semiconductor substrate 10, for example, an element isolation region 12 having a predetermined pattern is formed by a selective oxidation method or an STI (Shallow Trench Isolation) method. In the present embodiment, a case where the element isolation region 12 is formed of a semi-recessed LOCOS layer is shown.
[0024]
In the first well 51, a P-type third well 24 is formed. In this third well 24, a P-type impurity diffusion layer (first impurity diffusion layer) 22 can be formed. Specifically, the P-type impurity diffusion layer 22 is formed above the third well 24, and the P-type impurity diffusion layer 22 is formed with a higher impurity concentration than the third well 24.
[0025]
When a positive voltage of a predetermined value is applied to the signal input terminal IN, charges (holes in the present embodiment) move from the third well 24 to the P-type impurity diffusion layer 22, and as a result, Is formed with a depletion layer 24a (see FIG. 2). The third well 24 is formed such that the depletion layer 24a can be connected to the semiconductor substrate 10 when a predetermined positive voltage is applied to the signal input terminal IN. Specifically, by appropriately selecting the impurity concentration of the third well 24, the cross-sectional area and the depth of the third well 24, the type of the impurity to be introduced, and the like, a predetermined positive voltage is applied to the signal input terminal IN. When the voltage is applied, the semiconductor substrate 10 and the third well 24 are connected via the depletion layer 24a.
[0026]
The third well 24 can be formed by the same process as the well 11. The third well 24 is formed in the first well 51 similarly to the well 11, while a high breakdown voltage transistor 200 is formed in the well 11. That is, by forming the well 11 in the first well 51, a triple well is formed.
[0027]
In the second well 14, a P-type impurity diffusion layer (second impurity diffusion layer) 26 can be formed. This P-type impurity diffusion layer 26 is formed so as to have an impurity concentration higher than that of the second well 14.
[0028]
Further, as shown in FIG. 1, the third well 24 is formed near the end of the first well 51, and the second well 14 is also formed near the end of the first well 51. Therefore, the third well 24 is formed near the second well 14.
[0029]
The P-type impurity diffusion layers 22 and 26 are electrically separated from each other via the element isolation region 12. In the present embodiment, the P-type impurity diffusion layers 22 and 26 can be formed by the same process as the source / drain layers 17 and 19 constituting the high breakdown voltage transistor 300 described later. Alternatively, the P-type impurity diffusion layers 22 and 26 can be formed in the same step as the impurity layers of another transistor shown in FIG. 1, for example.
[0030]
The P-type impurity diffusion layer 22 is connected to an input signal terminal IN (signal input terminal), and the P-type impurity diffusion layer 26 is connected to a reference power supply voltage. In this embodiment, a case where the reference power supply voltage is ground ( _VSS ) is shown. A protected circuit 900 is connected to the input signal terminal IN in parallel with the semiconductor device 100 for electrostatic protection. Here, the circuit to be protected refers to a circuit that is protected from static electricity by the static electricity protection semiconductor device 100 of the present embodiment. The type of the protected circuit 900 is not particularly limited. For example, the high voltage transistor or the low voltage transistor shown in FIG. 1 may be the protected circuit 900.
[0031]
As described above, the high voltage transistors 200 and 400 and the low voltage transistors 300 and 500 are formed on the semiconductor substrate 10 together with the electrostatic protection semiconductor device 100 (see FIG. 1). In FIG. 1, ESD refers to a region where the electrostatic protection semiconductor device 100 is formed, HV refers to a region where the high breakdown voltage transistors 200 and 400 are formed, and LV refers to a region where the low breakdown voltage transistors 300 and 500 are formed. Refers to the formed area.
[0032]
The high withstand voltage transistors 200 and 400 are used when driven by a power supply voltage of 10 V or more, such as an LSI for driving a liquid crystal panel and an LSI for driving a CCD, and usually have a withstand voltage of 20 V or more. Further, the low breakdown voltage transistors 300 and 500 are used, for example, in an internal control logic unit that requires miniaturization and high speed.
[0033]
Specifically, as shown in FIG. 1, the N-channel high-voltage transistor 200 is formed in the fourth well 11 formed in the first well 51, and the P-channel high-voltage transistor 400 is It is formed in the first well 51. Further, the N-channel type low breakdown voltage transistor 300 is formed in the P-type well 61, and the P-channel type low breakdown voltage transistor 500 is formed in the N-type well 41. Hereinafter, description will be made with reference to the high breakdown voltage transistor 200 and the low breakdown voltage transistor 300 shown in FIG. The transistors 400 and 500 have substantially the same configuration as the transistors 200 and 300, respectively, except that they have the opposite conductivity types, and thus detailed description is omitted.
[0034]
As shown in FIG. 1, the high breakdown voltage transistor 200 includes a gate insulating layer 14H and a gate conductive layer 16H. The gate conductive layer 16H is formed on the gate insulating layer 14H. Further, a silicide layer 20SH can be formed on the gate conductive layer 16H.
[0035]
High breakdown voltage transistor 200 further includes n-type source / drain regions 17 and 19. The source / drain regions 17, 19 are formed so as to sandwich the gate conductive layer 16H. The source / drain regions 17 and 19 are formed in offset regions 37 and 39, respectively. Further, silicide layers 17S and 19S can be formed on the source / drain regions 17 and 19, respectively.
[0036]
As shown in FIG. 1, low-breakdown-voltage transistor 300 includes a gate insulating layer 28L and a gate conductive layer 16L. The gate conductive layer 16L is formed on the gate insulating layer 28L. Further, a silicide layer 20SL can be formed on the gate conductive layer 16L.
[0037]
Low breakdown voltage transistor 300 further includes n-type source / drain regions 47 and 49. The source / drain regions 47 and 49 are formed so as to sandwich the gate conductive layer 16L. The source / drain regions 47 and 49 are formed in the offset regions 27 and 29, respectively. Further, silicide layers 47S and 49S can be formed on the source / drain regions 27 and 29, respectively.
[0038]
The gate insulating layers 14H and 14L are made of, for example, a silicon oxide layer, and the gate conductive layers 20H and 20L are made of, for example, a doped polysilicon layer.
[0039]
2. Operation of Device Next, an operation of the semiconductor device 100 for electrostatic protection according to the present embodiment will be described with reference to FIG. FIG. 2 is a diagram schematically illustrating the operation of the electrostatic protection semiconductor device 100 shown in FIG. In FIG. 2, the direction of the arrow indicates the direction in which the current flows.
[0040]
In the electrostatic protection semiconductor device 100, it is assumed that a positive voltage (positive voltage pulse) of a predetermined value is applied to the signal input terminal IN. That is, in this case, when a positive voltage is applied to the P-type impurity diffusion layer 22 connected to the signal input terminal IN, holes move from the third well 24 to the P-type impurity diffusion layer 22. A depletion layer 24a is formed below the third well 24. When the depletion layer 24a reaches the P-type semiconductor substrate 10, the P-type third well 24, the depletion layer 24a, the P-type semiconductor substrate 10, and the P-type second well 14 from the P-type impurity diffusion layer 22. , A charge transfer path leading to the P-type impurity diffusion layer 26 is formed. As a result, the positive voltage pulse applied to the signal input terminal IN is discharged to the reference power supply voltage (ground potential) via the charge transfer path.
[0041]
3. According to the semiconductor device for electrostatic protection and the semiconductor device according to the present embodiment, the following effects are obtained.
[0042]
(1) First, when a positive voltage of a predetermined value is applied to the signal input terminal IN, the third well 24 and the semiconductor substrate 10 are connected via the depletion layer 24a formed below the third well 24. A third well 24 is formed for connection. That is, according to this configuration, when a positive-polarity voltage pulse is applied to the signal input terminal IN, a positive voltage is applied to the P-type impurity diffusion layer 22 connected to the signal input terminal IN. Holes move from the three wells 24 to the P-type impurity diffusion layer 22. As a result, a depletion layer 24a reaching the semiconductor substrate 10 is formed below the third well 24. Thereby, a charge transfer path from the P-type impurity diffusion layer 22 to the P-type impurity diffusion layer 26 via the P-type third well 24, the depletion layer 24a, the P-type semiconductor substrate 10, and the P-type second well 14 Is formed. Thus, the positive voltage pulse applied to the signal input terminal IN can be discharged to the reference power supply voltage (ground potential) via the charge transfer path. Thus, the protected circuit can be reliably protected from surges such as static electricity.
[0043]
Further, as shown in FIG. 1, the third well 24 is formed near the end of the first well 51, and the second well 14 is also formed near the end of the first well 51. According to this configuration, since the second well 14 is formed near the third well 24, the charge transfer path can be further shortened. Thus, the positive voltage pulse applied to the P-type impurity diffusion layer 22 can be quickly discharged to the P-type impurity diffusion layer 26 via the charge transfer path.
[0044]
(2) Secondly, in the semiconductor device of the present embodiment, the first well 51 and the second and third wells 14 and 24 formed in the first well 51 constitute a triple well. (See FIG. 1). In general, the wells forming the triple well are formed deeper than the wells forming the twin well. Therefore, the third well 24 forming the triple well is formed deeper than the well formed in a general twin well. As described above, since the third well 24 forming the electrostatic protection semiconductor device 100 is formed at a sufficient depth, a large voltage pulse can be more reliably discharged without requiring a large cross-sectional area. Can be.
[0045]
(3) Third, the electrostatic protection semiconductor device 100 can be formed by using a manufacturing process of a high breakdown voltage transistor (for example, the high breakdown voltage transistor 300). In this case, there is no need to separately provide a manufacturing process for forming the electrostatic protection semiconductor device 100, so that the manufacturing process can be simplified and the production cost can be reduced. As a result, a less expensive semiconductor device can be obtained.
[0046]
Further, since the electrostatic protection semiconductor device 100 is formed by using the manufacturing process of the high breakdown voltage transistor, each layer constituting the electrostatic protection semiconductor device 100 has the same structure as each layer constituting the high breakdown voltage transistor. It has excellent pressure resistance. Therefore, a large voltage pulse can be more reliably discharged.
[0047]
Note that the same operation and effect can be obtained when the electrostatic protection semiconductor device 100 is formed by using another transistor manufacturing process shown in FIG.
[0048]
The present invention is not limited to the above-described embodiment, and can take various aspects within the scope of the present invention.
[0049]
For example, even when the electrostatic protection semiconductor device according to the present embodiment is connected to a signal output terminal or a signal input / output terminal, the same effect can be obtained. Similar effects can be obtained even if the conductivity types of the semiconductor substrate, the impurity diffusion layer, and the wells of the semiconductor device for electrostatic protection according to the present embodiment are reversed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment to which the present invention is applied.
FIG. 2 is a cross-sectional view schematically showing an operation of the static electricity protection semiconductor device shown in FIG.
[Explanation of symbols]
Reference Signs List 10 semiconductor substrate, 11 fourth well, 12 element isolation region, 14 second well, 16H, 16L gate conductive layer, 17, 19, 47, 49, 57, 59, 67, 69 source / drain region, 17S, 19S, 20SH, 20SL, 22S, 26S, 26S, 47S, 49S, 57S, 59S, 67S, 69S silicide layer, 22 first impurity diffusion layer, 24 third well, 24a depletion layer, 26 second impurity diffusion layer, 27, 29 , 37, 39, 77, 79, 87, 89 offset region, 41, 61 well, 51 first well, 100 electrostatic protection semiconductor device, 200, 400 high voltage transistor, 300, 500 low voltage transistor, 900 protected circuit

Claims (12)

A first well of a second conductivity type and a second well of a first conductivity type, formed on a semiconductor substrate of the first conductivity type;
The first well includes a third well of a first conductivity type,
The third well includes a first impurity diffusion layer of a first conductivity type,
The second well includes a second impurity diffusion layer of a first conductivity type,
When a predetermined positive voltage is applied to the first impurity diffusion layer, a depletion layer is formed below the third well, and the third well is connected to the semiconductor substrate via the depletion layer. As described above, the semiconductor device for electrostatic protection in which the third well is formed. In claim 1,
The static electricity protection semiconductor device, wherein the first impurity diffusion layer is connected to a predetermined signal input terminal, signal output terminal, or signal input / output terminal. In claim 1 or 2,
The static electricity protection semiconductor device, wherein the second impurity diffusion layer is connected to a reference power supply voltage. In claim 3,
An electrostatic protection semiconductor device, wherein the reference power supply voltage is ground. In any one of claims 1 to 4,
The semiconductor device for electrostatic protection, wherein the first impurity diffusion layer and the second impurity diffusion layer are electrically separated by an element isolation region provided in a semiconductor substrate. In any one of claims 1 to 5,
The second well is formed near an end of the first well,
The third well is an electrostatic protection semiconductor device formed near the second well. Including the semiconductor device for electrostatic protection according to any one of claims 1 to 6,
A semiconductor device further comprising an insulated gate high voltage transistor and a low voltage transistor on the semiconductor substrate. In claim 7,
The semiconductor device, wherein the high breakdown voltage transistor is formed in the first well. In claim 8,
The semiconductor device, wherein the high breakdown voltage transistor is formed in a first well of a first conductivity type formed in the first well. In claim 9,
The semiconductor device, wherein the third well and the fourth well are formed in the same step. In any one of claims 7 to 10,
The semiconductor device, wherein the first impurity diffusion layer and a source / drain layer of the high breakdown voltage transistor are formed in the same step. In any one of claims 7 to 11,
The semiconductor device, wherein the second impurity diffusion layer and a source / drain layer of the high breakdown voltage transistor are formed in the same step.

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