JP2001291827A - Semiconductor device for protection against static electricity - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for protecting against static electricity which enables higher speed operation. SOLUTION: This semiconductor device contains a P-type well 11 containing a P-type impurity diffusion layer 60 and an N-type impurity diffusion layer 20 which is isolated electrically from the layer 60, and an N-type well 13 which is formed in the P-type well 11 and contains an N-type impurity diffusion layer 30. A first bipolar transistor 210 is constituted of the N-type impurity diffusion layer 30, the N-type well 13 and the P-type well 11. A second bipolar transistor 220 is constituted of the N-type impurity diffusion layer 20, the P-type well 11 and the N-type well 13. A Zener diode 230 is constituted of an N-type impurity diffusion layer 40 continuous from the P-type well 11 to the N-type well 13 and a P-type impurity diffusion layer 50 joined to the N-type diffusion layer 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for electrostatic protection, and more particularly, to a semiconductor device for electrostatic protection excellent in electrostatic breakdown resistance.

[0002]

2. Description of the Related Art Semiconductor devices, for example, complementary MOS (CMO)
S) In a semiconductor device, a surge such as static electricity may be applied to a signal input terminal, a signal output terminal, or a signal input / output terminal, and an internal circuit may be electrostatically damaged. In order to prevent such electrostatic breakdown, a protection circuit is generally connected to the above-mentioned terminals. For example, a protection circuit for protecting a signal input terminal is disclosed in JP-A-63-36556. FIG. 8 shows the configuration of the protection circuit disclosed in this publication.

In FIG. 8, a protection circuit 900 and an internal circuit 800 are both connected to a signal input terminal IN in parallel. The internal circuit 800 converts the P-channel transistor 133 and the N-channel transistor
An OS inverter is configured, and a common gate of the inverter is connected to a signal input terminal IN, and a common drain is connected to a next-stage circuit (not shown).

The protection circuit 900 includes a P-type semiconductor region 11
7, a PNP-type bipolar transistor composed of an N-type well region 114 and a P-type epitaxial layer 112, and an N-type well region 114 and a P-type epitaxial layer 1.
12 and N-type semiconductor region 116
Includes N-type bipolar transistors. This protection circuit 90
When a positive high voltage pulse is applied to the signal input terminal IN at 0, latch-up of the thyristor composed of the PNP transistor and the NPN transistor starts. By the activation of the latch-up, the P-type semiconductor region 117, N
Through the type well region 114, the P-type epitaxial layer 112, and the N-type semiconductor region 116, discharge is performed to a reference power supply voltage (earth). The protection circuit 900 protects the internal circuit 800 by discharging through the above-described path.

On the other hand, in order to more effectively eliminate the surge, it is required to operate the protection circuit at a higher speed. In a circuit that has a thyristor structure and removes a surge by latch-up of the thyristor as in the above-described protection circuit 900, a high-voltage pulse is applied to the signal input terminal IN in order to realize higher-speed operation. It is required to reduce the time from when the thyristor starts latch-up.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an electrostatic protection semiconductor device which can operate at higher speed.

[0007]

According to the present invention, there is provided a semiconductor device for electrostatic protection according to the present invention, comprising: a first impurity diffusion layer of a first conductivity type;
A first region of a first conductivity type including a second impurity diffusion layer of a second conductivity type electrically separated from the impurity diffusion layer;
A second conductivity type second region formed in a region, having a well structure and including a first conductivity type third impurity diffusion layer, the third impurity diffusion layer as an emitter region, and the second region as A first bipolar transistor having a base region and the first region serving as a collector region; and a second bipolar transistor having the second impurity diffusion layer serving as an emitter region, the first region serving as a base region, and the second region serving as a collector region. A bipolar transistor and a fourth conductive type fourth transistor formed in the first region.
An impurity diffusion layer, and a zener diode that is connected to the fourth impurity diffusion layer and is formed of a first conductivity type fifth impurity diffusion layer continuous with the first region.

In the above-described semiconductor device for electrostatic protection, the first impurity diffusion layer and the second impurity diffusion layer are connected to a reference power supply voltage, and the third impurity diffusion layer and the fourth impurity diffusion layer are connected to each other. , Predetermined signal input terminal,
It can be connected to a signal output terminal or a signal input / output terminal.

According to the semiconductor device for electrostatic protection connected as described above, the following effects are obtained.

When a positive high-voltage pulse is applied to the signal input terminal, the signal output terminal, or the signal input / output terminal, first, the Zener is supplied by a current flowing from the terminal to the fourth impurity diffusion layer. The breakdown of the diode makes it possible to quickly start the second bipolar transistor. As a result, the time from the application of the positive high-voltage pulse to the start of latch-up by the thyristor can be reduced, and higher-speed operation can be performed.

The following embodiments can be given as examples of the semiconductor device for electrostatic protection according to the present invention.

(A) The second and third impurity diffusion layers are formed inside the first and fourth impurity diffusion layers, respectively, with one boundary surface between the first region and the second region as a center. The fourth impurity diffusion layer may be formed on the side opposite to the side where the second impurity diffusion layer is formed with the third impurity diffusion layer as a center.

(B) The fourth impurity diffusion layer is formed in the first impurity diffusion layer.
It can be formed continuously from the region to the second region and can be formed so as to be in contact with the second region. According to this configuration, it is possible to secure a current passage path when a negative high-voltage pulse is applied to the terminal.
Details will be described in the section of the embodiment of the present invention.

(C) The fifth impurity insulating layer is formed of the fourth impurity insulating layer.
It can be formed so as to be joined to a part of the bottom surface of the impurity diffusion layer.

(D) The fifth impurity insulating layer can be formed such that its impurity concentration is lower than the impurity concentrations of the first and third impurity insulating layers. According to this configuration, it is possible to suppress the leak current as compared with the junction between the impurity diffusion layers having a high impurity concentration. Also, since the breakdown voltage can be set freely as compared with the well-to-well junction, a quicker operation is possible.

(E) The first region may have a well structure.

(F) At least one of the impurity diffusion layers is formed on a substrate surface, and a silicide layer can be formed on the impurity diffusion layer formed on the substrate surface.

(G) The reference power supply voltage can be grounded.

(H) It can be connected to an internal circuit including a CMOS transistor and used as a protection circuit.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device for electrostatic protection according to the present invention will be described.

FIG. 1 is a sectional view schematically showing an electrostatic protection semiconductor device according to the present embodiment. FIG. 2 is an example of an output circuit provided with the electrostatic protection semiconductor device shown in FIG. It is an equivalent circuit showing In the present embodiment,
An example in which the semiconductor device for electrostatic protection according to the present invention is applied to an internal circuit including a CMOS semiconductor device will be described.
In the present embodiment, the first conductivity type is P-type, and the second conductivity type is P-type.
An example in which the conductivity type is N-type will be described.

(Structure of Device) The semiconductor device for electrostatic protection according to the present embodiment has a discharge element constituting an electrostatic protection circuit 200.

In this electrostatic protection semiconductor device, as shown in FIG. 1, a P-type silicon substrate 10 has a P-type well (first region of first conductivity type) 11 and an N-type well (second region of second conductivity type). A second region 13 is formed. P-type well 11
The N-type well 13 is provided with, for example, a selective oxidation method or STI.
An element isolation region 12 having a predetermined pattern is formed by a (Shallow Trench Isolation) method, and P-type and N-type impurity diffusion layers described later are formed in regions other than the element isolation region 12.

In the P-type well 11, a P-type impurity diffusion layer (first impurity diffusion layer) 60 and an N-type impurity diffusion layer (second impurity diffusion layer) 20 are formed.

In the N-type well 13, a P-type impurity diffusion layer (third impurity diffusion layer) 30 is formed.

On the side opposite to the side on which the N-type impurity diffusion layer 20 is formed with the P-type impurity diffusion layer 30 as the center, an N-type impurity diffusion layer (continued from the P-type well 11 to the N-type well 13) A fourth impurity diffusion layer) 40 is formed.

Further, a P-type impurity diffusion layer (fifth impurity diffusion layer) 50 is formed so as to be joined to a part of the bottom surface of the N-type impurity diffusion layer 40. The P-type impurity diffusion layer 50
It is formed at a position deeper than N-type impurity diffusion layer 40. Further, the N-type impurity diffusion layer 40 and the P-type impurity diffusion layer 50 are formed by a Zener voltage (junction withstand voltage) of a Zener diode (DA) 230 composed of both.
Is set to a predetermined value. For example, the impurity concentrations of the N-type impurity diffusion layer 40 and the P-type impurity diffusion layer 50 are each set to 1 × 10 ¹⁸ cm ^−3.
The zener voltage can be set to about 6 to 6.5 V. Further, the impurity concentration of the P-type impurity diffusion layer 50 is
It is desirable that the impurity diffusion layers 30 and 60 are formed so as to have a lower impurity concentration. According to this configuration, compared to the junction between impurity diffusion layers having a high impurity concentration,
Leakage current can be suppressed. Also, since the breakdown voltage can be set freely as compared with the well-to-well junction, a quicker operation is possible.

The N-type impurity diffusion layer 20 and the P-type impurity diffusion layer 30 are formed around the one boundary surface between the P-type well 11 and the N-type well 13 respectively.
And N-type impurity diffusion layer 40.

These impurity diffusion layers (P-type impurity diffusion layers 30 and 60 and N-type impurity diffusion layers 20 and 40) are electrically isolated from each other via an element isolation region 12.
A silicide layer 14 is formed on each of the surfaces.

Further, the first bipolar transistor (BP1) 210 and the second bipolar transistor (BP) are formed by the aforementioned P-type and N-type impurity diffusion layers and wells.
2) 220, and Zener diode (DA) 230
Is configured.

That is, as shown in FIG. 1, a P-type impurity diffusion layer 30 is used as an emitter region, an N-type well 13 is used as a base region, and a P-type well 11 is used as a collector region.
NP-type first bipolar transistor (BP1) 210
Are parasitically configured.

An NPN-type second bipolar transistor (BP2) 220 is formed in a parasitic manner using the N-type impurity diffusion layer 20 as an emitter region, the P-type well 11 as a base region, and the N-type well 13 as a collector region. Have been.

Further, a Zener diode (DA) 230 is formed by a PN junction between the N-type impurity diffusion layer 40 and the P-type impurity diffusion layer 50.

Further, the P-type impurity diffusion layer 60 and the N-type impurity diffusion layer 20 are connected to ground (reference power supply voltage), and the P-type impurity diffusion layer 30 and the N-type impurity diffusion layer 40 are connected.
Are connected to an output pad (signal output terminal) 300. In this embodiment, the case where the reference power supply voltage is the ground ( _VSS ) is shown, but the reference power supply voltage may be the high potential power supply (V _DD ).

The semiconductor device for electrostatic protection of the present invention can be formed by a known semiconductor device forming process.
For example, after doping an impurity into the silicon substrate 10 to form a P-type well 11 and an N-type well 13, an element isolation region 12 is formed, and then the P-type impurity diffusion layers 30, 60 and N-type impurity diffusion layers 20 and 4
0 is formed. Further, the N-type impurity diffusion layer 40
P-type impurity diffusion layer 50 is formed so as to be joined to a part of the bottom surface of P. The impurity concentration and the diffusion depth of the N-type impurity diffusion layer 40 and the P-type impurity diffusion layer 50 are set so that a Zener diode (DA) 230 can be formed. N-type impurity diffusion layer 40 and P-type impurity diffusion layer 50
Is not limited. Subsequently, a semiconductor device for electrostatic protection of the present invention is obtained by forming a silicide layer on the impurity diffusion layers 20, 30, 40, and 60 except for the P-type impurity diffusion layer 50. These steps can employ the same steps as those for forming a semiconductor device of an internal circuit, for example, a CMOS semiconductor device.

(Example of Electrostatic Protection Circuit) Next, an example of an output circuit having the electrostatic protection circuit of the present invention will be described with reference to FIGS.

This output circuit includes a first bipolar transistor (BP1) 210, a second bipolar transistor (BP2) 220, and a Zener diode (DA).
An electrostatic protection circuit 200 including 230 is provided. The electrostatic protection circuit 200 shown in FIG. 2 is an equivalent circuit showing the semiconductor device for electrostatic protection shown in FIG. Static electricity protection circuit 200
As shown in FIG. 2, the output line 310 from the output pad 300 and the ground line (first reference power supply line) 50
0, an N-channel type M as an output transistor
It is connected in parallel with the OS transistor 100. Further, a P-channel MOS transistor 110 is connected between the output line 310 and the high-potential power supply line (second reference power supply line) 400.

The first bipolar transistor (BP1) 210 constituting the electrostatic protection circuit 200 has an emitter connected to the output line 310, a collector connected to the base of the second bipolar transistor (BP2) 220, and a base connected to the second bipolar transistor (BP2) 220. Bipolar transistor (BP2) 2
Connected to 20 collectors. The second bipolar transistor (BP2) 220 has an emitter connected to the ground line 500, a collector connected to the base of the first bipolar transistor (BP1) 210,
The base is the first bipolar transistor (BP1) 210
Connected to the collector. Further, the output line 31
A Zener diode (DA) 230 is connected between 0 and the ground line 500. The base of the first bipolar transistor (BP1) 210 and the collector of the second bipolar transistor (BP2) 220 are connected to a Zener diode (DA) 230.

(Operation of Device) Next, the operation of the electrostatic protection circuit 200 of the present invention will be described with reference to FIGS. 3 to 6 are diagrams schematically showing the operation of the output circuit shown in FIG. 3 to 6, the direction of the arrow indicates the direction in which the current flows.

It is assumed that a positive high voltage pulse is applied to the output pad 300 in the electrostatic protection circuit 200.
The value of the applied high-voltage pulse is
Is higher than the Zener voltage Vt, a current flows from the output pad 300 to the N-type impurity diffusion layer 40,
A Zener diode (DA) 230 composed of the N-type impurity diffusion layer 40 and the P-type impurity diffusion layer 50 undergoes Zener breakdown. Due to the Zener breakdown, a current flows from the Zener diode (DA) 230 to the P-type impurity diffusion layer 60 via the P-type well 11 (see FIG. 3).

At the same time, a current flows from the N-type impurity diffusion layer 40 to the N-type impurity diffusion layer 20 via the N-type well 13 and the P-type well 11, so that the N-type well 1
3, a second bipolar transistor (BP2) 22 composed of a P-type well 11 and an N-type impurity diffusion layer 20
0 is activated (see FIG. 4).

Further, when the discharge from P-type impurity diffusion layer 30 to N-type well 13 is started, a first bipolar formed of P-type impurity diffusion layer 30, N-type well 13 and P-type well 11 is formed. Transistor (BP1) 2
10 starts (see FIG. 5). As described above, the thyristor including the first and second bipolar transistors 210 and 220 is activated, and the trigger current It having a predetermined value or more flows through the electrostatic protection circuit 200 (see FIG. 6). When the voltage of the output line 310 is higher than the holding voltage Vh peculiar to this circuit, the latch-up of the thyristor composed of the first and second bipolar transistors 210 and 220 continues to be held. Then, when the voltage of the output line 310 falls to the holding voltage or less, the latch-up is not maintained and the normal state is restored.

Here, the Zener voltage Vt can be freely determined by changing the impurity concentration of the P-type impurity diffusion layer 50. Also, the holding voltage Vh
Of the first and second bipolar transistors 21
It can be freely determined by setting the width (base length) of the base region of 0,220.

In the electrostatic protection circuit 200, when a high-voltage pulse of negative polarity is applied to the output pad 300, a parasitic diode (DB) formed by a junction with the N-type well 13 and the P-type well 11 is formed. ) 240
, A current flows from the ground line 500 to the output pad 300, the high voltage pulse applied to the output pad 300 is released, and the voltage of the output pad 300 decreases. That is, a current flows from ground line 500 to P-type impurity diffusion layer 60, and is further discharged from P-type impurity diffusion layer 60 to output pad 300 via diode (DB) 240 and N-type impurity diffusion layer 40.

According to the semiconductor device for electrostatic protection according to the present embodiment, the following functions and effects are obtained.

(1) In the static electricity protection circuit 200,
A thyristor is composed of the first bipolar transistor (BP1) 210 and the second bipolar transistor (BP2) 220, and a Zener diode (DA) 230 is formed by a PN junction between the N-type impurity diffusion layer 40 and the P-type impurity diffusion layer 50. It is configured. According to this configuration, when a positive high-voltage pulse is applied to the output pad 300, first, the Zener diode (D) is supplied by a current flowing from the output pad 300 to the N-type impurity diffusion layer 40.
A) Breakdown of 230 allows second bipolar transistor (BP2) 220 to be quickly activated. As described above, the time from when a high-voltage pulse is applied to the output pad 300 to when the thyristor starts latch-up can be reduced, and higher-speed operation can be performed.

(2) The P-type impurity diffusion layer 50 is formed continuously with the N-type well 13 and is in contact with the N-type well 13. As a result, it is possible to secure a current passage path when a negative high voltage pulse is applied to the output pad 300. That is, according to the above configuration, the ground line 5
00, the P-type impurity diffusion layer 60 and the P-type well 1
The current flowing to the N-type well 13 via the parasitic diode (DB) 240 formed by the junction between the N-type well 1 and the N-type well 13 is discharged to the output pad 300 via the N-type impurity diffusion layer 40. be able to. As described above, discharge to the N-channel transistor 100 side can be prevented, and the internal circuit can be reliably protected from electrostatic breakdown.

As described above, according to the semiconductor device for electrostatic protection of the present invention, even if a high voltage pulse of either a positive polarity or a negative polarity is applied to the output pad 300, the internal circuit is protected from static electricity. It is possible to reliably protect against such surges.

Although the output circuit has been described with reference to FIG. 2, the electrostatic protection circuit according to the present invention can be similarly applied to an input circuit. For example, the input circuit shown in FIG. 7 includes the static electricity protection circuit 200 and the internal circuit 700 shown in FIG. The internal circuit 700 includes a P-channel MOS transistor 233 and an N-channel MOS transistor 2
34 and the input pad 30 via the input line 311.
1 (signal input terminal). P-channel type MOS
The transistor 233 and the N-channel MOS transistor 234 form a CMOS inverter. The common gate of the inverter is connected to the input pad 301, and the common drain is connected to the next circuit (not shown). The input circuit shown in FIG. 7 has the same operation and effect as the output circuit shown in FIG.

Similarly to the above-described input circuit and output circuit, the electrostatic protection circuit according to the present invention can be connected to a signal input / output terminal and used for an input / output circuit.

The present invention is not limited to the above-described embodiment, but can take various forms within the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a semiconductor device for electrostatic protection according to the present embodiment.

2 is an equivalent circuit showing an example of an output circuit in which the electrostatic protection semiconductor device shown in FIG. 1 is installed.

FIG. 3 is a diagram schematically showing an operation of the output circuit shown in FIG. 2;

FIG. 4 is a diagram schematically showing an operation of the output circuit shown in FIG. 2;

FIG. 5 is a diagram schematically showing an operation of the output circuit shown in FIG. 2;

FIG. 6 is a diagram schematically showing an operation of the output circuit shown in FIG. 2;

FIG. 7 is an equivalent circuit illustrating an example of an input circuit in which the electrostatic protection semiconductor device illustrated in FIG. 1 is installed.

FIG. 8 is a diagram schematically illustrating an example of a general static electricity protection semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 silicon substrate 11 p-type well 12 element isolation region 13 n-type well 14 silicide layer 20 n-type impurity diffusion layer (emitter region) 30 p-type impurity diffusion layer (emitter region) 40 n-type impurity diffusion layer 50 p-type impurity diffusion layer Reference Signs List 60 P-type impurity diffusion layer 100 N-channel type MOS transistor 110 P-channel type MOS transistor 200 Static electricity protection circuit 210 First bipolar transistor (BP1) 220 Second bipolar transistor (BP2) 230 Zener diode (DA) 233 P-channel type MOS transistor 234 N-channel type MOS transistor 240 Diode (DB) 250 N well resistance 260 P well resistance 300 Output pad 301 Input pad 310 Output line 311 Input line 400 Power supply line 500 Ground line 600 Internal circuit 700 Input circuit

Claims (10)

[Claims] 1. A first impurity diffusion layer of a first conductivity type, and a second impurity diffusion layer of a second conductivity type electrically separated from the first impurity diffusion layer.
A first region of a first conductivity type including an impurity diffusion layer; a first region formed in the first region, having a well structure,
A second region of a second conductivity type including a third impurity diffusion layer of a conductivity type; a third region having the third impurity diffusion layer as an emitter region, the second region being a base region, and the first region being a collector region. One bipolar transistor; a second bipolar transistor having the second impurity diffusion layer as an emitter region, the first region as a base region, and the second region as a collector region; and a second bipolar transistor formed in the first region. A fourth impurity diffusion layer of a conductivity type, and a Zener diode that is joined to the fourth impurity diffusion layer and is configured by a fifth impurity diffusion layer of the first conductivity type that is continuous with the first region. Semiconductor device for static electricity protection. 2. The device according to claim 1, wherein the first impurity diffusion layer and the second impurity diffusion layer are connected to a reference power supply voltage, and the third impurity diffusion layer and the fourth impurity diffusion layer are
An electrostatic protection semiconductor device connected to a predetermined signal input terminal, signal output terminal, or signal input / output terminal. 3. The first and fourth impurity diffusion layers according to claim 1, wherein the second and third impurity diffusion layers are respectively centered on one boundary surface between the first region and the second region. A fourth impurity diffusion layer formed on the inner side of the layer and on the side opposite to the side on which the second impurity diffusion layer is formed with the third impurity diffusion layer as a center, Semiconductor device. 4. The electrostatic protection device according to claim 1, wherein the fourth impurity diffusion layer is formed continuously from the first region to the second region, and is in contact with the second region. Semiconductor device. 5. The static electricity protection semiconductor device according to claim 1, wherein the fifth impurity insulating layer is joined to a part of a bottom surface of the fourth impurity diffusion layer. 6. The static electricity protection semiconductor device according to claim 1, wherein an impurity concentration of the fifth impurity insulating layer is lower than an impurity concentration of the first and third impurity insulating layers. 7. The semiconductor device according to claim 1, wherein the first region has a well structure. 8. The method according to claim 1, wherein at least one of the impurity diffusion layers is formed on a substrate surface, and a silicide layer is formed on the impurity diffusion layer formed on the substrate surface. Semiconductor devices for electrostatic protection. 9. The static electricity protection semiconductor device according to claim 1, wherein the reference power supply voltage is ground. 10. The semiconductor device according to claim 1, wherein the semiconductor device is connected to an internal circuit including a CMOS transistor.