JP2004236004A - Image signal transforming apparatus for phase regulation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate a phase regulation when an analog signal for displaying an image is transformed into a digital signal. <P>SOLUTION: An image display unit samples the analog signal for displaying the image at timing for specifying a dot clock signal. Then, the image display unit regulates the delay time τ of the dot clock signal in a range of τ=0, 1 to 31 so that a predetermined index value V becomes the minimum. The image display unit specifies first specifies τ=12 that the index value of τ=0, 4, 8 to 28 is the minimum (refer to STEP1). Then, the image display unit calculates the index values of τ=11 and τ=13 at the periphery of τ=12, and specifies the minimum index value V(τ=10). Finally, the image display unit calculates the index values of τ=9 and τ=11 at the periphery of τ=10, and hence can rapidly specify the minimum τ=9 with the index value of τ=0-31. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image signal conversion device that converts an analog signal representing an image composed of a plurality of adjacent lines into a digital signal.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a sampling device that samples an analog signal representing an image at a predetermined timing has been used. For example, when image data input to a projector is input as an analog signal, the projector performs projection and display of an image by performing sampling and quantization of the analog signal.
[0003]
FIG. 5 is an explanatory diagram showing timing for sampling an analog video signal. The illustrated video signal includes not only a stable region having the original information of the video signal, but also transients including ringing and rounding caused by the output circuit of the video signal output device and the connection cable between the video signal output device and the projector. There is an area. The projector sets sampling timings a, b,... So as to acquire signals corresponding to each pixel in the stable region. If the sampling timings a, b,... Are inappropriate, the signal is sampled at a position shifted from the information corresponding to the original pixel, so that noise appears in the image or an image with poor sharpness is displayed. Would. For example, in the example shown in FIG. _f , The acquired signal contains h _f And the image quality is degraded.
[0004]
The projector uses a predetermined dot clock signal to specify the sampling timings a, b,. The projector can adjust the sampling timings a, b,... By giving a delay time τ to the dot clock signal and changing the phase.
[0005]
Recent projectors can automatically adjust the delay time τ. For example, in Patent Document 1, a delay time τ at which a predetermined index value V is minimized _i There is disclosed a technique for setting an optimum delay time by specifying the delay time.
[0006]
FIG. 6 shows the optimum delay time τ _i It is explanatory drawing which shows the prior art which specifies.
First, the upper part of FIG. 6 shows the configuration of sampled image data. The image data is data representing one frame of a moving image by a large number of pixel data items coordinated by xy coordinates. The image data is configured by sequentially arranging lines in the x-axis direction in the y-axis direction. Each line is configured by arranging a large number of pixels in the x-axis direction.
[0007]
In the related art, the projector calculates an index value V (τ) for all settable delay times τ, and sets the index value V to a minimum τ. _i To identify. The index value is, for example, V (τ) = Σ _y | P (y = i + 1) -p (y = i) |. p (y = i + 1) and p (y = i) are two pixel data adjacent in the y direction in the image, as shown in the upper part of FIG. The index value V (τ) is a value obtained by summing the absolute value of the difference between the two values in the y-axis direction. It is desirable that the sum of the index value V (τ) is calculated for the entire image.
[0008]
In normal image data, since the difference between adjacent pixels is relatively small, if the delay time is appropriately adjusted, the above absolute value is a value sufficiently close to 0, and the index value V (τ) is also large. It becomes almost 0.
[0009]
If the delay time τ is not optimal, the difference h described earlier with reference to FIG. _f Occurs, the index value V (τ) becomes a positive value.
[0010]
The lower part of FIG. 6 shows the relationship between the delay time and the index value V (τ). In the related art, the delay time τ at which the index value V (τ) is minimized is obtained by calculating the index value V (τ) for each of 32 preset points of τ = 0, 1,. 9 is specified as the optimal delay time.
[0011]
[Patent Document 1]
JP-A-10-133609
[Patent Document 2]
Special edition 2000-513169
[Patent Document 3]
Japanese Patent Application No. Hei 10-529398
[0012]
[Problems to be solved by the invention]
However, in the related art, since the index value V (τ) is calculated for a large number of delay times, the optimum delay time τ cannot be set quickly. For example, it may take about 3 seconds to set the optimum delay time τ.
[0013]
The present invention has been made to solve the above-described problem, and has as its object to speed up phase adjustment when converting an analog signal representing an image composed of a plurality of adjacent lines into a digital signal.
[0014]
[Means for Solving the Problems and Their Functions and Effects]
In order to solve at least a part of the problems described above, the present invention employs the following configuration.
The image signal conversion device according to the present invention includes:
An image signal conversion device for converting an analog signal representing an image composed of a plurality of adjacent lines into a digital signal,
A sampling unit that samples a signal of a predetermined number of pixels from a line signal that is an analog signal corresponding to one line,
An optimization unit that optimizes a phase adjustment amount, which is a timing from the input of the line signal to the start of the sampling,
An adjustment unit that adjusts the phase according to the adjustment amount,
The optimizing unit includes:
A primary calculation unit that quantitatively calculates a shift between the sampled lines with respect to a plurality of primary adjustment amounts set at a first interval larger than the minimum adjustment unit of the phase;
A selection unit that selects at least one adjustment amount that minimizes the deviation from the primary adjustment amounts;
Secondary calculation for quantitatively calculating the deviation around the selected primary adjustment amount with respect to a secondary adjustment amount set at a second interval smaller than the first interval. Department and
It is a gist of the present invention to include an adjustment amount setting unit that sets, in the adjustment unit, an adjustment amount that minimizes the shift as an optimal value from all adjustment amounts for which the shift has been calculated.
[0015]
This makes it possible to quickly optimize the amount of phase adjustment. This is because many calculation processes for a phase different from the finally used phase can be omitted. The evaluation of the deviation can be performed using various parameters. For example, the absolute value or the square of the difference between the data values between pixels adjacent in the direction in which the lines intersect may be applied as the deviation evaluation value. The shift may be evaluated by using only a part of the screen as the representative area, or may be evaluated by an average or a sum of the entire screen.
[0016]
In the image signal conversion device of the present invention,
When the second interval is larger than the minimum adjustment unit, a convergence control unit that operates the secondary calculation unit by treating the secondary adjustment amount as the primary adjustment amount may be provided. .
[0017]
By doing so, the shift can be calculated by sequentially narrowing the interval of the adjustment amount, and the accuracy of phase adjustment can be improved. The calculation process for converging does not need to be repeated until the sequentially narrowed second interval matches the minimum adjustment unit, and may be stopped at an arbitrary stage.
[0018]
In the image signal conversion device of the present invention,
The secondary adjustment amount may be set in a predetermined range sandwiching only the selected one adjustment amount. In other words, the secondary adjustment amount in a range where “the primary adjustment amount that is one less than the selected adjustment amount <the secondary adjustment amount <the primary adjustment amount that is one greater than the selected adjustment amount” May be set.
[0019]
By doing so, the secondary adjustment amount can be narrowed to around the selected adjustment amount, and the phase adjustment amount can be quickly optimized.
[0020]
In the image signal conversion device of the present invention,
The second interval may be の of the first interval.
[0021]
By doing so, the adjustment amount can be set without bias, so that the adjustment accuracy can be improved. Further, the interval of 1/2 has the advantage that the calculation load for setting the secondary adjustment amount is reduced.
[0022]
In the present invention, the first interval can be set arbitrarily. However, if the first interval is set to be large, the number of points for calculating the deviation is reduced, so that the processing can be sped up. , The adjustment accuracy tends to decrease. Conversely, when the first interval is set small, the opposite tendency occurs. In consideration of these contradictory effects, the first interval is smaller than 1/4 and larger than 1/16 of the adjustable range of the phase in order to speed up the process while ensuring the adjustment accuracy. It is preferable to set the range. Further, it is preferable to set in the vicinity of 1/8 of the adjustable range.
[0023]
In the image signal conversion device of the present invention,
The first intervals may be evenly set at least in a range excluding both ends.
[0024]
By doing so, it is possible to suppress the deviation of the phase adjustment amount and improve the adjustment accuracy.
[0025]
Note that, as described above, the image signal conversion device of the present invention is not limited to the case where the first intervals are set to be equal at least in a range excluding at least both ends. At least a part may be set non-uniformly. For example, a portion having a high probability of being the optimum phase may have a smaller interval than other portions.
[0026]
In the image signal conversion device of the present invention,
The optimizing unit may select the adjustment amount from a predetermined number of phases discretely set in advance.
[0027]
By doing so, the configuration of the image signal conversion device can be simplified. In addition, it is possible to shorten the set time while keeping the suitability of the set phase high.
[0028]
Note that the image signal conversion device may be capable of arbitrarily setting the phase within a range including at least a part that is continuous.
[0029]
In the image signal conversion device of the present invention,
When each of the predetermined number of phases is referred to as a section, the number of the primary adjustment amounts may be a divisor excluding 1 with respect to the number of sections corresponding to the entire adjustable range.
[0030]
By doing so, the first adjustment amount can be set without bias, and the second adjustment amount can be set relatively easily.
[0031]
In the image signal conversion device of the present invention,
An adjustment amount storage unit that stores the primary adjustment amount in advance may be provided.
[0032]
By doing so, it is not necessary to set the primary adjustment amount by calculation or the like every time adjustment is performed, and the processing can be speeded up. The primary adjustment amount can be stored in various forms. For example, all primary adjustment amounts may be stored individually, or one primary adjustment amount as a representative point may be stored, and a relative deviation from the representative point may be stored. It is good also as a format to put. In the latter case, the representative point may be, for example, a minimum value or a maximum value among a plurality of primary adjustment amounts to be stored.
[0033]
In the image signal conversion device of the present invention,
The adjustment amount storage unit stores a plurality of sets of the primary adjustment amounts,
The primary calculation unit may be configured to select one of the sets and calculate the shift.
[0034]
In this way, the success rate of the optimization can be increased.
[0035]
In the image signal conversion device of the present invention,
A retry instruction unit for instructing a retry of the adjustment,
The primary calculation unit may select a different set from the immediately preceding set.
[0036]
As described above, by applying different adjustment amounts at the time of retry, the success rate of optimization can be increased. The retry indication can be given in various forms. For example, a unique operation unit for instructing retry may be provided, or an operation such as switching of an input source of an image signal may be regarded as a retry instruction.
[0037]
In the image signal conversion device of the present invention,
The storage unit stores the primary adjustment amount according to a predetermined representative adjustment amount and a relative deviation from the representative adjustment amount,
The primary adjustment amount of each group is different only in the representative adjustment amount,
The difference between the representative adjustment amounts may be set to be smaller than the second interval.
[0038]
In this way, the success rate of the optimization can be increased.
[0039]
In the image signal conversion device of the present invention,
The first adjustment amount may not include the adjustment amounts at both ends of the predetermined number of phases.
[0040]
In this way, the success rate of the optimization can be increased. For example, when the delay time can be adjusted in 32 steps of τ = 0, 1, 2,..., 31, the primary adjustment amount may not include τ = 0 and τ = 31. Τ = 1, 5, 9,..., 29 can be given as an example of such a primary adjustment amount. According to the primary adjustment amounts of τ = 1, 5, 9,..., 29, it is possible to successfully optimize various analog signals with high probability.
[0041]
The present invention is, as a more specific configuration, an image signal conversion device that converts an analog signal representing an image composed of a plurality of adjacent lines into a digital signal,
A sampling unit that samples a signal of a predetermined number of pixels from a line signal that is an analog signal corresponding to one line,
An optimization unit that selects an optimization value from 32 predetermined adjustment amounts discretely set in advance as a timing from the input of the line signal to the start of the sampling;
An adjustment unit that adjusts the phase according to the adjustment amount,
The optimizing unit includes:
Starting from the minimum value of the predetermined adjustment amount or one value larger than the minimum value as a starting point, for each of the plurality of primary adjustment amounts set at equal intervals of 2 or more and 8 or less, A primary calculation unit that quantitatively calculates a shift between lines;
A selection unit that selects at least one adjustment amount that minimizes the deviation from the primary adjustment amounts;
Secondary calculation for quantitatively calculating the deviation around the selected primary adjustment amount with respect to a secondary adjustment amount set at a second interval smaller than the first interval. Department and
The image signal conversion device may include an adjustment amount setting unit that sets, in the adjustment unit, an adjustment amount that minimizes the difference as an optimal value from among all adjustment amounts for which the calculation of the difference has been performed.
[0042]
The primary adjustment amount may be eight, and the second interval may be の of the first interval.
[0043]
The present invention can be configured as an invention of a projector or other image display device, an image signal conversion method, and an image display method, in addition to the configuration as the image signal conversion device described above. Further, the present invention can be realized in various forms, such as a computer program for realizing these methods, a recording medium on which the programs are recorded, and a data signal including the programs and embodied in a carrier wave.
[0044]
Here, examples of the recording medium include a flexible disk, a CD-ROM, a magneto-optical disk, an IC card, a ROM cartridge, a punched card, a printed matter on which a code such as a barcode is printed, and a computer internal storage device (such as a RAM or ROM). Various computer-readable media such as a memory and an external storage device can be used.
[0045]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in the following order based on examples.
A. overall structure:
B. processing:
C. Second embodiment:
D. Third embodiment:
[0046]
A. overall structure:
FIG. 1 is an explanatory diagram showing the configuration of the image display device 100. The image display device 100 can convert an analog signal representing a still image or a moving image into a digital signal. Note that the image display device 100 may be a projector.
[0047]
The image display device 100 includes a signal input mechanism 177, an A / D converter 111, a buffer memory 112, an image display mechanism 113, an index value calculation circuit 114, a control mechanism 115, and a PLL circuit 116.
[0048]
The signal input mechanism 177 inputs an analog signal 177i from outside the image display device 100. Further, the signal input mechanism 177 inputs a synchronization signal to the PLL circuit 116 and a video signal to the A / D converter 111 based on the analog signal 177i.
[0049]
The PLL circuit 116 generates a dot clock signal that defines a sampling timing at the time of conversion into a digital signal, and inputs the signal to the A / D converter 111. The PLL circuit 116 can delay the phase of the dot clock signal in 32 stages by using a predetermined delay circuit.
[0050]
The A / D converter 111 samples the video signal according to the dot clock signal, and converts the analog video signal into a digital signal. The image data converted into the digital format is stored in the buffer memory 112. The image display mechanism 113 displays an image based on digital image data stored in the buffer memory 112.
[0051]
The index value calculation circuit 114 can calculate the deviation index value V described in FIG. 6 by reading the pixel data p stored in the buffer memory 112. All or some of the functions realized by hardware resources such as the index value calculation circuit 114 can be realized by software.
[0052]
The control mechanism 115 is configured as a microcomputer including a CPU, a ROM, a RAM, and the like, and controls operations of the PLL circuit 116, the index value calculation circuit 114, the buffer memory 112, and the like.
[0053]
FIG. 1 also shows the configuration of functional blocks realized by software by the control mechanism 115. The control mechanism 115 can realize each functional block illustrated by executing control software stored in the ROM. All or some of the illustrated functional blocks may be realized by hardware. All or part of the functions realized by the hardware resources such as the index value calculation circuit 114 can be realized by software.
[0054]
The delay time instruction unit 119 can instruct the PLL circuit 116 on the delay time τ specified by the control unit 118. Specifically, the delay time instruction unit 119 can set any one of the delay times of τ = 0, 1, 2,..., 31 (32 stages) in the PLL circuit 116. As a result, a digital signal corresponding to the delay time is recorded in the buffer 112.
[0055]
The initial value storage unit 120 stores an initial value of the delay time. In the embodiment, the initial values stored in the initial value storage unit 120 are τ = 1, 5,..., 29 where the range in which the delay time can be set is divided into eight equal parts.
Note that FIG. 1 shows τ = 0, 4,..., 28 for convenience of illustration. Hereinafter, the case of τ = 0, 4,..., 28 will be described, but the same applies to τ = 1, 5,.
First, control unit 118 instructs PLL circuit 116 of each delay time stored in initial value storage unit 120. In the subsequent processing, the instruction value to the PLL circuit 116 is determined based on the initial value until the optimum delay time is determined.
[0056]
The calculation control unit 117 instructs the index value calculation circuit 114 to calculate the index value V. The index value calculation circuit 114 calculates an index value V based on the data in the buffer memory 112 and transfers the index value V to the control unit 118.
[0057]
The control unit 118 specifies the optimum delay time by controlling the above-described functional blocks, and sets the optimum delay time in the PLL circuit 116 via the delay time instruction unit 119. The setting of the optimum delay time can be executed at various timings. In the present embodiment, the delay time is adjusted when the image signal 177i is switched and when the user operates the adjustment instruction button 102.
[0058]
B. processing:
FIG. 2 is a flowchart showing a process for setting an optimum delay time in the PLL circuit 116.
In step Sa1, the eight initial values τ = 0, 4, 8,..., 28 (originally τ = 1, 5,..., 29) of the delay time stored in the initial value storage unit 120 are controlled. The unit 118 reads out.
[0059]
In step Sa2, the image display device 100 causes the index values V (0), V (4), V (8),..., V (28) corresponding to the initial values τ = 0, 4,. ) (Originally V (1), V (5), V (9),..., V (29); the same applies hereinafter). The calculation of the index value is realized by causing the index value calculation circuit 114 to perform a calculation process in a state where the PLL circuit 116 generates a dot clock signal corresponding to the delay time τ to be calculated, as described above.
[0060]
FIG. 3 is an explanatory diagram showing index values calculated sequentially.
In STEP 1 of FIG. 3, the eight index values V (0), V (4), V (8),..., V (28) calculated in step Sa2 are indicated by black circles in the graph.
[0061]
Next, in step Sa3 of FIG. 2, the smallest index value is specified from the eight index values calculated in step Sa2. In the case of STEP 1 in FIG. 3, it is specified that the index value V (τ = 12) at the delay time τ = 12 is the minimum (originally, the index value V (τ = 13); the same applies hereinafter).
[0062]
In step Sa4 of FIG. 2, the image display device 100 specifies a section to search for the delay time τ. In the first step Sa4, a search target section is specified based on the minimum index value τ specified in step Sa3. Specifically, among the sections 0 → 4, 4 → 8,..., 24 → 28 specified by the initial values τ = 0, 4, 8,..., 28 (original sections 1 → 5, 5 → 9, .., 25 → 29. The same applies hereinafter), and the two sections around τ specified in step Sa3 are specified. In the case of STEP 1 of FIG. 3, since the minimum delay time of the index value is τ = 12, two sections 8 → 12 and 12 → 16 around τ = 12 are specified (see STEP 2 of FIG. 3).
[0063]
In step Sa5 of FIG. 2, the image display device 100 sets the delay time between the sections as the secondary delay time for the two sections specified in step Sa4. In the case of FIG. 3, as shown in STEP 2, τ = 10 in the middle between sections 8 → 12 and τ = 14 in the middle between sections 12 → 16 are set as the secondary delay time. The image display device 100 calculates an index value for these secondary delay times. Note that in STEP 2 of FIG. 3, the index values related to the calculation in step Sa5 are black circles, the index values at the section ends of the section to be searched are black squares, and the other index values calculated in the past are black triangles. Indicated.
[0064]
In step Sa6 in FIG. 2, the image display device 100 checks whether or not all the delay time index values in the search target section have been calculated. In the case of STEP 2 in FIG. 3, since τ = 9, 11 in sections 8 → 12 and τ = 13, 15 in sections 12 → 16, there are index values that have not been calculated, so that the process proceeds to step Sa7.
[0065]
In step Sa7 in FIG. 2, the image display device 100 selects one of the two sections for which the index value was calculated in step Sa5 as a target range for the next search. Here, the index values at the end points and the intermediate points of the two sections have already been calculated. In step Sa7, the section including the smallest index value among the index values already calculated is specified. In the case of STEP 2 in FIG. 3, among the index values V (τ = 8), V (τ = 10), V (τ = 12), V (τ = 14), and V (τ = 16) that have already been calculated. Since V (τ = 10) is the minimum, the section 8 → 12 including τ = 10 is selected.
[0066]
In addition, in step Sa7 of FIG. 2, the smaller one of the index values V (τ = 10) and V (τ = 14) at the intermediate point may be simply selected.
[0067]
The range selected in step Sa7 is subjected to the processing in steps Sa4 to Sa6 again. First, in step Sa4, the image display device 100 specifies two sections obtained by dividing the range selected in step Sa7 into two at the midpoint. In STEP 3 of FIG. 3, sections 8 → 10 and 10 → 12 are specified. In response to this, in step Sa5, the image display device 100 calculates an index value at the midpoint of each section specified in step Sa4. In the case of STEP 3 in FIG. 3, index values of the intermediate points τ = 9 and τ = 11 are calculated, respectively. As a result, all the index values V (8), V (9), V (10), V (11), and V (12) in the search range 8 → 12 have been completely calculated. In step Sa6, the image display device 100 shifts the processing to step Sa8.
[0068]
In step Sa8 in FIG. 2, the index value V specifies the minimum τ among the delay times in the search range. That is, the index value V specifies the smallest τ in the search range including the entire two sections specified in the latest step Sa4. In the case of STEP 3 in FIG. 3, V (9) is set as the minimum index value among the index values V (8), V (9), V (10), V (11), and V (12) in the search range 8 → 12. ) Is specified.
[0069]
In step Sa9, the image display device 100 sets the delay time specified in step Sa8 in the PLL circuit 116. In the case of STEP 3 in FIG. 3, τ = 9 is set in the PLL circuit 116 as the optimum delay time.
[0070]
According to the image display device 100 described above, the optimal delay time can be quickly set in the PLL circuit 166.
[0071]
In the embodiment, index values are first calculated for eight delay times of τ = 0, 4, 8,..., 28 (original τ = 1, 5, 9,. However, the present invention is not limited to such a case.
For example, among 16 delay times such as τ = 0, 2, 4,. ₀ After the first search, V (τ ₀ ) And V (τ ₀ +1) and V (τ ₀ The smallest one of -1) may be specified.
[0072]
Alternatively, an index value may be calculated first for two delay times such as τ = 8, 24. At this time, the optimum delay time may be searched for only in steps Sa4 to Sa9 in FIG. That is, in the first step Sa4, sections 0 → 16 and sections 16 → 31 may be specified to calculate V (τ = 8) and V (τ = 24). At this time, the optimum delay time can be searched while the search range is sequentially narrowed by ２.
[0073]
Further, in steps Sa4 to Sa9 in FIG. 2, the range of the search target is narrowed sequentially by １ ／, but may be narrowed by 狭. At this time, N segments (N is a positive integer of 2 or more) are specified in step Sa4, and an index value is calculated in the middle of each of the N segments in step Sa5, and the segment selection process is performed in step Sa7. The search range can be narrowed by 1 / N.
[0074]
Note that the graph of the index values in FIG. 3 illustrates a case where the graph has a single peak, but the same applies to a case where the graph has two or more peaks. In the embodiment, the case where the initial value is set in an equal section is illustrated, but this section may not be equal.
[0075]
Further, in step Sa3 in FIG. 2, only one τ having the smallest index value is specified, but τ having the second smallest index value may also be specified. As a result, in the processing after step Sa4, the delay time around the initial value having the second smallest index value can also be searched. At this time, in step Sa7, the search range may be reduced to ４ by selecting the segment having the smallest index value. Note that the same applies to the case where the delay time around the initial value having the third smallest index value is also searched in the processing after step Sa4.
[0076]
C. Second embodiment:
Hereinafter, a case will be described in which the initial value storage unit 120 stores a plurality of sets of initial values, and the image display device 100 selectively uses the stored plurality of sets of initial values.
[0077]
FIG. 4 is a flowchart showing a delay time setting process performed while selecting an initial value. The processing in FIG. 4 corresponds to the processing in FIG. 2 in the embodiment.
[0078]
In step Sb1 of FIG. 4, the image display device 100 specifies a first set of initial values from the first and second sets of initial values stored in the initial value storage unit 120. Here, the image display device 100 that performs the processing of FIG. 4 stores two sets of initial values of the first set and the second set in the initial value storage unit 120. In FIG. 4, the initial value storage unit 120 stores a first set of initial values τ = 1, 5, 9, 13, 17, 21, 25, 29 and a second set of initial values τ = 3, 7, 11,. 15, 19, 23, 27, and 31 are stored.
[0079]
In step Sb2 of FIG. 4, the delay time setting process described in the embodiment is performed. However, in steps Sa1 to Sa3 in FIG. 2, processing is performed on the initial value of the set specified in step Sb1 in FIG.
[0080]
In step Sb3, it is checked whether or not the user has issued a retry instruction via the adjustment instruction button 102 or the like. The user can identify failure of the delay time setting process (step Sb2 in FIG. 4) by visually recognizing that noise appears in the image or that an image with poor sharpness is displayed. When the delay time setting process has failed, the user can instruct the image display device 100 to retry the delay time setting process. If there is no retry instruction, the image display device 100 ends the process as it is. If there is a retry instruction, the image display device 100 proceeds to the process of step Sb4. Note that the image display device 100 may specify the failure of the delay time setting process by itself and automatically retry the delay time setting process.
[0081]
If there is a retry instruction, the image display device 100 specifies the second set of initial values stored in the initial value storage unit 120 in step Sb4. Thus, the delay time setting process using the second set of initial values is performed in step Sb2.
[0082]
According to the image display device 100 described above, the success rate of the optimization of the delay time can be increased by applying different sets of initial values at the time of retry.
[0083]
Note that various modes can be applied to how to take the initial value.
For example, τ = 0,4,8,12,16,20,24,28 is used in principle, and when the delay time setting processing with this initial value fails, τ = 1,5,9,13, 17, 21, 25, and 29 may be used. By doing so, a desired delay time can be specified with a high probability even in the case of an image whose contents differ greatly for each horizontal line.
Also, as initial values of the first set and the second set, τ = 1, 5,..., 29 and τ = 2, 6,. ,..., 30 may be used.
[0084]
The following effects can be obtained by the image display device 100 described above, which will be described.
[0085]
First, the results of comparison between the case of the prior art (FIG. 6) and the case of the embodiment (FIGS. 2 and 3) will be described. The number of index value calculation processes required for the delay time setting process has been improved from twelve times to twelve times. At this time, the time required for the delay time setting processing was improved from about 3.1 seconds to about 2.1 seconds. On the other hand, the probability of succeeding in the delay time setting process has only decreased from 94.4% to 76%, and a success rate comparable to that of the conventional technique has been obtained. Further, by applying the technique shown in the modified example (FIG. 4) and the like, the success rate can be improved to 93.1%, which is almost the same as the success rate of the conventional technique of 94.4%. Was.
[0086]
Next, a result of comparison between the case of the embodiment where the number of initial values is 8 (FIGS. 2 and 3) and the case where the number of initial values is 2 and 16 will be described. At this time, the number of times of the index value calculation processing is 10, 12, and 18, respectively, when the number of initial values is 2, 8, and 16. Success rates of 72%, 76%, and 82% were obtained in the delay time setting process for the number of calculation processes.
[0087]
As described above, the image signal conversion device according to the present invention has been described based on the embodiments. Absent. The present invention can be changed and improved without departing from the spirit and scope of the claims.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a configuration of an image display device 100.
FIG. 2 is a flowchart showing a process for setting an optimum delay time in a PLL circuit 116.
FIG. 3 is an explanatory diagram showing index values calculated sequentially.
FIG. 4 is a flowchart illustrating a delay time setting process performed while selecting an initial value.
FIG. 5 is an explanatory diagram showing timing for sampling an analog video signal.
FIG. 6: Optimal delay time τ _i It is explanatory drawing which shows the prior art which specifies.
[Explanation of symbols]
100 image display device
102 ... Adjustment instruction button
112 ... Buffer memory
113 ... Image display mechanism
114 ... Index value calculation circuit
115 ... Control mechanism
117: calculation control unit
177 ... Signal input mechanism
177i: External signal
118 ... Control unit
119: delay time indicating section
120: Initial value storage unit

Claims (20)

An image signal conversion device for converting an analog signal representing an image composed of a plurality of adjacent lines into a digital signal,
A sampling unit that samples a signal of a predetermined number of pixels from a line signal that is an analog signal corresponding to one line,
An optimization unit that optimizes a phase adjustment amount, which is a timing from the input of the line signal to the start of the sampling,
An adjustment unit that adjusts the phase according to the adjustment amount,
The optimizing unit includes:
A primary calculation unit that quantitatively calculates a shift between the sampled lines with respect to a plurality of primary adjustment amounts set at a first interval larger than the minimum adjustment unit of the phase;
A selection unit that selects at least one adjustment amount that minimizes the deviation from the primary adjustment amounts;
Secondary calculation for quantitatively calculating the deviation around the selected primary adjustment amount with respect to a secondary adjustment amount set at a second interval smaller than the first interval. Department and
An image signal conversion device comprising: an adjustment amount setting unit that sets, in the adjustment unit, an adjustment amount that minimizes the shift as an optimum value from all adjustment amounts for which the shift has been calculated. The image signal conversion device according to claim 1,
An image signal conversion device including a convergence control unit that operates the secondary calculation unit by treating the secondary adjustment amount as the primary adjustment amount when the second interval is larger than the minimum adjustment unit; . The image signal conversion device according to claim 1,
The image signal conversion device, wherein the secondary adjustment amount is set in a predetermined range sandwiching only the selected one adjustment amount. The image signal conversion device according to claim 1,
The image signal conversion device, wherein the second interval is の of the first interval. The image signal conversion device according to claim 1,
The image signal conversion device according to claim 1, wherein the first interval is smaller than 1/4 and larger than 1/16 of the adjustable range of the phase. The image signal conversion device according to claim 1,
The image signal conversion device according to claim 1, wherein the first interval is uniformly set at least in a range excluding both ends. The image signal conversion device according to claim 1,
The image signal conversion device, wherein the optimization unit selects the adjustment amount from a predetermined number of phases discretely set in advance. The image signal conversion device according to claim 7,
The image signal conversion device according to claim 1, wherein when the predetermined number of phases is referred to as a section, the number of the primary adjustment amounts is a divisor excluding 1 with respect to the number of sections corresponding to the entire adjustable range. The image signal conversion device according to claim 7,
An image signal conversion device including an adjustment amount storage unit that stores the primary adjustment amount in advance. The image signal conversion device according to claim 9,
The adjustment amount storage unit stores a plurality of sets of the primary adjustment amounts,
The image signal conversion device, wherein the primary calculation unit selects one of the sets and calculates the shift. The image signal conversion device according to claim 10,
A retry instruction unit for instructing a retry of the adjustment,
The image signal conversion device, wherein the primary calculation unit selects a different set from the immediately preceding set in the retry. The image signal conversion device according to claim 10,
The storage unit stores the primary adjustment amount according to a predetermined representative adjustment amount and a relative deviation from the representative adjustment amount,
The primary adjustment amount of each group is different only in the representative adjustment amount,
The image signal conversion device, wherein the difference between the representative adjustment amounts is set to be smaller than the second interval. The image signal conversion device according to claim 7,
The image signal conversion device, wherein the first adjustment amount does not include the adjustment amounts at both ends of the predetermined number of phases. The image signal conversion device according to claim 13,
The predetermined number of phases are 32 equally spaced phases defined by dividing an adjustment amount corresponding to one pixel into 32 equal parts,
When the predetermined number of phases are referred to as 0th to 31st adjustment amounts in order from the one where the adjustment amount becomes 0, the primary adjustment amounts are 1,5,9,13,17,21,25,29th Image signal conversion device that is the adjustment amount of. An image signal conversion device for converting an analog signal representing an image composed of a plurality of adjacent lines into a digital signal,
A sampling unit that samples a signal of a predetermined number of pixels from a line signal that is an analog signal corresponding to one line,
An optimization unit that selects an optimization value from 32 predetermined adjustment amounts discretely set in advance as a timing from the input of the line signal to the start of the sampling;
An adjustment unit that adjusts the phase according to the adjustment amount,
The optimizing unit includes:
Starting from the minimum value of the predetermined adjustment amount or one value larger than the minimum value as a starting point, for each of the plurality of primary adjustment amounts set at equal intervals of 2 or more and 8 or less, A primary calculation unit that quantitatively calculates a shift between lines;
A selection unit that selects at least one adjustment amount that minimizes the deviation from the primary adjustment amounts;
Secondary calculation for quantitatively calculating the deviation around the selected primary adjustment amount with respect to a secondary adjustment amount set at a second interval smaller than the first interval. Department and
An image signal conversion device comprising: an adjustment amount setting unit that sets, in the adjustment unit, an adjustment amount that minimizes the shift as an optimum value from all adjustment amounts for which the shift has been calculated. An image display device that displays an image,
An input unit for inputting an analog signal representing the image;
An image signal converter according to any one of claims 1 to 15, which converts the analog signal into a digital signal.
A display unit for displaying the sampled image. 17. The image display device according to claim 16, which is a projector. An image signal conversion method for converting an analog signal representing an image composed of a plurality of adjacent lines into a digital signal,
Sampling a signal of a predetermined number of pixels from a line signal that is an analog signal corresponding to one line,
A step of optimizing the adjustment amount of the phase, which is the timing from the input of the line signal to the start of the sampling,
Adjusting the phase according to the adjustment amount,
The optimizing step includes:
A step of quantitatively calculating a shift between the sampled lines for a plurality of primary adjustment amounts set at a first interval larger than the minimum adjustment unit of the phase;
Selecting at least one adjustment amount that minimizes the deviation from the first adjustment amount;
Around the selected primary adjustment amount, quantitatively calculating the deviation with respect to a secondary adjustment amount set at a second interval smaller than the first interval;
Setting, as an optimum value, an adjustment amount that minimizes the deviation from among all the adjustment amounts for which the deviation has been calculated. A computer program for causing a computer to convert an analog signal representing an image composed of a plurality of adjacent lines into a digital signal,
A function of inputting the sampled data from a sampling mechanism that samples a signal of a predetermined number of pixels from a line signal that is an analog signal corresponding to one line,
A function of optimizing an adjustment amount of a phase, which is a timing from the input of the line signal to the start of the sampling,
By inputting a predetermined signal to the sampling mechanism, a function of adjusting the phase according to the adjustment amount,
For realizing the function of performing the optimization,
A function of quantitatively calculating a shift between the sampled lines with respect to a plurality of primary adjustment amounts set at a first interval larger than the minimum adjustment unit of the phase;
A function of selecting at least one adjustment amount that minimizes the deviation from the primary adjustment amounts;
A function of quantitatively calculating the deviation with respect to a secondary adjustment amount set at a second interval smaller than the first interval around the selected primary adjustment amount;
A computer program for causing the computer to realize a function of setting, as an optimum value, an adjustment amount that minimizes the shift from among all adjustment amounts for which the shift has been calculated. A computer-readable recording medium on which the computer program according to claim 19 is recorded.

Images