JP2004235940A - Semiconductor integrated circuit for communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable deskewing and reference signal generation without changing the configurations between a plurality of data channels, by reducing the difference in wiring delay between a reference signal processing part and the signal processing part of each data channel in a circuit block which performs deskewing and reference signal generation, in a semiconductor integrated circuit for communication which inputs and outputs the signals of the data channels and the deskewing reference signals to be transmitted and received. <P>SOLUTION: In the circuit block (3) for performing deskewing and reference signal generation, the reference signal processing part (B) to/from which reference signals(DSC) are inputted/outputted, is arranged on a central route which divides into two a plurality of transmission lines (A00-A15) through which the signals (TXIN00-TXIN15) of the data channels are transmitted, respectively. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a communication semiconductor integrated circuit for transmitting and receiving signals of a plurality of channels, for example, an optical communication MUX (multiplexer) module for generating an optical communication signal and an optical device for dividing an optical communication signal into a plurality of channels. The present invention relates to a technique useful for a DEMUX (demultiplexer) module for communication.
[0002]
[Prior art]
An optical communication MUX module that multiplexes 2.5 Gbps × 16 channel signals to generate a 40 Gbps electric signal used in optical communication, and conversely, converts a 40 Gbps electric signal used in optical communication to a 2.5 Gbps × 16 channel signal. The DEMUX module for optical communication that divides into signals requires an interface for inputting and outputting signals of a plurality of channels.
[0003]
In such an interface for inputting and outputting signals of a plurality of channels, there is a problem of a shift in input / output timing between signals, that is, a skew between channels. In particular, when handling high-speed signals as described above, the occurrence of skew is a serious problem. Therefore, at present, a standard called SFI-5 (SerDes Framer Interface Level 5) in which a reference signal is provided to adjust the skew and the reference signal is made to run in parallel with the signals of a plurality of data channels is being developed. ing.
[0004]
In this standard, as shown in FIG. 2, the reference signal DSC includes data obtained by copying a part of data from the signals TXIN00 to TXIN15 of each data channel and serially combining them. Then, by comparing the signals TXIN00 to TXIN15 of each data channel with the signals copied in the reference signal DSC, the amount of skew between the reference signal DSC and the signals TXIN00 to TXIN15 of each channel is detected. It is designed to eliminate skew.
[0005]
[Problems to be solved by the invention]
As a result of studying a circuit for removing skew between data channels in accordance with the SFI-5 standard, the present inventors have found that there are the following difficulties.
That is, as shown in FIGS. 9A and 9B, for example, a plurality of reference signal processing units B which receive the reference signal DSC and distribute the comparison signal to the transmission lines LANE00 to LANE15 of each data channel are provided. Is arranged on one side of the transmission lines LANE00 to LANE15, the wiring required to send the signal for comparison to the nearest transmission line due to the difference in the distance between the reference signal processing unit B and each of the transmission lines LANE00 to LANE15. A difference occurs between the delay and the wiring delay required to send the signal to the farthest transmission line, and this difference becomes a level that cannot be ignored compared to the signal speed.
[0006]
Further, if a circuit configuration is added to eliminate the influence of the time difference, the circuit configuration differs between the plurality of data channels, that is, the configuration becomes asymmetric between the plurality of data channels. In circuits that perform high-speed signal processing, such as those used in optical communications, it is difficult to secure an extra operating margin for each unit.Therefore, the asymmetric configuration described above poses a new problem in achieving synchronization between data channels. This causes an increase in the load on the circuit design and a decrease in yield. Therefore, the addition of the above circuit configuration is not preferable.
[0007]
Further, as shown in FIGS. 10A and 10B, when the reference signal processing unit B is arranged at a position separated from the plurality of transmission lines LANE00 to LANE15, the reference signal processing unit B and the plurality of transmission lines LANE00 to LANE00 are arranged. The area occupied by the wiring connecting to the LANE 15 increases, leading to an increase in circuit scale and a rise in manufacturing cost.
[0008]
The above-described problem does not occur only on the input side for inputting the signals of the plurality of data channels and the reference signal, but also on the output side for outputting the signals of the plurality of data channels and the reference signal. This occurs similarly when a reference signal is generated from a signal of the data channel.
[0009]
An object of the present invention is to eliminate skew and generate a reference signal in a communication semiconductor integrated circuit that inputs or outputs a signal of a plurality of channels and a reference signal for removing skew between channels as in the SFI-5 standard. In the circuit block that performs the above, the difference in wiring delay of signals exchanged between the reference signal processing unit and the signal processing unit of each channel is reduced to a negligible level, thereby reducing the burden on the circuit design of this part. The purpose is to improve the yield.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be described as follows.
That is, in a communication semiconductor integrated circuit that inputs or outputs a reference signal for adjusting skew between channels in parallel with a signal of a plurality of channels, a reference signal is generated in a circuit block that removes skew and generates a reference signal. The input / output reference signal processing unit is arranged at a position between a first transmission path group and a second transmission path group that divide the plurality of transmission paths through which the signals of the plurality of channels are transmitted. It was done. The number of transmission lines included in the first transmission line group and the second transmission line group is not limited to the same number. For example, the first transmission line group and the second transmission line group as long as they handle signals of 16 channels. May have a difference of 2 channels or 4 channels in the number of transmission paths.
By such means, it is possible to reduce the difference in wiring delay between the reference signal processing unit to which the reference signal is input / output and each transmission path.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS.
<First embodiment>
FIG. 1 is a block diagram showing the overall configuration of a multiplexer LSI (large-scale integrated circuit) according to a first embodiment of the present invention.
The multiplexer LSI1 receives, for example, signals TXIN00 to TXIN15 of 2.5 to 2.7 Gbps × 16 data channels conforming to the SFI-5 standard and a signal (reference signal) DSC of one deskew channel. Are multiplexed to generate the output signal OUT of 40 to 43 Gbps used in optical communication. The multiplexer LSI 1 includes an input circuit 2 for inputting the above-mentioned (16 + 1) channel signal, a deskew block 3 as a timing adjustment circuit for removing skew of the 16 data channel signals TXIN00 to TXIN15 based on the reference signal DSC. And a multiplexer (MUX) 4 for multiplexing the signals TXDATA00 to TXDATA15 of the 16 data channels from which the skew has been removed.
[0012]
FIG. 2 is a data chart showing the signals TXIN00 to TXIN15 of a plurality of data channels input to the multiplexer LSI1 of FIG. 1 and the reference signal DSC.
Each of the transmitted and received data channel signals TXIN00 to TXIN15 is an arbitrary serial digital signal.
[0013]
The reference signal DSC is, for example, a serial digital signal in which a signal obtained by serially combining a 64-bit header pattern and a portion obtained by cutting out a part of data from each data channel is a signal of one frame (= 1088 bits). Specifically, as shown in FIG. 2, in a state where the signals TXIN00 to TXIN15 of the respective data channels are aligned so that there is no skew between the channels, 64-bit data continuous from the respective signals TXIN00 to TXIN15 are respectively transmitted. This is cut out from the bit position shifted by 64 bits so that the bit position does not overlap, and copied at the same bit position of the reference signal DSC.
[0014]
FIG. 3 is a diagram illustrating a schematic configuration of the deskew block 3, and FIG.
The deskew block 3 receives data signals TXIN00 to TXIN15 of each data channel and adjusts the skew of the input signals TXIN00 to TXIN15, and inputs a reference signal DSC to input data TXIN00 to TXIN15. And a reference signal processing unit B for supplying the corresponding data channel processing units A00 to A15.
[0015]
The data channel processing units A00 to A15 are formed in a layout along a transmission path through which the corresponding input signals TXIN00 to TXIN15 are transmitted. Each of the internal configurations is the same, and includes a shift register for transmitting an input signal, a first register for storing a comparison signal supplied from the reference signal processing unit B, and the contents of the first register and the shift. Decoders and the like are provided, each of which compares a part of the bits of the register with a bit and changes the time that the signal passes through the shift register based on the comparison result. The decoder also has a function of outputting a notification signal to the processing result monitoring unit B2 of the reference signal processing unit B when the skew cannot be removed because the comparison result exceeds the correctable skew amount.
[0016]
The reference signal processing unit B detects the header pattern of the input reference signal DSC, separates data from the next bit by 64 bits at a time, and outputs the data to the corresponding data channel processing units A00 to A15 as a signal for comparison. A data separation / distribution unit B1 and a processing result monitoring unit B2 that receives a notification signal indicating that skew cannot be removed and outputs a warning signal ALARM to the outside are provided. Note that the processing result monitoring unit B2 may be provided in a space other than the reference signal processing unit B.
[0017]
The data channel processing units A00 to A15 and the reference signal processing unit B are configured to operate based on an operation clock synchronized with the reference signal DSC generated based on the header detection of the reference signal DSC.
[0018]
As shown in FIG. 3, in such a deskew block 3, the plurality of data channel processing units A00 to A15 and the reference signal processing unit B are arranged in parallel so as to be adjacent to each other, and the reference signal processing unit B is arranged on the middle path so as to divide the plurality of data channel processing units A00 to A15 by half. With such an arrangement, the difference between the distances between the data channel processing units A14 and A01 that are closest to the reference signal processing unit B and the data channel processing units A00 and A15 that are farthest from each other is determined as shown in FIGS. ) Is smaller than the case where the reference signal processing unit B is disposed on one side, and a level at which a difference in wiring delay for transmitting a comparison signal from the reference signal processing unit B to each of the data channel processing units A00 to A15 can be ignored. Can be reduced to
[0019]
According to the deskew block 3 having the above configuration, when the reference signal DSC and the signals TXIN00 to TXIN15 of each data channel are input, a signal for comparison of each data channel is output from the reference signal DSC input in the reference signal processing unit B. As the signals are sequentially separated, the separated comparison signals are sequentially output to the corresponding data channel processing units A00 to A15. Then, in each data channel processing unit, a part of each of the input signals TXIN00 to TXIN15 is compared with a comparison signal, and the time length of each of the input signals TXIN00 to TXIN15 changes according to the coincident timing. . As a result, as shown in FIG. 4, even if there is a skew in the input data channel signals TXIN00 to TXIN15, the skew amounts of the input signals TXIN00 to TXIN15 with respect to the reference signal DSC are made uniform, and as a result, the data channel The skew between them is eliminated, and signals TXDATA00 to TXDATA15 of the data channel without skew are output.
[0020]
Incidentally, it is assumed that the deskew block 3 of this embodiment removes a skew of about ± 10 bits. Further, the reference signal DSC is exhausted in the deskew block 3 and is not output to a stage subsequent thereto.
[0021]
In such skew removal processing, since the reference signal DSC is input serially, the timing for separating and outputting the comparison signal from the reference signal DSC is shifted by 64 bits for each data channel. Further, the bit positions to be compared with each of the input signals TXIN00 to TXIN15 are shifted by 64 bits in the same order (see FIG. 2). Therefore, the timing of comparing the input signals TXIN00 to TXIN15 with the comparison signal in each of the data channel processing units A00 to A15 is also shifted in the same order by 64 bits for each data channel. In other words, the interval from when the comparison signal is separated and output by the reference signal processing unit B to when the input signal and the comparison signal are compared, and the comparison result from the comparison between the input signal and the comparison signal is input. The intervals until the control is reflected in the control of the signal transit time have the same time length in all data channels.
[0022]
Therefore, the difference in the wiring delay required to send the comparison signal from the reference signal processing unit B to each of the data channel processing units A00 to A15 increases, and the difference in the wiring delay causes the operation of the input register to receive the comparison signal. If the difference is not within the margin, the variation in the wiring delay causes a shift in the comparison timing, causing skew of one bit in the output signals TXDATA00 to TXDATA15. However, in the deskew block 3 of this embodiment, due to the layout of the above-described reference signal processing unit B, a wiring delay required for transmitting a comparison signal from the reference signal processing unit B to each of the data channel processing units A00 to A15 is reduced. Since the variation can be kept within the range of the operation margin of the register for inputting the comparison signal, the above-described skew removal processing can be performed normally without adding a circuit for correcting the variation of the wiring delay. Has become.
[0023]
Also, as shown in FIG. 1, in this embodiment, the arrangement order of the signals of 17 channels input to the input circuit 2 and the external terminals for inputting the data signals TXIN00 to TXIN15 of 16 channels and the reference signal DSC. The arrangement order of the external connection pins 10D and 10R is the same as the arrangement order of the input signals of the deskew block 3. That is, the external connection pin 10R for inputting the reference signal DSC is disposed at the center which vertically divides the 16 external connection pins 10D for inputting the data channel signals TXIN00 to TXIN15 by half. With such a pin arrangement, each signal can be transmitted from the input to the deskew block 3 without intersecting.
[0024]
As described above, according to the multiplexer LSI 1 of this embodiment, since the reference signal processing unit B is disposed at the center in the deskew block 3, the comparison signal is transmitted from the reference signal processing unit B to each data channel processing unit. It is possible to reduce the difference between the wiring delays to be sent to A00 to A15 so as to be within the operation margin of the input register to which the comparison signal is input. Therefore, each of the data channel processing units A00 to A15 can have the same logical configuration. By contrasting the configuration between the channels in this way, it is possible to reduce the design cost and improve the yield.
[0025]
<Second embodiment>
FIG. 5 shows an example of an overall configuration diagram of a demultiplexer LSI according to a second embodiment of the present invention.
The demultiplexer LSI 6 receives an electric signal IN of 40 to 43 Gbps used in optical communication, separates the signal, generates a reference signal DSC based on the separated signal, and complies with, for example, the SFI-5 standard. It outputs signals RXOUT00 to RXOUT15 of 2.5 to 2.7 Gbps × 16 data channels and a signal (reference signal) DSC of one deskew channel. The demultiplexer LSI 6 separates the input signal IN into 16 data channel signals RXDATA 00 to RXDATA 15 by a demultiplexer (DEMUX) 9, and converts the reference signal DSC based on the separated 16 channel data signals RXDATA 00 to RXDATA 15. A DSC generation block 8 as a reference signal generation circuit that generates and outputs the data signals of 16 channels in parallel, and an output circuit that outputs, for example, 16-channel data signals RXOUT00 to RXOUT15 and a reference signal DSC according to the SFI-5 standard. 7 is provided.
[0026]
The input signal IN is an arbitrary serial digital signal, and the signals RXOUT00 to RXOUT15 of each data channel are serial digital signals obtained by separating the input signal IN into 16 channels.
The reference signal DSC is obtained by replacing the signals TXIN00 to TXIN15 of the 16 data channels in FIG. 2 with output signals RXOUT00 to RXOUT15, and the contents of the signals are the same as those described in the first embodiment.
[0027]
FIG. 6 is a schematic configuration diagram of the DSC generation block 8, and FIG. 7 is a functional explanatory diagram of the DSC generation block 8.
The DSC generation block 8 transmits and outputs the signals RXDATA00 to RXDATA15 of the respective data channels, and also cuts out predetermined 64-bit data during this transmission and outputs the data to the reference signal processing unit D. To C15, and a reference signal processing unit D for serially connecting and outputting 64-bit data sequentially transmitted from the data channel processing units C00 to C15 after a predetermined header pattern.
[0028]
The data channel processing units C00 to C15 are formed in a layout along the transmission paths of the corresponding data signals RXDATA00 to RXDATA15. The internal configuration is the same for all data channels. For example, a shift register that transmits an input signal, a counter that counts the timing of extracting data, and a device that copies data of some bits of the shift register at a predetermined timing. And a signal processing circuit for outputting the signal to the reference signal processing unit D.
[0029]
The reference signal processing unit D includes a counter that counts a frame period, a register that holds a predetermined header pattern, and an operation clock that receives the header pattern and data transmitted from each of the data channel processing units C00 to C15. An output shift register for serially outputting in synchronization is provided.
The data channel processing units C00 to C15 and the reference signal processing unit D are configured to operate based on an operation clock generated according to the speed of the input signal IN.
[0030]
In such a DSC generation block 8, the plurality of data channel processing units C00 to C15 and the reference signal processing unit D are arranged in parallel so as to be adjacent to each other as shown in FIG. The unit D is arranged in the center so as to divide the data channel processing units C00 to C15 into half. With such an arrangement, the difference between the distances between the data channel processing units C14 and C01 that are closest to the reference signal processing unit D and the data channel processing units C00 and C15 that are farthest from each other is different from those shown in FIGS. 9A and 9B. Thus, the reference signal processing unit B is smaller than the case where the reference signal processing unit B is arranged on one side, and the difference in wiring delay for sending cutout data from each of the data channel processing units C00 to C15 to the reference signal processing unit D can be reduced. .
[0031]
According to the DSC generation block 8 having such a configuration, as shown in FIG. 7, when the signals RXDATA00 to RXDATA15 of 16 channels are transmitted from the demultiplexer 9 without skew, the signals RXDATA00 to RXDATA15 are skewed. And is output to a subsequent output circuit.
[0032]
At the same time, while the signals RXDATA00 to RXDATA15 are transmitted through the data channel processing units C00 to C15, 64-bit data at predetermined bit positions are sequentially copied (cut out) from the data channel processing unit C15 to the data channel processing unit C00. Then, they are sequentially output to the reference signal processing unit D. The position where data is cut out from the shift register for transmitting data is the same bit position in all data channel processing units C00 to C15, and the data cutout timing is shifted by 64 bits for each channel. The data cutout cycle is set so as to correspond to the length of one frame (1088 bits) of the reference signal DSC.
[0033]
In the reference signal processing unit D, a header pattern is generated in a cycle corresponding to the data length of one frame, and 64-bit data transmitted from each of the data channel processing units C00 to C15 while shifting the timing by 64 bits. Are serially connected and output. As a result, as shown in FIG. 7, the reference signal DSC is output from the DSC generation block 8 in synchronism with the signals RXDATA00 to RXDATA15 of each data channel.
[0034]
In the generation process of the reference signal DSC, the timing at which the data is cut out in each of the data channel processing units C00 to C15 is a timing shifted by 64 bits as described above. The interval until serial connection by the reference signal processing unit D is the same for all data channels. Therefore, an operation error occurs unless the difference in the wiring delay required to send the data cut out from each of the data channel processing units C00 to C15 to the reference signal processing unit D is within the operating margin of the input register receiving the cutout data. However, due to the layout of the above-described reference signal processing unit D, the difference in the wiring delay becomes small enough to be within the operation margin of the input register, so that the above-described generation processing of the reference signal DSC can be performed normally. It has become.
[0035]
In this embodiment, the arrangement order of the signals of the 17 channels input to the output circuit 7, and the external connection pins as external terminals for outputting the data signals RXOUT00 to RXOUT15 of the 16 channels and the reference signal DSC of the 1 channel. The arrangement order of 20D and 20R is the same as the arrangement order of the output signals of the DSC generation block 8. That is, the external connection pin 20R that outputs the reference signal DSC is disposed at the center that divides the 16 external connection pins 20D that output the data channel signal by half. With such a pin arrangement, each signal can be transmitted from the DSC generation block 8 to the output without crossing.
[0036]
As described above, according to the demultiplexer LSI 6 of the present embodiment, since the reference signal processing unit D is arranged at the center in the DSC generation block 8, the data channel processing units C00 to C15 transfer the reference signal processing unit D to the reference signal processing unit D. In sending the cut data, the difference in the wiring delay between the channels can be reduced so as to be within the operating margin of the circuit receiving the cut data, whereby the reference signal DSC does not need to be processed differently for each channel. Generation can be performed. That is, the configuration between the channels can be made symmetrical, thereby reducing the design cost and improving the yield.
[0037]
FIG. 8 shows an example of a specific circuit layout diagram of the multiplexer LSI 1 of the first embodiment.
Although the multiplexer LSI 1 and the demultiplexer LSI 6 have different circuit configurations from the input circuit 2 and the output circuit 7, the deskew block 3 and the DSC generation block 8, and the multiplexer 4 and the demultiplexer 9, the layout of each block is the same. Hereinafter, the case of the multiplexer LSI1 will be described, but the same layout can be applied to the case of the demultiplexer LSI6.
[0038]
On the left side of the multiplexer LSI1, 17 sets of input circuits 2 for inputting signals TXIN00 to TXIN15 of the data channel and the reference signal DSC, and input circuits 5A for inputting a synchronous clock TXCK and a reference clock TXREFCK for operating the LSI, 5C and an output circuit 5B for outputting a monitoring clock TXCKSRC for monitoring LSI operation.
[0039]
Each of the input / output circuits 2, 5A to 5C is provided with three external connection pads PAD as external terminals as shown in FIG. Each is an input pad for supplying a power supply voltage to the input / output circuit. The circuits 5A to 5C for inputting / outputting the synchronous clock TXCK, the reference clock TXREFCK, and the monitor clock TXCKSRC and the input / output pads may be provided on the upper side or lower side of the LSI.
[0040]
The input pad to which the reference signal DSC is input is provided at the center which halves the 16 input pads to which the signals TXIN00 to TXIN15 of the 16 data channels are input respectively according to the layout of the deskew block 3 and the input circuit 2. Have been.
[0041]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the spirit of the invention. Nor.
For example, in the input circuit 2 and the output circuit 7, and in the deskew block 3 and the DSC generation block 8, the arrangement order of the signals TXIN00 to TXIN15 and RXOUT00 to RXOUT15 of each data channel is not limited to those shown in FIGS. , May be arranged in any order.
[0042]
In the above embodiment, in the deskew block 3 and the DSC generation block 8, the reference signal processing unit B (or D) is a middle path that divides the 16 data channel processing units A00 to A15 (or C00 to C15) by half. Although the example provided above is shown, even if, for example, the one-stage or two-stage arrangement is shifted up and down, the closest data channel and the farthest data channel are compared with the layouts of FIGS. It is also possible to obtain the same effect as in the embodiment by reducing the difference in the distances. When the arrangement of the reference signal processing units B or D is shifted in this way, the arrangement order of the input / output circuits 2, 7 and the external connection pins 10D, 10R, 20D, 20R may be changed accordingly.
[0043]
Further, in the embodiment, the input circuit 2 and the deskew block 3 are described to transmit the signals TXIN00 to TXIN15 of each data channel and the reference signal DSC serially along one transmission path, respectively. It is also possible to adopt a configuration in which the signal of each data channel and the signal of the reference signal DSC are divided into a plurality of, for example, four, and transmitted in parallel at the subsequent stage of the circuit 2 to remove the skew. Even in such a case, when a plurality of signals are regarded as one set of signals for each channel, a plurality of reference signal processing units B for handling one set of reference signals DSC and a plurality of sets for handling signals of a plurality of sets of data channels are provided. Similar effects can be obtained by arranging the data channel processing units A00 to A15 in the same manner as in the embodiment. The same can be said for the output circuit 7 and the DSC generation block 8.
[0044]
In the above description, the invention made by the inventor has been mainly described with respect to the multiplexer LSI and the demultiplexer LSI for optical communication, which are the fields of application which are the background of the invention. However, the invention is not limited thereto. Widely used in semiconductor integrated circuits that input and output signals of a plurality of data channels and reference signals, such as an input interface IC composed of an input circuit 2 and a deskew block 3 or an output interface IC composed of an output circuit 7 and a DSC generation block 8. Can be.
[0045]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
That is, according to the present invention, it is possible to reduce a difference in wiring delay between channels of a signal transmitted between a reference signal processing unit and a location where signals of a plurality of channels are transmitted. Accordingly, in a timing adjustment circuit that removes a skew of a signal of each channel based on a reference signal, or in a reference signal generation circuit that generates a reference signal from signals of a plurality of channels, a timing adjustment process can be performed without performing a different process for each channel. Reference signal generation processing can be performed. That is, the configuration between the channels can be made symmetrical, which has the effect of reducing the design cost and improving the yield.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a multiplexer LSI according to a first embodiment of the present invention.
FIG. 2 is a data chart showing a plurality of data channel signals and reference signals input to the LSI of FIG. 1;
FIG. 3 is a diagram showing a schematic configuration of a deskew block in FIG. 1;
FIG. 4 is an explanatory diagram showing the function of a deskew block.
FIG. 5 is a block diagram showing an overall configuration of a demultiplexer LSI according to a second embodiment of the present invention.
FIG. 6 is a diagram illustrating a schematic configuration of a DSC generation block in FIG. 5;
FIG. 7 is an explanatory diagram showing functions of a DSC generation block.
FIG. 8 is a diagram illustrating an example of a layout of external connection terminals of a multiplexer LSI and a demultiplexer LSI.
FIG. 9 is a diagram illustrating a case where a reference signal processing unit is arranged on one side of a transmission path of a plurality of channels.
FIG. 10 is a diagram illustrating a case where a reference signal processing unit is arranged away from transmission paths of a plurality of channels.
[Explanation of symbols]
1 Optical communication multiplexer LSI
2 Input circuit
3 Deskew Block
4 Multiplexer
6 Optical Communication Demultiplexer LSI
7 Output circuit
8 DSC generation block
9 Demultiplexer
External connection pin for 10D data channel
External connection pin for 10R reference signal
External connection pin for 20D data channel
External connection pin for 20R reference signal
A00 to A15 Data channel processing unit
B Reference signal processing unit
C00-C15 Data channel processing unit
D Reference signal processing unit

Claims (5)

A communication semiconductor integrated circuit that performs signal processing by receiving a signal of a plurality of channels to be transmitted and received and a reference signal for adjusting timing variations of the signals of the plurality of channels,
A timing adjustment circuit that adjusts the timing of the signals of the plurality of channels so that the timing shift of the signals of the plurality of channels is reduced based on the reference signal;
In the timing adjustment circuit, a reference signal process for receiving the reference signal at a position sandwiched between a first transmission line group and a second transmission line group obtained by dividing a plurality of transmission lines through which the signals of the plurality of channels are respectively transmitted. A communication semiconductor integrated circuit, wherein a communication unit is disposed. A communication semiconductor integrated circuit capable of outputting a signal of a plurality of channels to be transmitted and received and a reference signal for adjusting timing variations of the signals of the plurality of channels,
A reference signal generation circuit that generates the reference signal based on the signals of the plurality of channels,
In the reference signal generation circuit, the reference signal is output to a portion sandwiched between a first transmission line group and a second transmission line group obtained by dividing a plurality of transmission lines through which the signals of the plurality of channels are respectively transmitted. A communication semiconductor integrated circuit, wherein a reference signal processing unit is provided. 3. The reference signal processing unit according to claim 1, wherein the reference signal processing unit is disposed at a position substantially equidistant from transmission lines at both ends among a plurality of transmission lines through which the signals of the plurality of channels are respectively transmitted. Communication semiconductor integrated circuit. The external terminal for inputting or outputting the reference signal is arranged near a central terminal among the plurality of external terminals for inputting or outputting the signals of the plurality of channels. A communication semiconductor integrated circuit according to any one of the above. 5. The communication semiconductor integrated circuit according to claim 1, wherein the reference signal is a signal including data obtained by copying data included in the transmitted and received signals of the plurality of channels.

Images