JP2004235832A - Comparator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a comparator capable of obtaining highly precise a comparison result with low power consumption and fewer errors even when an analog signal of a high frequency is inputted. <P>SOLUTION: In the comparator, first and second comparator capacities have identical capacity values. Also, a plurality of switches are set so that, during a period of sampling, they connect the first comparator capacity between the analog signal and a ground, connect the second comparator capacity between a reference signal and the ground, and connect a third comparator capacity between an output terminal and the ground by performing short-circuit with an input terminal and an output terminal of an inverter, and during a period of comparison, the switches connect the first and the second comparator capacities in parallel with polarities reversed, connect the third comparator capacity between one terminal and the ground, and connect the other terminal to the input terminal of the inverter. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a comparator that compares a voltage of an analog signal with a voltage of a reference signal and outputs a result of the comparison.
[0002]
[Prior art]
FIG. 4 is a configuration circuit diagram of an example of a conventional comparator. The comparator 42 shown in the figure is a chopper type that compares the voltage of the analog signal VIN with the voltage of the reference signal VREF and outputs the comparison result VOUT. The comparator 42 has a comparator capacitor 44 and three switches 46, 48, 50 and an inverter 52.
[0003]
Here, the switch 46 is connected between the input terminal of the analog signal VIN and the internal node A, and the switch 48 is connected between the input terminal of the reference signal VREF and the internal node A. The comparator capacitance 44 is connected between the internal nodes A and B. The inverter 52 is connected between the internal node B and the output terminal of the comparison result VOUT, and the switch 50 is connected between the input terminal and the output terminal of the inverter 52.
[0004]
The chopper-type comparator has a period during which the voltage of the analog signal VIN is sampled by the comparator capacitance, and a period during which the voltage of the analog signal VIN sampled by the comparator capacitance is compared (compared) with the voltage of the reference signal VREF.
[0005]
In the chopper type comparator 42, the switches 46 and 50 are turned on and the switch 48 is turned off during the sampling period. At this time, since both ends of the inverter 52 are short-circuited via the switch 50, the voltage between both ends becomes the logical threshold voltage Vsw of the inverter 52. Further, since the voltage of the analog signal VIN and the threshold voltage Vsw of the inverter 52 are applied to both ends of the comparator capacitor 44, the voltage on the internal node A side of the comparator capacitor 44 becomes VIN−Vsw.
[0006]
Next, in the compare period, the switches 46 and 50 are turned off and the switch 48 is turned on. At this time, the voltage of the reference signal VREF is applied to the terminal on the side of the internal node A of the comparator capacitance 44, and the voltage of the comparator signal is changed according to the amount of change VIN-VREF from the voltage of the analog signal VIN to the voltage of the reference signal VREF. The voltage of the terminal on the internal node B side of the capacitor 44, that is, the voltage of the input terminal of the inverter 52 becomes VIN−VREF + Vsw.
[0007]
This voltage is inverted and amplified by the inverter 52 and output as the comparison result VOUT. That is, when the voltage of the analog signal VIN is higher than the voltage of the reference signal VREF (VREF <VIN), the voltage of the other terminal of the comparator capacitor 44 becomes lower than the logical threshold voltage Vsw of the inverter 52. This voltage is inverted by the inverter 52, and the comparison result VOUT becomes low level. On the contrary, when the voltage is low (VREF> VIN), the comparison result VOUT becomes high level.
[0008]
In the chopper type comparator, as shown in FIG. 5, when the analog signal VIN changes at high speed, a displacement current I = C * dV / dt flows through the comparator capacitance 44, the switch 50, and the inverter 52. When this displacement current flows, the voltage at the input terminal of the inverter 52 rises by ΔV from the threshold voltage Vsw. Since this change depends on the transition speed of the analog signal VIN, the change is detected as an error in the comparison result VOUT.
[0009]
When the chopper type comparator 42 is used for an AD converter (analog-digital converter) or the like, it is necessary to suppress ΔV to several mV or less in order to maintain high accuracy. In order to achieve this, the driving capability of the inverter 52 must be increased so that the inverter 52 can flow a large current even when ΔV is small. However, in this case, there is a problem that a large through current flows through the inverter 52 and power consumption increases.
[0010]
As one means for solving such a problem, a voltage comparator described in Patent Document 1 has been proposed.
[0011]
FIG. 6 is a configuration circuit diagram of the voltage comparator disclosed in Patent Document 1. Since the details of the voltage comparator 54 shown in the figure are described in detail in Patent Document 1, the repeated description thereof will be omitted here. In brief, in the voltage comparator 54, the switches 60, 66, 68, and 74 are turned on and the other switches are turned off in the sampling period. At this time, electric charges are stored in the comparator capacitors 56 and 58 between the analog signal VIN and the ground and between the reference signal VREF and the ground, respectively.
[0012]
During the compare period, the switches 62, 64, 70, and 72 are turned on and the other switches are turned off, and two comparator capacitors 56 and 58 are connected between the reference inverter 76 and the output inverter 78 in reverse. Connected in parallel with polarity. As a result, a difference voltage based on the charges accumulated in the two comparator capacitors 56 and 58 is calculated based on the threshold voltage of the reference inverter 76, and the comparison result VOUT between the two is output from the output inverter 78. .
[0013]
In the voltage comparator 54 of Patent Document 1, similarly to the case of the comparator 42 shown in FIGS. 4 and 5, as shown in FIG. 7, a displacement current I = C * dV / dt flows through the comparator capacitor 56 during the sampling period. . However, unlike the case of the comparator 42 shown in FIGS. 4 and 5, the voltage comparator 54 of Patent Document 1 has no inverter in the path through which the displacement current flows, so that the driving capability of the inverter is increased to increase the accuracy. There is an advantage that there is no need to do this.
[0014]
However, the voltage comparator 54 of Patent Document 1 requires a reference inverter 76 for setting the threshold voltage of the output inverter 78. Therefore, the threshold voltage of the reference inverter 76 needs to be matched with the threshold voltage of the output inverter 78 with high accuracy. For this reason, even if the threshold voltages of the two are slightly deviated, this appears as an error in the comparison result VOUT of the comparator, but there is a problem that it is very difficult to accurately match the threshold voltages of the two.
[0015]
Further, in the voltage comparator 54 of Patent Document 1, in addition to the current flowing in the output inverter 78, the through current always flows in the reference inverter 76, so that there is a problem that power consumption increases.
[0016]
[Patent Document 1]
JP-A-6-273457
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-described problems of the related art, and to obtain a high-precision comparison result with low power consumption and little error even when a high-frequency analog signal is input. Is to provide.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, the present invention outputs first and second comparator capacitors having the same capacitance value, a third comparator capacitor having an arbitrary capacitance value, and a comparison result between an analog signal and a reference signal. An inverter, and a plurality of switches connecting between the first, second, and third comparator capacitors and the inverter;
The plurality of switches, during a sampling period, connect the first comparator capacitance between the analog signal and ground, connect the second comparator capacitance between the reference signal and ground, The input terminal and the output terminal of the inverter are short-circuited to connect the third comparator capacitor between the output terminal of the inverter and the ground. During the compare period, the first and second comparators are connected. Capacitors are connected in parallel with opposite polarities, the third comparator capacitor is connected between one terminal of the first and second comparator capacitors connected in parallel and ground, and the capacitors are connected in parallel. A comparator configured to connect the other terminal of the first and second comparator capacitors to an input terminal of the inverter. It is intended to provide.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the comparator of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0020]
FIG. 1 is a configuration circuit diagram of an embodiment of a comparator according to the present invention. The comparator 10 shown in FIG. 1 compares the voltage of the input analog signal VIN with the voltage of the reference signal VREF, and outputs the comparison result VOUT. Two comparator capacitors 12 having the same capacitance value are output. , 14, a comparator capacitor 16 having an arbitrary capacitance value, eleven switches 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, and an output inverter 40. ing.
[0021]
Here, the switch 18 is connected between the input terminal to which the reference signal VREF is input and the internal node C, and the switch 20 is connected between the internal nodes C and A. The switch 22 is connected between the ground and the internal node D, and the switch 24 is connected between the internal node D and the internal node B. The comparator capacitance 12 is connected between the internal nodes C and D.
[0022]
Similarly, switch 30 is connected between an input terminal to which analog signal VIN is input and internal node F, and switch 32 is connected between internal node F and internal node B. The switch 26 is connected between the ground and the internal node E, and the switch 28 is connected between the internal node E and the internal node A. The comparator capacitance 14 is connected between the internal nodes F and E.
[0023]
The inverter 40 is connected between the internal node A and an output terminal from which the comparison result VOUT is output, and the switch 38 is connected between the input terminal and the output terminal of the inverter 40. The switch 34 is connected between the internal nodes A and G, and the switch 36 is connected between the internal nodes B and G. The comparator capacitance 16 is connected between the internal node G and the ground.
[0024]
In the comparator 10, during the sampling period, as shown in FIG. 2, the switches 18, 22, 26, 30, 34, and 38 are turned on, and the other switches 20, 24, 28, 32, and 36 are turned off.
[0025]
At this time, the comparator capacitance 12 is connected between the reference signal VREF and the ground via the switches 18 and 22. Therefore, assuming that the voltage of the reference signal VREF is Vref and the capacitance value of the comparator capacitance 12 is C, the comparator capacitance 12 is charged with a charge of Q1 = C * Vref.
[0026]
Similarly, the comparator capacitor 14 is connected between the analog signal VIN and the ground via the switches 30 and 26. Accordingly, assuming that the voltage of the analog signal VIN is Vin and the capacitance value of the comparator capacitor 14 is C, the charge of the comparator capacitor 14 is charged by Q2 = C * Vin.
[0027]
The comparator capacitor 16 is connected between the input terminal of the inverter 40 and the ground via the switch 34. Further, since the input terminal and the output terminal of the inverter 40 are short-circuited via the switch 38, the voltage between both ends becomes the logical threshold voltage Vsw of the inverter 40. Therefore, assuming that the capacitance value of the comparator capacitance 16 is Csw, the charge of Q3 = Csw * Vsw is charged in the comparator capacitance 16.
[0028]
The state of the comparator 10 during the sampling period is conceptually shown in the frame of FIG.
[0029]
Next, in the compare period, as shown in FIG. 3, in the comparator 10, the switches 20, 24, 28, 32, and 36 are turned on, and the other switches 18, 22, 26, 30, 34, and 38 are turned off.
[0030]
At this time, the comparator capacitance 12 is connected between the internal nodes A and B via the switches 20 and 24, and the comparator capacitance 14 is connected between the internal nodes B and A via the switches 32 and 28. Connected between them. That is, the comparator capacitance 12 and the comparator capacitance 14 are connected in parallel between the internal nodes A and B with opposite polarities.
[0031]
The comparator capacitance 16 is connected between the internal node B and the ground via the switch 36. Further, the switch 38 is turned off, and the state of the internal node A is inverted and output by the inverter 40.
[0032]
Note that the state of the comparator 10 during the compare period is conceptually shown in the frame of FIG.
[0033]
When the compare period starts after the end of the sampling period, the internal nodes A and B shown in FIG. 3 are both in a floating state. That is, since charges do not flow into and out of the internal nodes A and B, the charge amounts stored in the comparator capacitors 12 and 14 and the comparator capacitor 16 are preserved.
[0034]
Therefore, the voltage Vb of the internal node B is Vb = Vsw. The voltage Va of the internal node A can be obtained as follows. That is, the difference between the charges charged in the comparator capacitors 12 and 14 is Q1−Q2 = C * (Vref−Vin) = 2C * (Va−Vb). Therefore, Va = (1/2) * (Vref-Vin) + Vb = (1/2) * (Vref-Vin) + Vsw.
[0035]
The voltage Va of the internal node A is inverted and amplified by the inverter 40, and is output as a comparison result VOUT. That is, when the voltage of the analog signal VIN is higher than the voltage of the reference signal VREF (VREF <VIN), the voltage Va of the internal node A becomes lower than the logical threshold value voltage Vsw. Therefore, the comparison result VOUT becomes high level. Conversely, when the voltage is low (VREF> VIN), the comparison result VOUT becomes low level.
[0036]
In the comparator 10, the displacement current does not flow during the sampling period and the voltage at the input terminal of the inverter 40 does not fluctuate. Therefore, even when a high frequency is input to the analog signal, the analog signal and the reference signal are accurately output. And the input signal band can be increased. Further, since it is not necessary to increase the driving capability of the inverter 40 in order to maintain accuracy, power consumption can be reduced accordingly.
[0037]
Further, since the reference inverter 76 is not required as compared with the voltage comparator 54 of Patent Document 1 shown in FIG. 6, there is no penetrating current, and power consumption is further reduced as compared with the voltage comparator 54. be able to. Further, since there is no influence due to the difference between the threshold values of the reference inverter 76 and the output inverter 78, the accuracy of the comparison result can be improved more than the voltage comparator 54.
[0038]
Note that VIN and VREF may be interchanged, and VIN may be connected to the comparator capacitor 12 and VREF may be connected to the comparator capacitor 14. In this case, the polarity of the comparison result is inverted.
[0039]
The present invention is basically as described above.
As described above, the comparator according to the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various modifications and changes may be made without departing from the gist of the present invention.
[0040]
【The invention's effect】
As described in detail above, according to the comparator of the present invention, since no displacement current flows during the sampling period, even when a high frequency is input to the analog signal, the analog signal and the reference signal can be accurately determined. A comparison can be made and the input signal bandwidth can be increased. Further, since it is not necessary to increase the driving capability of the inverter in order to maintain accuracy, power consumption can be reduced accordingly.
[Brief description of the drawings]
FIG. 1 is a configuration circuit diagram of an embodiment of a comparator according to the present invention.
FIG. 2 is a configuration circuit diagram showing a state of a comparator shown in FIG. 1 during a sampling period.
FIG. 3 is a configuration circuit diagram illustrating a state of a comparator during a compare period shown in FIG. 1;
FIG. 4 is a configuration circuit diagram of an example of a conventional comparator.
FIG. 5 is a configuration circuit diagram illustrating a state of a sampling period of the comparator illustrated in FIG. 4;
FIG. 6 is a configuration circuit diagram of another example of a conventional comparator.
7 is a configuration circuit diagram illustrating a state of a comparator during a sampling period illustrated in FIG. 6;
[Explanation of symbols]
10,42 Comparator 12,14,16,44,56,58 Comparator capacity 18,20,22,24,26,28,30,32,34,36,38,46,48,50,60,62,64 , 66, 68, 70, 72, 74 Switch 40, 52, 76, 78 Inverter 54 Voltage comparator

Claims (1)

A first and a second comparator capacitance having the same capacitance value, a third comparator capacitance having an arbitrary capacitance value, and an inverter for outputting a comparison result between an analog signal and a reference signal; A plurality of switches connecting between the comparator capacity and the inverter,
The plurality of switches, during a sampling period, connect the first comparator capacitance between the analog signal and ground, connect the second comparator capacitance between the reference signal and ground, The input terminal and the output terminal of the inverter are short-circuited to connect the third comparator capacitor between the output terminal of the inverter and the ground. During the compare period, the first and second comparators are connected. Capacitors are connected in parallel with opposite polarities, the third comparator capacitor is connected between one terminal of the first and second comparator capacitors connected in parallel and ground, and the capacitors are connected in parallel. A comparator set to connect the other terminals of the first and second comparator capacitors to an input terminal of the inverter.

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