JP2004228157A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily perform the adjusting process of an output amplifier gain level and also control deterioration of image quality in order to satisfy the requirements for multiple pixels and high frame rate, in the solid-state imaging device of a total pixel read system having multi-channel output system. <P>SOLUTION: The solid-state imaging device is constituted so that, on an imaging portion 4 where many photosensing portions 2 are arranged in the shape of a matrix it has a color filter 7 of a layout regulation of two vertical pixels × two horizontal pixels corresponding to each photosensing portion 2, the vertical transfer register 3 is formed in common to the phtosensing portions 2 of each column, the vertical transfer register 3 is formed of a first vertical transfer register 31 and a second register 32 which are arranged separately in both sides of the corresponding photosensing portion 2, at least four horizontal transfer registers 5A, 5B, 5C, and 5D are provided at one end of the vertical transfer register 3 to respectively transfer independent signal charges eA, eB, eC, and eD accumulated in the four photosensing portions 2A, 2B, 2C, and 2D corresponding to four pixels of arrangement specification, and moreover, output portions 6A, 6B, 6C, and 6D are respectively provided in the subsequent stage. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device, particularly to a solid-state imaging device suitable for being applied to an image sensor of an all-pixel readout system having a multi-channel output system.
[0002]
[Prior art]
FIG. 18 shows a configuration of a conventional CCD image sensor of, for example, an interline transfer system.
The CCD image sensor 50 has an image section 53 in which a plurality of light receiving sections 51 serving as pixels are arranged in a matrix, and a vertical transfer register 52 is formed on one side of each light receiving section 51. The terminal of the horizontal transfer register 54 is connected to the terminal of the horizontal transfer register 54, and the output unit 55 is connected to the terminal of the horizontal transfer register 54 via a charge-voltage converter (not shown) such as a floating diffusion region or a floating gate.
[0003]
Further, as shown in FIG. 19, two horizontal transfer registers 54 are provided in parallel (first and second horizontal transfer registers 541 and 542), and furthermore, the first and second horizontal transfer registers 541 and 542 are By connecting an output unit (first output unit 551 and second output unit 552) to the subsequent stage, a so-called multi-channel output type CCD image sensor 60 having two image signal output formats is also known. I have.
Since the other parts are the same as those in the configuration of FIG. 18, the corresponding parts are denoted by the same reference numerals, and redundant description is omitted.
[0004]
In such a CCD image sensor 50 (CCD image sensor 60), for example, by supplying four-phase vertical transfer pulses ΦV1 to ΦV4 to the image portion 53, the potential under each vertical transfer electrode (not shown) in the image portion 53 is increased. The distribution sequentially changes, so that the signal charges accumulated in each light receiving unit 51 are vertically transferred along the vertical transfer registers 52 of the image unit 53 by the horizontal transfer registers 54 (two horizontal transfer registers 541 and 542). Will be transferred to
[0005]
The signal charges transferred to, for example, the horizontal transfer register 54 are transferred to two-phase-shifted two-phase polycrystalline silicon layers (not shown) formed on the horizontal transfer register 54. The horizontal transfer pulses .phi.H1 and .PHI.H2 are sequentially transferred through the horizontal transfer register 54 to the output unit 55, converted into electrical signals at the output unit 55, and taken out as imaging signals.
[0006]
The signal charges transferred to the two horizontal transfer registers 541 and 542 are, for example, horizontal transfer electrodes (not shown) of, for example, two polycrystalline silicon layers formed on the respective horizontal transfer registers 541 and 542. )), Two horizontal transfer pulses ΦH1 and ΦH2 having different phases from each other are sequentially transferred to the output units 551 and 552 in the respective horizontal transfer registers 541 and 542, and converted into electric signals at the output units 551 and 552. Then, they are extracted as two image pickup signals.
[0007]
By the way, in recent years, in a solid-state imaging device, a demand for a large number of pixels and a high frame rate has been increasing. It is also required to be able to cope with the all-pixel reading method.
However, in order to meet these demands in a so-called single channel output type solid-state imaging device having one output format as shown in FIG. 18, the drive frequency increases, the horizontal transfer efficiency deteriorates, and the power consumption increases. And other problems.
Therefore, it is very difficult for a single-channel output type solid-state imaging device to meet the above-mentioned requirements.
[0008]
On the other hand, in the case of a so-called multi-channel output type solid-state image pickup device having two output formats shown in FIG. Can solve problems such as an increase in driving frequency, a decrease in horizontal transfer efficiency, and an increase in power consumption, which have occurred in the case of the single-channel output method.
However, if the output amplifier gain levels are not uniform at the output units 551 and 552 of the two horizontal transfer registers 541 and 542, linear defects such as vertical streaks occur on the screen, causing a problem of pixel deterioration. .
Therefore, very high-precision and high-speed output amplifier gain level adjustment processing is required.
[0009]
As shown in FIG. 20, the image unit 53 is divided into two parts (531, 532). At one end of each of the image units 531 and 532, two horizontal transfer registers 541 and 542 provided with output units 551 and 552 are provided. In the case of the provided solid-state imaging device 70 of the multi-channel output format in which the angle of view is divided into two in the horizontal direction and the output format of the imaging signal is two systems, each output unit 551 of the two horizontal transfer registers 541 and 542 If the output amplifier gain levels are not uniform in steps 552 and 552, image quality deterioration such as a vertical streak in the center of the screen occurs.
[0010]
Further, although not shown, for example, in the case of a solid-state imaging device in which the output is divided into an even line and an odd line in the horizontal or vertical direction, if the output amplifier gain levels are not uniform, horizontal stripes and vertical stripes are displayed on the screen. Occurs, the output amplifier gain level must be adjusted with very high accuracy and at high speed in the same manner as described above.
[0011]
On the other hand, in the above-described multi-channel output type solid-state imaging device, a configuration corresponding to the requirement of the all-pixel reading system is disclosed (see Patent Document 1). FIG. 21 shows a configuration in which such a solid-state imaging device is applied to a CCD image sensor. Parts corresponding to those in FIGS. 18 to 20 are denoted by the same reference numerals. In the CCD image sensor 80, similarly to the CCD image sensors 50 and 60 described above, a plurality of light receiving units 51 to be pixels are arranged in a matrix, and a vertical transfer register 52 is formed on one side of each light receiving unit 51 column. The vertical transfer registers 52 are connected to the horizontal transfer registers 541 and 542 at the ends of the vertical transfer registers 52. Further, at the ends of the horizontal transfer registers 541 and 542, a charge-to-voltage conversion means such as a floating diffusion region or a floating gate (FIG. The output units 551 and 552 are connected via a not-shown).
[0012]
In such a CCD image sensor 80, the vertical transfer register 52 is formed of the first and second vertical transfer registers 52A and 52B, and for example, the signal charges eA accumulated in the light receiving units 51A for the odd rows are converted to the first. In the vertical transfer register 52A, the signal charges eB stored in the light receiving unit 51B for the even-numbered rows are read out independently to the second vertical transfer register 52B, and the signal charges eA and the signal charges eA and eB is transferred to a horizontal transfer register 542 provided at one end of the first vertical transfer register 52A and a horizontal transfer register 541 provided at one end of the second vertical transfer register 52B.
[0013]
The signal charges eA and eB transferred to the horizontal transfer registers 542 and 541 are independently transferred in the horizontal transfer registers 542 and 541, respectively, and are provided at the subsequent stage of the horizontal transfer registers 542 and 541. The signals are converted into electric signals in the output units 51 and 552, and are taken out as two image signals of odd rows and even rows.
[0014]
[Patent Document 1]
“JP-A-9-129861”
[0015]
[Problems to be solved by the invention]
However, even in the solid-state imaging device having such a configuration, if adjustment of the output amplifier gain level between the output units 551 and 552 is not uniform, pixel deterioration such as a linear defect occurs as described above, resulting in high accuracy. It is necessary to adjust the output amplifier gain level.
[0016]
The present invention has been made in view of the above circumstances, and in a solid-state imaging device of an all-pixel reading system having a multi-channel output system, it is possible to suppress deterioration in image quality and to cope with demands for increasing the number of pixels and increasing a frame rate. Things.
[0017]
[Means for Solving the Problems]
The solid-state imaging device according to the present invention has a plurality of light receiving units as pixels that photoelectrically convert into an amount of signal charge corresponding to the amount of incident light from a subject. In the image area, a vertical transfer register is formed in common for the light receiving sections of each column, and the vertical transfer registers are first and second. The vertical transfer register is formed of a second vertical transfer register, and the first and second vertical transfer registers are separately disposed on both sides of a corresponding light receiving portion, and one end of the vertical transfer register corresponds to four pixels of the arrangement rule. At least four horizontal transfer registers for independently transferring the signal charges read from the four light receiving units are provided, and output units for outputting the signal charges are provided at the subsequent stage of each horizontal transfer register. It become one.
[0018]
According to the solid-state imaging device of the present invention, each pixel is provided on an image section in which a large number of light receiving sections as pixels that perform photoelectric conversion into signal charges of an amount corresponding to the amount of incident light from a subject are arranged in a matrix. Correspondingly, it has a color filter arranged in an arrangement rule of 2 vertical pixels × 2 horizontal pixels. In the image portion, a vertical transfer register is formed in common for the light receiving portions in each column, and the vertical transfer register is The first and second vertical transfer registers are formed separately from each other on both sides of the corresponding light receiving section. A vertical transfer register is provided in each of the light receiving units of the four pixels corresponding to the color filters, and the signal charges for each color accumulated in the four light receiving units are transferred to the first and second light receiving units arranged on both sides of each light receiving unit. Vertical rotation It is possible to read data independently from each other in the transfer registers and to perform vertical transfer in each vertical transfer register independently.
[0019]
Further, at one end of the vertical transfer register, at least four horizontal transfer registers for independently transferring the signal charges read by the four light receiving units corresponding to the four pixels of the arrangement rule are provided. Since the output sections for outputting the signal charges are provided at the subsequent stages, the signal charges corresponding to each color vertically transferred independently in each vertical transfer register can be horizontally transferred independently. And can be output independently. That is, the signal charges corresponding to each color can be output after being color-separated.
[0020]
As described above, since the signal charges corresponding to the respective colors can be output after being color-separated, it is also possible to adjust the difference between the output amplifier gain levels during the signal processing (color matching) of the signal charges corresponding to the respective colors. it can. Thus, the output amplifier gain level can be easily adjusted. Further, as described above, since the output amplifier gain level for each color can be arbitrarily adjusted in the subsequent stage, the spectral characteristics can be arbitrarily adjusted. Further, since four pixels of two vertical pixels × two horizontal pixels are output independently of each other, the boundary of the difference of the image due to the difference of the output amplifier gain level becomes not a line but a point, so that the boundary can be made inconspicuous. Therefore, pixel deterioration such as a linear defect can be suppressed.
[0021]
In addition, the solid-state imaging device according to the present invention has a configuration in which a plurality of light receiving units as pixels that photoelectrically convert an amount of signal light according to the amount of incident light from a subject are arranged in a matrix on an image unit. In the image portion, a vertical transfer register is formed in common for the light receiving portions in each column, and the vertical transfer register is The first and second vertical transfer registers are formed separately on both sides of a corresponding light receiving section, and one end of the vertical transfer register is provided with four pixels of the arrangement rule. At least two horizontal transfer registers for independently transferring the signal charges read from one of the four light receiving units corresponding to the four light receiving units are provided. To the rules At least two horizontal transfer registers for independently transferring the signal charges read from the other two light receiving units of the corresponding four light receiving units are provided, and the signal charges are output to the subsequent stage of each horizontal transfer register. Output units are provided.
[0022]
According to the solid-state imaging device of the present invention, as in the case of the solid-state imaging device described above, a large number of light-receiving units as pixels that photoelectrically convert the signal charge into an amount corresponding to the amount of incident light from the subject are arranged in a matrix. A color filter is arranged on the image portion formed in accordance with an arrangement rule of 2 pixels vertically × 2 pixels horizontally corresponding to each light receiving portion. A transfer register is formed, and the vertical transfer register is formed from the first and second vertical transfer registers. Since the first and second vertical transfer registers are separately disposed on both sides of the corresponding light receiving unit, A vertical transfer register is provided for each of the four light receiving units of four pixels corresponding to the color filter of the arrangement rule of two vertical pixels × two horizontal pixels, so that the signal charges for each color accumulated in the four light receiving units are It is possible to independently read out the data into the first and second vertical transfer registers arranged on both sides of the light receiving unit, and to perform vertical transfer independently in each vertical transfer register.
[0023]
One end of the vertical transfer register is provided with two horizontal transfer registers for independently transferring signal charges read from one of the two light receiving units corresponding to the four pixels of the arrangement rule. Is provided at least at the other end of the vertical transfer register, two horizontal lines for independently transferring signal charges read from the other two light receiving units of the four light receiving units corresponding to the arrangement rule. Since at least a transfer register is provided, and an output section for outputting a signal charge is provided at a stage subsequent to each horizontal transfer register, each of the two light receiving sections is independently read out to each vertical transfer register. The signal charges corresponding to each color can be vertically transferred to two horizontal transfer registers provided at one end of each vertical transfer register. It becomes possible to vertically transfer signal charges corresponding to each color read to each vertical transfer register independently to two horizontal transfer registers provided at the other end of each vertical transfer register. .
Further, similarly to the case of the solid-state imaging device described above, signal charges corresponding to each color vertically transferred independently in each vertical transfer register can be horizontally transferred independently, and further independently. Output. That is, the signal charges corresponding to each color can be output after being color-separated.
[0024]
In addition, since the signal charges corresponding to the respective colors can be output after being color-separated, the difference between the output amplifier gain levels is also adjusted during the signal processing (color matching) of the signal charges corresponding to the respective colors, as described above. The output amplifier gain level can be easily adjusted. Further, as described above, since the output amplifier gain level for each color can be arbitrarily adjusted in the subsequent stage, the spectral characteristics can be arbitrarily adjusted. In addition, since the boundary of the image difference due to the difference in the output amplifier gain level is not a line but a point, it can be made less noticeable. Therefore, pixel deterioration such as a linear defect can be suppressed.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, an embodiment in which the solid-state imaging device according to the present invention is applied to an image sensor having a two-layer four-phase CCD structure will be described.
As shown in FIG. 1, a CCD image sensor 111 according to the present embodiment has a plurality of light receiving units 2 serving as pixels arranged on an image unit 4 in which many light receiving units 2 are arranged in a matrix. And a color filter (not shown) arranged according to an arrangement rule of two vertical pixels × two horizontal pixels. In the image section 4, a vertical transfer register 3 is formed in common with the light receiving sections 2 in each column. It becomes.
[0026]
As shown in FIG. 2, a color filter formed on the image section 4 and having a vertical 2 pixel × horizontal 2 pixel arrangement rule has, for example, an odd number row in which R and Gr are sequentially arranged along the horizontal direction. A so-called Bayer array color filter 7 in which a large number of the blocks are arranged in the horizontal direction as one block, and a large number of the blocks are arranged in the horizontal direction in the order of Gb and B in the horizontal direction for even-numbered rows. Used.
Since the color filter 7 is formed such that one color is assigned to one light receiving portion 2, the light receiving portions 2A, 2B, 2C, and 2D of 2 vertical pixels × 2 horizontal pixels shown in FIG. The four colors R, Gr, Gb, and B of the color filter 7 correspond to each other. For example, R corresponds to the light receiving unit 2A, Gr corresponds to the light receiving unit 2B, Gb corresponds to the light receiving unit 2C, and B corresponds to the light receiving unit 2D. are doing.
In the illustrated example, of the four light receiving units 2A, 2B, 2C, and 2D corresponding to the colors R, Gr, Gb, and B, the upper two light receiving units 2A and 2B are odd-numbered rows and the lower light receiving unit. Let 2C and 2D be even rows.
[0027]
As shown in FIG. 3, the image section 4 has a large number of transfer channel regions (vertical transfer registers) 3 formed by, for example, n-type impurity diffusion, which are transfer paths for signal charges, in the vertical direction. In the illustrated example, the transfer channel regions are shown as 3, 33... Each of the transfer channel regions 3 has a first channel stop region 8 which is formed in a central portion thereof by, for example, p-type impurity diffusion extending in a vertical direction and is separated into right and left.
Accordingly, in the following description, of the transfer channel regions separated into right and left, the left transfer channel region is referred to as a first transfer channel region (first vertical transfer register) 31, and the right transfer channel region is referred to as a second transfer channel region. Transfer channel region (second vertical transfer register) 32 of FIG. When collectively shown, it is simply referred to as a transfer channel region 3.
[0028]
In the image section 4, of the light receiving sections 2A and 2B for the odd-numbered rows, the second channel stop area 9 is located between the light receiving section 2A and the second transfer channel area 32 of the transfer channel area 33 adjacent to the left side in the drawing. Is formed, and the second channel stop region 9 is formed between the light receiving section 2B and the first transfer channel region 31 of the transfer channel region 33 adjacent to the right side in the drawing.
A second channel stop region 9 is formed between the light receiving unit 2C and the first transfer channel region 31 of the transfer channel region 3 adjacent to the right side in the drawing among the light receiving units 2C and 2D for even rows, A second channel stop region 9 is formed between the light receiving section 2D and the second transfer channel region 32 of the transfer channel region 3 adjacent on the left side in the drawing.
The second channel stop region 9 is also formed continuously between the light receiving units adjacent in the vertical direction (between the light receiving units 2A and 2C and between the light receiving units 2B and 2D in FIG. 3).
[0029]
Further, of the light receiving units 2A and 2B related to the odd rows, the region between the light receiving unit 2A and the first transfer channel region 31 of the transfer channel region 3, the light receiving unit 2B and the second transfer channel region of the transfer channel region 3 32, the read gate units 10A and 10B are formed in the region between the light receiving unit 2C and the second transfer channel region 32 of the transfer channel region 33 among the light receiving units 2C and 2D for even rows. Readout gate units 10C and 10D are formed in a region between the light receiving unit 2D and the first transfer channel region 31 of the transfer channel region 33.
[0030]
Thus, in the light receiving units 2A and 2B for the odd rows, the read gate units 10A and 10B are formed to face each other. In the light receiving units 2C and 2D for even rows, each of the read gate units 10C and 10D is formed to face an adjacent light receiving unit (not shown).
[0031]
Therefore, in the light receiving units 2 adjacent to each other on the left and right, the read gate units 10 are formed to face each other, and in the light receiving units adjacent vertically (the light receiving units 2A and 2C and the light receiving units 2B and 2D in the example of FIG. 3), The configuration is such that the direction of the portion is reversed.
As a result, it is possible to read out the signal charges stored in the light receiving units 2 adjacent to the right and left sides to the same vertical transfer register 3.
[0032]
With this configuration, the signal charges eA, eB, eC, and eD accumulated in the light receiving units 2A, 2B, 2C, and 2D corresponding to the colors R, Gr, Gb, and B of the color filter 7 are converted. , And can be read out with color separation independently through each of the readout gate sections 10A, 10B, 10C, and 10D.
[0033]
On each transfer channel region 3, that is, for the first and second transfer channel regions 31 and 32, for example, four vertical transfer electrodes (first to fourth vertical transfer electrodes) of, for example, two polycrystalline silicon layers are commonly used. The transfer electrodes 15a to 15d) are one set, and a large number of the sets are sequentially arranged in the vertical direction. In particular, in the illustrated example, for example, the first and second vertical transfer electrodes 15a and 15b are arranged adjacent to the light receiving units 2C and 2D for even rows, and the first and second vertical transfer electrodes 15a and 15b are adjacent to the light receiving units 2A and 2B for odd rows. Third and fourth vertical transfer electrodes 15c and 15d are arranged.
[0034]
In the present embodiment, in particular, at one end of the vertical transfer register 3 (below the image section 4 in the figure), four light receiving sections corresponding to 4 pixels in the arrangement rule of 2 × 2 pixels Four horizontal transfer registers 5A, 5B, 5C, and 5D for independently transferring the signal charges eA, eB, eC, and eD accumulated in 2A, 2B, 2C, and 2D are provided. Output units 6A, 6B, and 6C output signal charges eA, eB, eC, and eD via charge-voltage conversion means (not shown) such as a floating diffusion region or a floating gate at the subsequent stage of 5B, 5C, and 5D. , 6D.
[0035]
Between each horizontal transfer register (between the horizontal transfer register 5C and the horizontal transfer register 5A, between the horizontal transfer register 5A and the horizontal transfer register 5B, and between the horizontal transfer register 5B and the horizontal transfer register 5C), a transfer gate 11 between horizontal transfer registers is provided. Each is provided.
[0036]
The correspondence between each vertical transfer register (transfer channel region) 3 and each horizontal transfer register 5 is, for example, a horizontal line through the first transfer channel region 31 of the transfer channel region 3 from which the signal charge eA from the light receiving section 2A is read. A transfer register 5A is provided, and a horizontal transfer register 5B is provided so as to communicate with the second transfer channel region 32 of the transfer channel region 3 from which the signal charge eB from the light receiving section 2B is read. Further, a horizontal transfer register 5C is provided so as to communicate with the second transfer channel region 32 of the transfer channel region 33 from which the signal charge eC from the light receiving unit 2C is read, and the transfer channel region from which the signal charge eD from the light receiving unit 2D is read. A horizontal transfer register 5D is provided through 33 first transfer channel regions.
[0037]
Next, the actual operation of the CCD image sensor according to the present embodiment will be described with reference to FIGS.
First, a charge reading operation for reading each signal charge from each light receiving unit will be described with reference to a timing chart of FIG. 4A and an operation conceptual diagram of FIG. FIG. 5A shows the charge reading operation of the light receiving unit 2C (2D) for the even-numbered row, and FIG. 5B shows the charge reading operation of the light receiving unit 2A (2B) for the odd-numbered row.
First, at time t0 immediately before reading in FIG. 4A, a first vertical transfer pulse φV1 applied to the first vertical transfer electrode 15a and a third vertical transfer pulse φV3 applied to the third vertical transfer electrode 15c are generated. The second vertical transfer pulse φV2 applied to the second vertical transfer electrode 15b and the fourth vertical transfer pulse φV4 applied to the fourth vertical transfer electrode 15d are respectively at a high level (eg, 0 V). (For example, −9 V), a potential well is formed in a region below the first and third vertical transfer electrodes 15 a and 15 c in the first and second transfer channel regions 31 and 32 of each transfer channel region 3. It is formed.
At this time, since the potential steps under the first and third vertical transfer electrodes 15a and 15c are located at positions shallower than the potential steps of the light receiving sections 2A, 2B, 2C, and 2D, the light receiving sections 2A, 2B, 2C, and 2D. Does not flow in the signal charges eA, eB, eC, and eD.
[0038]
At the next time t1, the first vertical transfer pulse φV1 becomes the read level (for example, 15 V), so that the potential well below the first vertical transfer electrode 15a becomes deeper than the potential step of the light receiving units 2C and 2D. As a result, the signal charges eC and eD corresponding to Gb and B accumulated in the light receiving units 2C and 2D for the even-numbered rows are below the first vertical transfer electrode 15a. The signal charge eD is transferred and accumulated under the first vertical transfer electrode 15a in the first transfer channel region 31 of the transfer channel region 33 under the first vertical transfer electrode 15a in the second transfer channel region 32. Become.
At this time, the signal charges eA and eB stored in the light receiving sections 2A and 2B for the odd rows are prevented from being transferred below the third vertical transfer electrode 15c by the second channel stopper region.
[0039]
Next, at time t2, since the first vertical transfer pulse φV1 returns to the original high level (0 V), the transfer is performed below the first vertical transfer electrode 15a in the second transfer channel region 32 of the transfer channel region 33. The transferred signal charge eC and the signal charge eD transferred under the first vertical transfer electrode 15a in the first transfer channel region 31 of the transfer channel region 33 still remain under the first vertical transfer electrode 15a. .
[0040]
Then, at the next time t3, the third vertical transfer pulse φV3 becomes the read level (15 V), so that the potential well below the third vertical transfer electrode 15c is higher than the potential step of the light receiving units 2A and 2B. As a result, the signal charges eA and eB corresponding to R and Gr stored in the light receiving units 2A and 2B for the odd rows are reduced below the third vertical transfer electrode 15c, and in particular, in this case, the signal charges eA are transferred to the transfer channel. The signal charge eB is transferred and accumulated under the third vertical transfer electrode 15c in the first transfer channel region 31 of the region 3, and the signal charge eB is transferred below the third vertical transfer electrode 15c in the second transfer channel region 32 of the transfer channel region 3. Will be transferred and stored.
At this time, the signal charges eC and eD from the light receiving units 2C and 2D in the even-numbered rows still remain in the first transfer channel region 32 of the transfer channel region 33 and the first transfer channel region 31 of the transfer channel region 33. It will stay below the vertical transfer electrode 15a.
[0041]
Next, at time t4, the third vertical transfer pulse φV3 returns to the original high level (0 V), so that the signal charges eC and eD in the even-numbered rows are still in the second transfer channel region 32 of the transfer channel region 33. And the transfer channel region 33 remains below the third vertical transfer electrode 15c in the first transfer channel region 31. At this time, the odd-numbered signal charges eA and eB still remain below the first vertical transfer electrodes 15a of the first and second transfer channel regions 31 and 32 of the transfer channel region 3.
[0042]
Next, at time t5, since the second vertical transfer pulse φV2 becomes high level (0 V), one continuous potential well is formed from below the first vertical transfer electrode 15a to below the third vertical transfer electrode 15c. As a result, the signal charges eC and eD are transferred to the first to third vertical transfer electrodes (15a) in the second transfer channel region 32 of the transfer channel region 33 and the first transfer channel region 31 of the transfer channel region 33. 15c) are transferred and accumulated in a potential well formed continuously below, and the signal charges eA and eB are transferred to the first to third transfer channels in the first transfer channel region 31 and the second transfer channel region 32 of the transfer channel region 3. Are transferred and accumulated in a potential well formed continuously below the vertical transfer electrodes (15a to 15c).
[0043]
Next, at time t6, the third vertical transfer pulse φV3 becomes low level (−9V), so that a potential barrier is formed below the third vertical transfer electrode 15c, and the signal charges out of the signal charges eC and eD. The electric charge eC is transferred and accumulated in a potential well formed continuously below the first and second vertical transfer electrodes 15a and 15b in the second transfer channel region 32 of the transfer channel region 33, and the signal charge eD is transferred to the transfer channel. Data is transferred and accumulated in a potential well formed under the first and second vertical transfer electrodes 15a and 15b in the first transfer channel region 31 of the region 33.
Further, of the signal charges eA and eB, the signal charge eA is transferred to a potential well formed continuously below the first and second vertical transfer electrodes 15a and 15b in the first transfer channel region 31 of the transfer channel region 3. The accumulated signal charges eB are transferred and accumulated in a potential well formed under the first and second vertical transfer electrodes 15a and 15b in the second transfer channel region 32 of the transfer channel region 3.
[0044]
Therefore, of the light receiving units 2A and 2B for the odd rows, the signal charge eA corresponding to R accumulated in the light receiving unit 2A is read out to the first transfer channel region 31 of the transfer channel region 3 through the read gate unit 10A, The signal charge eB corresponding to Gr accumulated in the light receiving unit 2B is read out to the second transfer channel region 32 of the transfer channel region 3 through the read gate unit 10B.
Further, of the light receiving units 2C and 2D for the even rows, the signal charge eC corresponding to Gb accumulated in the light receiving unit 2C is read out to the second transfer channel region 32 of the transfer channel region 33 through the read gate unit 10C, The signal charge eD corresponding to B accumulated in the light receiving unit 2D is read out to the first transfer channel region 31 of the transfer channel region 33 through the read gate unit 10D.
That is, in the CCD image sensor 1 according to the present embodiment, the signal charges eA, eB, eC, eD corresponding to the respective colors R, Gr, Gb, B read from the respective light receiving sections 22A, 2B, 2C, 2D are Each color can be read out to each transfer channel area 3 (first and second transfer channel areas 31 and 32) independently of each other.
[0045]
Next, a vertical transfer operation (a transfer operation along a vertical transfer register) in the image sensor according to the above embodiment will be described with reference to a timing chart of FIG. 4B and operation conceptual diagrams of FIGS. 6 and 7.
FIG. 6 shows the vertical transfer operation of the signal charges eC and eD stored in the light receiving section 2C (2D) for the even rows, and FIG. 7 shows the signal charges eA and e stored in the light receiving section 2A (2B) for the odd rows. The vertical transfer operation of eB is shown.
First, after the end of the charge reading operation shown in FIG. 5, the signal charge eC among the signal charges eC and eD in the even-numbered rows is transferred to the first and second vertical transfer channels in the second transfer channel region 32 of the transfer channel region 33. The signal charge eD is transferred and accumulated under the electrodes 15a and 15b, and is transferred and accumulated under the first and second vertical transfer electrodes 15a and 15b in the first transfer channel region 31 of the transfer channel region 33. Of the signal charges eA and eB in the row, the signal charge eA is transferred and accumulated in a potential well formed continuously below the first and second vertical transfer electrodes 15a and 15b in the first transfer channel region 31 of the transfer channel region 3. Then, the signal charges eB are placed below the first and second vertical transfer electrodes 15a and 15b in the second transfer channel region 32 of the transfer channel region 3. Illustrating the state of being transferred to and stored in connection formed potential well (at t11).
[0046]
At the next time t12, since the fourth vertical transfer pulse φV4 becomes high level, a potential well is formed below the fourth vertical transfer electrode 15d, whereby the signal charges eC and eD are transferred to the transfer channel region 33. Transfer to potential wells formed continuously below the first, second and fourth vertical transfer electrodes 15a, 15b, 15d in the second transfer channel region 32 and the first transfer channel region 31 of the transfer channel region 33. The accumulated signal charges eA and eB are continuously formed under the first, second and fourth vertical transfer electrodes 15a, 15b and 15d in the first and second transfer channel regions 31 and 32 of the transfer channel region 3. Is transferred and accumulated in the potential well.
[0047]
At the next time t13, since the second vertical transfer pulse φV2 becomes low level, a potential barrier is formed below the second vertical transfer electrode 15b, whereby the signal charges eC and eD are transferred to the transfer channel region 33. The signal charges eA are transferred and accumulated in potential wells formed continuously below the first and fourth vertical transfer electrodes 15a and 15d in the second transfer channel region 32 and the first transfer channel region 31 of the transfer channel region 33. And eB are transferred and accumulated in a potential well formed continuously below the first and fourth vertical transfer electrodes 15a and 15d in the first and second transfer channel regions 31 and 32 of the transfer channel region 3.
[0048]
Next, at t14, since the third vertical transfer pulse φV3 becomes high level, a potential well is formed below the third vertical transfer electrode 15c, whereby the signal charges eC and eD are transferred to the transfer channel region 33. Transfer / accumulation is performed in a potential well formed continuously below the first, third, and fourth vertical transfer electrodes 15a, 15c, 15d in the first transfer channel region 31 of the second transfer channel region 32 and the transfer channel region 33. Then, the signal charges eA and eB are continuously formed under the first, third and fourth vertical transfer electrodes 15a, 15c and 15d in the first and second transfer channel regions 31 and 32 of the transfer channel region 3. Transferred and accumulated in the potential well.
[0049]
Next, at time t15, since the first vertical transfer pulse φV1 becomes low level, a potential barrier is formed below the first vertical transfer electrode 15a, whereby the signal charges eC and eD are transferred to the transfer channel region 33. Are transferred and accumulated in potential wells formed continuously below the third and fourth vertical transfer electrodes 15c and 15d in the second transfer channel region 32 and the first transfer channel region 31 of the transfer channel region 33. eA and eB are transferred and accumulated in potential wells formed continuously below the third and fourth vertical transfer electrodes 15c and 15d in the first and second transfer channel regions 31 and 32 of the transfer channel region 3.
[0050]
Next, at time t16, since the second vertical transfer pulse φV2 becomes high level, a potential well is formed below the second vertical transfer electrode, whereby the signal charges eC and eD are transferred to the transfer channel region 33. Are transferred and accumulated in potential wells formed continuously under the second to fourth vertical transfer electrodes (15b to 15d) in the second transfer channel region 32 and the first transfer channel region 31 of the transfer channel region 33, respectively. The signal charges eA and eB are transferred to potential wells formed continuously under the second to fourth vertical transfer electrodes (15b to 15d) in the first and second transfer channel regions 31 and 32 of the transfer channel region 3. Stored.
[0051]
Next, at time t17, since the fourth vertical transfer pulse φV4 becomes low level, a potential barrier is formed below the fourth vertical transfer electrode 15d, whereby the signal charges eC and eD are transferred to the transfer channel region. The signal is transferred and accumulated in a potential well formed continuously below the second and third vertical transfer electrodes 15b and 15c in the second transfer channel region 32 and the first transfer channel region 31 of the transfer channel region 33. The charges eA and eB are transferred and accumulated in a potential well formed continuously below the second and third vertical transfer electrodes 15b and 15c in the first and second transfer channel regions 31 and 32 of the transfer channel region 3. .
[0052]
Next, at time t18, since the first vertical transfer pulse φV1 becomes high level, a potential well is formed below the first vertical transfer electrode 15a, whereby the signal charges eC and eD are transferred to the transfer channel region. In the second transfer channel region 32 of the transfer channel region 33 and the first transfer channel region 31 of the transfer channel region 33, transfer and accumulation are performed in potential wells continuously formed below the first to third vertical transfer electrodes (15a to 15c). And the signal charges eA and eB are transferred to the potential wells continuously formed below the first to third vertical transfer electrodes (15a to 15c) in the first and second transfer channel regions 31 and 32 of the transfer channel region 3.・ Accumulated.
[0053]
Next, at time t19, since the third vertical transfer pulse φV3 becomes low level, a potential barrier is formed below the third vertical transfer electrode 15c, whereby the signal charges eC and eD are transferred to the transfer channel region. In the second transfer channel region 32 of the transfer channel region 33 and the first transfer channel region 31 of the transfer channel region 33, transfer and accumulation are performed in potential wells continuously formed below the first and second vertical transfer electrodes (15a and 15b). And the signal charges eA and eB are transferred to the potential wells continuously formed under the first and second vertical transfer electrodes (15a and 15b) in the first and second transfer channel regions 31 and 32 of the transfer channel region 3.・ Accumulated.
[0054]
At this stage, the second transfer channel region 32 of the transfer channel region 33 and the first and second vertical transfer electrodes 15a and 15b of the first transfer channel region 31 of the transfer channel region 33 are continuously formed in the previous stage. The signal charges eC and eD accumulated in the potential wells are respectively transferred to the second transfer channel region 32 of the transfer channel region 33 and the first and second transfer channel regions 31 of the transfer channel region 33 in the next stage. Is transferred and accumulated in a potential well formed continuously below the vertical transfer electrodes 15a and 15b.
Further, the signal charges eA accumulated in the potential wells formed under the first and second vertical transfer electrodes 15a and 15b in the first and second transfer channel regions 31 and 32 of the transfer channel region 3 in the previous stage. And eB are transferred to potential wells formed continuously under the first and second vertical transfer electrodes 15a and 15b in the first and second transfer channel regions 31 and 32 of the transfer channel region 3 in the next stage, respectively. Stored.
[0055]
As described above, the first to fourth vertical transfer pulses φV1 to φV4 are applied to the vertical transfer electrodes (15a to 15d) at the timing shown in FIG. 4B, so that each of the transfer channel regions 3 (31 And the signal charges eA, eB, eC and eD read out in the transfer channel regions 3 (31 and 32) are sequentially transferred in the vertical direction while being independent.
[0056]
That is, the signal charge eA corresponding to R accumulated in the light receiving unit 2A is sequentially transferred vertically downward in the first transfer channel region 31 of the transfer channel region 3, and is transferred to the Gr accumulated in the light receiving unit 2B. The corresponding signal charges eB are sequentially transferred vertically downward in the second transfer channel region 32 of the transfer channel region 3. The signal charge eC corresponding to Gb accumulated in the light receiving unit 2C is sequentially transferred vertically downward in the second transfer channel region 32 of the transfer channel region 33, and is transferred to the B accumulated in the light receiving unit 2D. The corresponding signal charges eD are sequentially transferred vertically downward in the first transfer channel region 31 of the transfer channel region 33.
[0057]
The signal charges eA, eB, eC, and eD corresponding to the respective colors R, Gr, Gb, and B transferred independently from the transfer channel regions 3 (31, 32) correspond to the respective transfer channel regions 3. Then, the data is transferred to each of the horizontal transfer registers 5A, 5B, 5C, 5D provided at one end thereof.
That is, the signal charges eA transferred in the first transfer channel 31 of the transfer channel region 3 are transferred to the horizontal transfer register 5A, and the signal charges eB transferred in the second transfer channel region 32 of the transfer channel region 3 are transferred to the horizontal transfer register 5A. The data is transferred to the horizontal transfer register 5B. The signal charge eC transferred in the second transfer channel region 32 of the transfer channel region 33 is transferred to the horizontal transfer register 5C by the signal charge eD transferred in the first transfer channel region 31 of the transfer channel region 33. Are respectively transferred to the horizontal transfer register 5D.
[0058]
The signal charges eA, eB, eC, and eD corresponding to the colors R, Gr, Gb, and B transferred to the horizontal transfer registers 5A, 5B, 5C, and 5D are, for example, horizontally formed by two polycrystalline silicon layers. By applying two-phase horizontal transfer pulses φH1 and φH2 having different phases to transfer electrodes (not shown), the signals are sequentially transferred in the horizontal transfer registers 5A, 5B, 5C and 5D in the horizontal direction, respectively. Each of the output units 6A, 6B, 6C, 6D provided at the subsequent stage of the transfer registers 5A, 5B, 5C, 5D is converted into an electric signal and taken out as an image signal from the output unit 6A, 6B, 6C, 6D. Become.
That is, four signal charges eA, eB, eC, and eD corresponding to each color R, Gr, Gb, and B can be simultaneously color-separated and output by one horizontal transfer operation.
[0059]
As described above, in the CCD image sensor 111 according to the present embodiment, each color R, Gr, and R of the color filter (see FIG. 2) formed on the image portion 4 and having the arrangement rule of two vertical pixels × two horizontal pixels. The signal charges eA, eB, eC, and eD accumulated in the light receiving units 2A, 2B, 2C, and 2D corresponding to Gb and B can be read out to the respective vertical transfer registers 3 (31 and 32) independently.
[0060]
In addition, the signal charges eA, eB, eC, and eD corresponding to the colors R, Gr, Gb, and B, which are read independently, are respectively independently transferred to the vertical transfer registers 3 (the first vertical transfer register 31 and the first vertical transfer register 31). 2 vertical transfer registers 32) can be transferred vertically.
[0061]
Also, one horizontal transfer register 5 (5A, 5B, 5C and 5D in the present embodiment) is provided for one light receiving unit 2 (four light receiving units 2A, 2B, 2C and 2D in the present embodiment). As a result, the signal charges eA, eB, eC, and eD corresponding to the respective colors R, Gr, Gb, and B accumulated in the respective light receiving units 2 are output in one unit, and the respective colors R, Gr, and During signal processing for color matching of the signal charges eA, eB, eC, and eD corresponding to Gb and B, the difference between the output amplifier gain levels can be adjusted, so that the output amplifier gain level can be easily adjusted.
Further, the adjustment of the output amplifier gain level for each of the colors R, Gr, Gb, B can be arbitrarily adjusted in the subsequent stage, and the spectral characteristics can be arbitrarily adjusted.
[0062]
At the time of one horizontal transfer, the signal charges eA, eB, eC, and eD corresponding to the respective colors R, Gr, Gb, and B are independently transferred horizontally in the horizontal transfer registers 5A, 5B, 5C, and 5D. Since the signals are output from the output units 6A, 6B, 6C, and 6D provided in the subsequent stages of the horizontal transfer registers 5A, 5B, 5C, and 5D, respectively, they are separated into colors. In comparison, it is possible to obtain about twice the frame rate at the same driving frequency (this multiple changes depending on the horizontal transfer blanking period).
[0063]
Although the output units 6A, 6B, 6C, and 6D are different for each of the light receiving units 2A, 2B, 2C, and 2D, even if a deviation of the output amplifier gain level occurs between the output units 6, the deviation of the output amplifier gain is obtained. Is generated for each of the light receiving sections 2A, 2B, 2C, and 2D, so that it does not become a linear defect and becomes a dot, making it less noticeable.
[0064]
Further, in the CCD image sensor 1 according to the present embodiment, the same timing of the charge readout operation and the timing of the charge transfer operation in the vertical direction as in the normal IT type image sensor can be used. That is, the charge readout operation and the charge transfer operation in the vertical direction can be performed at the same timing as the IT method.
[0065]
Further, a transfer channel region (vertical transfer register) 3 is composed of first and second transfer channel regions 31 and 32, and these transfer channel regions 31 and 32 are provided on both sides of each light receiving section 2 in the corresponding column. Since they are arranged separately, the transfer electrodes 15a, 15b, 15c, and 15d used when transferring the signal charges 2 can be composed of two layers of electrode materials. Characteristics such as simplification, high sensitivity, and improvement of the smear suppression ratio can be obtained.
[0066]
Further, as shown in FIG. 3, when the second channel stop region 9 is formed continuously through the vertically adjacent channel stop region 9, the signal charge and the signal charge, the signal charge and Crosstalk of signal charges can be effectively prevented, and when a fixed potential is to be supplied to the channel stop region to adjust the height of the potential barrier, the supply end is led out of the image unit 4. Therefore, a wiring structure for supplying a fixed potential can be simplified.
[0067]
In the above-described embodiment (see FIG. 3), a channel stop region (first light receiving portion 2A and light receiving portion 2C, light receiving portion 2B and light receiving portion 2D in the example of FIG. 3) is provided between the light receiving portions 2 adjacent in the vertical direction. Although the configuration in which two channel stop regions 9) are continuously formed is shown, the channel stop region is removed only in the region between the light receiving units 2 adjacent in the vertical direction, and the channel stop region 9) is formed in the vertical direction. The CCD image sensor 111 can also be configured such that the channel stop regions 9 provided alternately on both sides of each of the light receiving units 2 are formed discontinuously.
[0068]
Here, in the configuration of the CCD image sensor 1 shown in FIG. 1, since the horizontal transfer of the signal charges is all performed in the same direction, the subsequent stage of each horizontal transfer register 5A, 5B, 5C, 5D. The output units 6A, 6B, 6C, and 6D provided on the side are all provided on one side (the left side in the example of FIG. 3). That is, the output units 6A, 6B, 6C, and 6D are provided concentrated on one side.
[0069]
However, when all of the output units 6A, 6B, 6C, and 6D are provided on one side of the horizontal transfer registers 5A, 5B, 5C, and 5D, in the CCD image sensor 1, the image unit 4 At one end, four horizontal transfer registers are provided. For example, at the time of horizontal transfer, the transfer of signal charges is concentrated on one side, and there is a possibility that that portion may become a heat source.
[0070]
Therefore, as shown in FIG. 8, in the four horizontal transfer registers 5A, 5B, 5C, and 5D, at least one pair of adjacent horizontal transfer registers (between the horizontal transfer registers 5C and 5A, between the horizontal transfer registers 5B and 5D). The CCD image sensor 111 is configured such that the output portions 6 (output portions 6C and 6A, output portions 6B and 6D) do not concentrate on one side by making the transfer directions of the signal charges in the directions opposite to each other. You can also.
[0071]
As described above, the configuration in which the transfer directions of the signal charges 2 in the adjacent horizontal transfer registers 5 are opposite to each other is, as shown in FIG. 9, between the adjacent horizontal transfer registers 5 (horizontal transfer registers 5C and 5A). The first horizontal transfer electrode 16 and the second horizontal transfer electrode 17 are formed to cross each other on the provided transfer gate 11 between horizontal transfer registers. At this time, the arrangement of the potential steps formed between the first horizontal transfer electrode 16 and the second horizontal transfer electrode 17 of the horizontal transfer register 5C and the horizontal transfer register 5A is based on the horizontal transfer register 5C and the horizontal transfer register 5A. The opposite is true.
[0072]
Thus, by applying the two-phase horizontal transfer pulses φH1 and φH2, the signal charge eC is shifted to one side (left side) in the horizontal transfer register 5C, and the signal charge eA is shifted to the other side (right side) in the horizontal transfer register 5A. And output from the output unit 6C and the output unit 6A provided in different directions.
[0073]
Therefore, in the case of such a configuration, in addition to the above-described functions and effects, it is possible to prevent the output units 6A, 6B, 6C, and 6D from being concentrated on one side, thereby suppressing heat generation.
In the illustrated example, the configuration on the horizontal transfer register transfer gate 11 provided between the horizontal transfer registers 5C and 5A is shown, but the horizontal transfer register transfer gate provided between the horizontal transfer registers 5B and 5D is shown. 11 has the same configuration as that of FIG.
[0074]
As shown in FIG. 10, for example, of the four horizontal transfer registers 5A, 5B, 5C, and 5D provided at one end of the image unit 4, the signal charges of the upper two horizontal transfer registers 5C and 5A are changed. The transfer direction and the transfer direction of the signal charges in the two lower horizontal transfer registers 5B and 5D may be opposite to each other.
[0075]
In this case, the horizontal transfer register transfer gate 11 (that is, the horizontal transfer register 5A and the horizontal transfer register 5B) provided between the upper two horizontal transfer registers 5C and 5A and the lower two horizontal transfer registers 5B and 5D. The first horizontal transfer electrode 16 and the second horizontal transfer electrode 17 may be crossed on the horizontal transfer register transfer gate 11) provided between the first horizontal transfer electrode 16 and the second horizontal transfer electrode 17 as shown in FIG.
[0076]
Thereby, the signal charges eA and eC can be transferred to one side (left side) in the horizontal transfer registers 5C and 5A, and the signal charges eB and eD can be transferred to the other side (right side) in the horizontal transfer registers 5B and 5D. The signal charges (eA and eC, eB and eD) can be output from the output units 6C and 6A and the output units 6B and 6D provided in different directions.
Therefore, similarly to the case described above, it is possible to prevent concentration of each of the output units 6A, 6B, 6C, and 6D on one side and to suppress heat generation.
[0077]
Next, another embodiment in which the solid-state imaging device according to the present invention is applied to an image sensor having a two-layer four-phase CCD structure will be described.
Parts corresponding to those in FIGS. 1 to 3 are denoted by the same reference numerals.
As shown in FIG. 11, the CCD image sensor 112 according to the present embodiment has a plurality of light receiving sections 2 serving as pixels arranged on the image section 4 in a matrix, as in the above-described embodiment. 2 has a color filter shown in FIG. 2 which is arranged in accordance with an arrangement rule of 2 vertical pixels × 2 horizontal pixels in correspondence with each light receiving section 2, and the image section 4 is shared by the light receiving sections 2 of each column. The vertical transfer register 3 is formed. The vertical transfer register 3 is formed of first and second vertical transfer registers 31 and 32, and the first and second vertical transfer registers 31 and 32 are separately disposed on both sides of the corresponding light receiving section 2, respectively. I have.
[0078]
As shown in FIG. 12, the image section 4 includes a transfer channel region (vertical transfer register) 3 formed by, for example, n-type impurity diffusion, which is a signal charge transfer path, in the vertical direction, as in the above-described embodiment. A large number are formed (for ease of explanation, the transfer channel regions are shown as 3, 33... Every other column in the illustrated example). Each of these transfer channel regions 3 (3, 33) has a first channel stop region 8 formed in the center portion thereof by, for example, p-type impurity diffusion extending in the vertical direction, and is separated left and right. . Also in the present embodiment, the transfer channel area on the left side is referred to as a first transfer area (first vertical transfer register) 31, and the transfer channel area on the right side is a second transfer channel area (second vertical transfer register). 32. When indicated collectively, the transfer channel area 3 is indicated.
Also in the present embodiment, of the four light receiving units 2A, 2B, 2C, and 2D corresponding to the colors R, Gr, Gb, and B, the upper two light receiving units 2A and 2B are odd-numbered rows, and the lower light receiving unit The sections 2C and 2D are assumed to be even rows.
[0079]
In the image unit 4, as in the above-described embodiment, of the light receiving units 2A and 2B for the odd rows, the light receiving unit 2A and the second transfer channel region 32 of the transfer channel region 33 adjacent to the left side in the drawing are connected. A second channel stop region 9 is formed between them, and a second channel stop region 9 is formed between the light receiving portion 2B and the first transfer channel region 31 of the transfer channel region 33 adjacent to the right side in the drawing. Have been.
A second channel stop region 9 is formed between the light receiving unit 2C and the first transfer channel region 31 of the transfer channel region 3 adjacent to the right side in the drawing among the light receiving units 2C and 2D for even rows. A second channel stop region 9 is formed between the light receiving portion 2D and the second transfer channel region 32 of the transfer channel region 3 adjacent on the left side in the drawing.
The second channel stop region 9 is also formed continuously between the light receiving units adjacent in the vertical direction (the light receiving units 2A and 2C and the light receiving units 2B and 2D in FIG. 12).
[0080]
Further, as in the case of the above-described embodiment, of the light receiving units 2A and 2B for the odd rows, the region between the light receiving unit 2A and the first transfer channel region 31 of the transfer channel region 3, and the light receiving unit 2B Readout gate portions 10A and 10B are formed in a region between the transfer channel region 3 and the second transfer channel region 32.
Further, of the light receiving units 2C and 2D related to the even rows, a region between the light receiving unit 2C and the second transfer channel region 32 of the transfer channel region 33, and a first transfer channel region of the light receiving unit 2D and the transfer channel region 33. Read gate portions 10C and 10D are formed in a region between the read gate portions 31 and 31.
[0081]
Therefore, as in the above-described embodiment, in the light receiving units 2 adjacent to each other on the left and right, the readout gate units 10 are formed to face each other, and the light receiving units adjacent to each other vertically (the light receiving units 2A and 2C in the example of FIG. In the sections 2B and 2D), the read gate section is formed with the direction inverted. As a result, it is possible to read out the signal charges stored in the light receiving units 2 adjacent to the right and left sides to the same vertical transfer register 3.
[0082]
With this configuration, also in the present embodiment, each color R, R2 stored in each of the light receiving units 2A, 2B, 2C, and 2D corresponding to a color filter having an arrangement rule of 2 vertical pixels × 2 horizontal pixels. The signal charges eA, eB, eC, and eD corresponding to Gr, Gb, and B can be color-separated and read independently through the read gate units 1010A, 10B, 10C, and 10D.
[0083]
In the present embodiment, one end (upper side) of the vertical transfer register 3 has two light receiving units 2A, 2B, 2C, and 2D corresponding to the four pixels of the above-described arrangement rule and two light receiving units in the odd-numbered rows. Two horizontal transfer registers 5A and 5B for independently transferring the signal charges eA and eB accumulated in the sections 2A and 2B are provided, and the other end (lower side) of the vertical transfer register 33 is provided according to the above-described arrangement rule. Two horizontal transfer registers 5C and 5D for independently transferring the signal charges eC and eD stored in the two light-receiving units 2C and 2D of the even-numbered rows among the corresponding four light-receiving units are provided. Output sections 6A, 6B, 6C and 6D for outputting signal charges eA, eB, eC and eD are provided at the subsequent stage of 5A, 5B, 5C and 5D, respectively.
That is, in the present embodiment, instead of transferring signal charges in one direction (downward) as in the above-described embodiment, signal charges are transferred upward and downward, respectively.
[0084]
As described above, when two horizontal transfer registers 5A, 5B, 5C, and 5D are provided at one end and the other end with the image unit 4 interposed therebetween, the horizontal transfer registers 5A, 5B, 5C, and 5D are provided in common to the light receiving units 2 in each column. The transfer direction of the signal charge is reversed in every other column of the vertical transfer register (transfer channel region) 3.
[0085]
That is, as described above, four vertical transfer electrodes (for example, two polycrystalline silicon layers) are formed in common on each transfer channel region 3, that is, on the first and second transfer channel regions 31 and 32. Although the first to fourth vertical transfer electrodes 15a to 15d) are set as one set and a large number of the sets are sequentially arranged in the vertical direction, in the present embodiment, every other row of the vertical transfer register (transfer channel region) 3 Each of the vertical transfer electrodes 15a to 15d is configured to be inverted upside down.
[0086]
More specifically, the first vertical transfer electrode 15a has its electrode portion (portion along the vertical transfer register) on the vertical transfer register (transfer channel region) 3 whose signal charge transfer direction is set to be upward. Are formed to extend to the lower side in the figure, and on the vertical transfer register (transfer channel region) 33 in which the transfer direction of the signal charge is set to the lower side, the electrode portion (the portion along the vertical transfer register) is located at the upper side in the figure It is formed to extend.
[0087]
On the vertical transfer electrode (transfer channel region) 3 in which the transfer direction of the signal charge is set upward, the second vertical transfer electrode 15b has its electrode portion (the portion along the vertical transfer register) in the upper part of the figure. On the vertical transfer register (transfer channel region) 33 in which the signal charge transfer direction is downward, the electrode portion (the portion along the vertical transfer register) extends downward in the figure. Have been.
[0088]
In the third vertical transfer electrode 15c, the electrode portion (the portion along the vertical transfer register) on the vertical transfer electrode (transfer channel region) 3 in which the transfer direction of the signal charge is set upward is lower in the figure. On the vertical transfer register (transfer channel region) 33 formed so as to extend to the side and the signal charge transfer direction is set downward, the electrode portion (portion along the vertical transfer register) extends upward in the drawing. Have been.
[0089]
On the vertical transfer electrode (transfer channel region) 3 in which the signal charge transfer direction is set upward, the fourth vertical transfer electrode 15d is such that its electrode portion (the portion along the vertical transfer register) is on the upper side in the figure. On the vertical transfer register (transfer channel region) 33 formed so as to extend downward and the signal charge transfer direction is set downward, the electrode portion (portion along the vertical transfer channel region) extends downward in the drawing. Is formed.
In the present embodiment, by configuring each of the vertical transfer electrodes (15a to 15d) as described above, each of the readout gate units 10A, 10B, 10C, and 10D in the four light receiving units 2A, 2B, 2C, and 2D is configured as a It is arranged below one vertical transfer electrode 15a.
[0090]
Next, the actual operation of the CCD image sensor according to the present embodiment will be described with reference to FIGS.
First, a charge reading operation for reading signal charges from the light receiving unit will be described with reference to a timing chart of FIG. 13A and an operation conceptual diagram of FIG.
FIG. 14A shows the charge reading operation of the light receiving unit 2C (2D) for the even-numbered rows, and FIG. 14B shows the charge reading operation of the light receiving unit 2A (2B) for the odd-numbered rows.
First, at time t0 immediately before reading in FIG. 13A, the first vertical transfer pulse φV1 applied to the first vertical transfer electrode 15a is at a high level (for example, 0 V), and the second, third, and fourth vertical transfer electrodes Since the second, third, and fourth vertical transfer pulses applied to 15b, 15c, and 15d are at a low level (for example, 9 V), the first and second transfer channel regions 3 and 33, a potential well is formed in a region below the first vertical transfer electrode 15a.
At this time, since the potential step below the first vertical transfer electrode 15a is located at a position shallower than the potential steps of the light receiving sections 22A, 2B, 2C, 2D, the signal charges eA, eB of the light receiving sections 22A, 2B, 2C, 2D. , EC and eD do not flow.
[0091]
At the next time t1, the first vertical transfer pulse φV1 becomes the read level (for example, 15 V), so that the potential well below the first vertical transfer electrode 15a is higher than the potential step of the light receiving sections 2A, 2B, 2C, and 2D. Get deeper. As a result, the signal charges eA and eB stored in the light receiving units 2A and 2B for the odd-numbered rows are transferred to the transfer channel region 3 that communicates with the horizontal transfer registers 5A and 5B disposed above, respectively. Is transferred and accumulated in a potential well formed below the first vertical transfer electrode 15a in the transfer channel region 31, and the signal charge eB is formed below the first vertical transfer electrode 15a in the second transfer channel region 32. Transferred and accumulated in the potential well.
The signal charges eC and eD stored in the light receiving units 2C and 2D for the even-numbered rows are transferred to the transfer channel regions 3 communicating with the lower horizontal transfer registers 5C and 5D, respectively. The signal charge eD is transferred and accumulated in a potential well formed under the first vertical transfer electrode 15a in the transfer channel region 32, and the signal charge eD is transferred under the potential formed under the first vertical transfer electrode 15a in the first transfer channel region 31. Transferred and stored in the well.
[0092]
Next, at time t2, the first vertical transfer pulse φV1 returns to the original high level (0 V), so that the first vertical transfer in the first and second transfer channel regions 31 and 32 of the transfer channel region 3 is performed. The signal charges eA and eB accumulated under the electrode 15a still remain below the first vertical transfer electrode 15a, and the first and second signal charges eA and eB in the second and first transfer channel regions 32 and 31 of the transfer channel region 33. The signal charges eC and eD accumulated under the vertical transfer electrode 15a of the first vertical transfer electrode 15a still remain under the first vertical transfer electrode 15a.
[0093]
As described above, in the present embodiment, the read gate units 10A, 10B, 10C, and 10D of the four light receiving units 2A, 2B, 2C, and 2D are arranged below the first vertical transfer electrode 15a. Therefore, the application of one vertical transfer pulse φV1 to the first vertical transfer electrode 15a corresponds to each color R, Gr, Gb, B stored in each of the light receiving sections 2A, 2B, 2C, 2D. The signal charges eA, eB, eC, and eD can be read.
[0094]
Next, a vertical transfer operation (a transfer operation along a vertical transfer register) in the image sensor 112 according to the present embodiment will be described with reference to a timing chart of FIG. 13B and conceptual diagrams of operations of FIGS. 15 and 16. .
FIG. 15 shows the vertical transfer operation of the signal charges stored in the light receiving section 2C (2D) for the even rows, and FIG. 16 shows the vertical transfer of the signal charges stored in the light receiving section 2A (2B) for the odd rows. The operation is shown.
First, after the end of the charge read operation shown in FIG. 14, first vertical transfer of the signal charges eA and eB in the first and second transfer channel regions 31 and 32 of the transfer channel region 3 in which the transfer direction is upward. The signal charges eC and eD are transferred and accumulated in the potential well formed below the electrode 15a, and the signal charges eC and eD are transferred to the first vertical direction in the second and first transfer channel regions 32 and 31 of the transfer channel region 33 whose transfer direction is downward. A description will be given of a state (t11) of transfer and accumulation in the potential well formed below the transfer electrode 15a.
[0095]
At the next time t12, since the fourth vertical transfer pulse φV4 becomes high level, a potential well is formed below the fourth vertical transfer electrode 15d, whereby the signal charges eA and eB are transferred to the transfer channel region 3d. Are transferred and accumulated in potential wells continuously formed under the first and fourth vertical transfer electrodes 15a and 15d in the first and second transfer channel regions 31 and 32, and the signal charges eC and eD are transferred to the transfer channel regions. 33 is transferred and accumulated in a potential well formed continuously below the second and first transfer channel regions 32 and 31.
[0096]
At the next time t13, since the first vertical transfer pulse φV1 becomes low level, a potential barrier is formed below the first vertical transfer electrode 15a, whereby the signal charges eA and eB are transferred to the transfer channel region 3a. Are transferred and accumulated in a potential well formed under the fourth vertical transfer electrode 15d in the first and second transfer channel regions 31 and 32, and the signal charges eC and eD are transferred to the second and third transfer channels in the transfer channel region 33. Data is transferred and accumulated in a potential well formed below the fourth vertical transfer electrode 15d in one of the transfer channel regions 32 and 31.
[0097]
At the next time t14, the third vertical transfer pulse φV3 becomes high level, so that a potential well is formed below the third vertical transfer electrode 15c, whereby the signal charges eA and eB are transferred to the transfer channel region 3c. Are transferred and accumulated in potential wells continuously formed under the third and fourth vertical transfer electrodes 15c and 15d in the first and second transfer channel regions 31 and 32, and the signal charges eC and eD are transferred to the transfer channel regions. In the 33 second and first transfer channel regions 32 and 31, transfer and accumulation are performed in potential wells continuously formed below the third and fourth vertical transfer electrodes 15 c and 15 d.
[0098]
At the next time t15, the fourth vertical transfer pulse φV4 becomes low level, so that a potential barrier is formed below the fourth vertical transfer electrode, whereby the signal charges eA and eB are transferred to the transfer channel region 3. The signal charges eC and eD are transferred and accumulated in the potential well formed below the third vertical transfer electrode 15c in the first and second transfer channel regions 31 and 32, and the signal charges eC and eD are transferred to the second and first transfer channels in the transfer channel region 33. Are transferred and accumulated in a potential well formed below the third vertical transfer electrode 15c in the transfer channel regions 32 and 31 of FIG.
[0099]
At the next time t16, since the second vertical transfer pulse goes high, a potential well is formed below the second vertical transfer electrode 15b, whereby the signal charges eA and eB are removed from the transfer channel region 3. The signal charges eC and eD are transferred and accumulated in potential wells formed continuously under the second and third vertical transfer electrodes 15b and 15c in the first and second transfer channel regions 31 and 32, and the signal charges eC and eD are transferred to the transfer channel region 33. Is transferred and accumulated in a potential well formed continuously below the second and third vertical transfer electrodes 15b and 15c in the second and first transfer channel regions 32 and 31 of FIG.
[0100]
At the next time t17, since the third vertical transfer pulse φV3 becomes low level, a potential barrier is formed below the third vertical transfer electrode 15c, whereby the signal charges eA and eB are transferred to the transfer channel region 3c. Are transferred and accumulated in a potential well formed under the second vertical transfer electrode 15b in the first and second transfer channel regions 31 and 32, and the signal charges eC and eD are transferred to the second and third transfer channel regions 33 and 32, respectively. Data is transferred and accumulated in a potential well formed under the second vertical transfer electrode 15b in one of the transfer channel regions 32 and 31.
[0101]
At the next time t18, the first vertical transfer pulse φV1 becomes high level, so that a potential well is formed below the first vertical transfer electrode 15a, whereby the signal charges eA and eB are transferred to the transfer channel region. 3, the signal charges eC and eD are transferred and accumulated in potential wells formed continuously below the first and second vertical transfer electrodes 15a and 15b in the first and second transfer channel regions 31 and 32. In the second and first transfer channel regions 32 and 31 of the region 33, the transfer and accumulation are performed in the potential wells continuously formed under the first and second vertical transfer electrodes 15a and 15b.
[0102]
At the next time t19, since the second vertical transfer pulse φV2 becomes low level, a potential barrier is formed below the second vertical transfer electrode 15b, whereby the signal charges eA and eB are transferred to the transfer channel region. The signal charges eC and eD are transferred and accumulated in a potential well formed below the first vertical transfer electrode 15a in the first and second transfer channel regions 31 and 32 of the third transfer channel region 31 and 32. Data is transferred and accumulated in a potential well formed under the first vertical transfer electrode 15a in the first transfer channel regions 32 and 31.
[0103]
At this stage, the signal charges eA and eB accumulated in the potential well formed under the first vertical transfer electrode 15a in the first and second transfer regions 31 and 32 of the transfer channel region 3 at the previous stage, respectively. Is transferred and accumulated in a potential well formed under the first vertical transfer electrode 15a in the first and second transfer channel regions 31 and 32 of the transfer channel region 3 in the next stage.
In the preceding stage, the signal charges eC and eD accumulated in the potential wells formed under the first vertical transfer electrodes 15a in the second and first transfer channel regions 32 and 31 of the transfer channel region 33 are respectively Data is transferred and accumulated in a potential well formed below the first vertical transfer electrode 15a in the second and first transfer channel regions 32 and 31 of the transfer channel region 33 in the next stage.
[0104]
As described above, the first to fourth vertical transfer pulses φV1 to φV4 are applied to the respective vertical transfer electrodes 15 (15a to 15d) at the timing shown in FIG. The signal charges eA, eB, eC, and eD read to the region 3 (31, 32) are the same as the signal charges eA and eB for the odd-numbered rows, respectively, while the first and second transfer channels of the channel region 3 remain independent. The signal charges eC and eD for the even-numbered rows are transferred upward in the regions 31 and 32, respectively, and are directed downward in the second and first transfer channel regions 32 and 31 of the channel region 33, respectively, independently. Will be transferred.
[0105]
That is, the signal charges eA and eB corresponding to the respective colors of R and Gr accumulated in the light receiving units 2A and 2B sequentially go upward in the first and second transfer channel regions 31 and 32 of the transfer channel region 3, respectively. And the signal charges eC and eD corresponding to the respective colors of Gb and B accumulated in the light receiving sections 2C and 2D sequentially and vertically in the second and first transfer channel regions 32 and 31 of the transfer channel region 33, respectively. It is transferred downward.
[0106]
The signal charges eA, eB, eC, and eD corresponding to the respective colors R, Gr, Gb, and B transferred independently from the transfer channel regions 3 (31, 32) are respectively transferred to the respective transfer channel regions 3 (31, 32). , 32) are transferred to the horizontal transfer registers 5A, 5B, 5C, 5D respectively arranged at one end of the horizontal transfer registers.
That is, the signal charges eA transferred in the first transfer channel 31 of the transfer channel region 3 are transferred to the horizontal transfer register 5A, and the signal charges eB transferred in the second transfer channel region 32 of the transfer channel region 3 are transferred to the horizontal transfer register 5A. The data is transferred to the horizontal transfer register 5B. The signal charge eC transferred in the second transfer channel region 32 of the transfer channel region 33 is transferred to the horizontal transfer register 5C by the signal charge eD transferred in the first transfer channel region 31 of the transfer channel region 33. Is transferred to the horizontal transfer register 5D.
[0107]
The signal charges eA, eB, eC, and eD corresponding to the colors R, Gr, Gb, and B transferred to the horizontal transfer registers 5A, 5B, 5C, and 5D are, for example, horizontally formed by two polycrystalline silicon layers. By applying two-phase horizontal transfer pulses φH1 and φH2 having different phases to transfer electrodes (not shown), the horizontal transfer registers 5A, 5B, 5C, and 5D are sequentially transferred in the horizontal direction, respectively. Each of the output units 6A, 6B, 6C, 6D provided at the subsequent stage of the registers 5A, 5B, 5C, 5D is converted into an electric signal, and is taken out as an image signal from the output unit 6A, 6B, 6C, 6D. .
That is, also in the present embodiment, four signal charges 2eA, eB, eC, and eD corresponding to the respective colors R, Gr, Gb, and B can be simultaneously color-separated and output by one horizontal transfer operation.
[0108]
Here, in the present embodiment, the transfer direction of the signal charges eA, eB, eC, and eD is reversed in every other column of the vertical transfer register 3 (the transfer direction in the vertical transfer register 3 is upward. In the horizontal transfer registers 5A, 5B, 5C, and 5D, the vertical transfer register 33 transfers the signal charges eA, eB, eC, and eD from the vertical transfer register 3 (packet). A portion (packet) not to be formed is formed alternately.
[0109]
That is, in the horizontal transfer registers 5A, 5B, 5C, and 5D, the signal charges eA, eB, eC, and eD are transferred only every other packet. After transferring the signal charges for one horizontal line (for example, the signal charges eA and eB in the odd-numbered rows) to the transfer register 5, each horizontal transfer register 5 is horizontally transferred by one bit, so that the signal is transferred below the vertical transfer register 3. Is a so-called empty packet in which no signal charge is transferred, and the next one horizontal line of signal charges (for example, signal charges eC and eD of even-numbered rows) are further transferred from the vertical transfer register 3 to this empty packet. Can be transferred.
[0110]
Therefore, signal charges (eA and eB, eC and eD) for two horizontal lines can be transferred from each vertical transfer register 3 into each horizontal transfer register 5, and a total of four lines can be transferred by one horizontal transfer. Can be output. As a result, it is possible to obtain a frame rate approximately four times as high as that of the conventional solid-state imaging device using the previous pixel readout method at the same driving frequency (this multiple changes depending on the horizontal blanking period).
[0111]
As described above, in the CCD image sensor 112 according to the present embodiment, similarly to the above-described embodiment, the color filter of the arrangement rule of 2 × 2 pixels formed on the image unit 4 is used. The signal charges eA, eB, eC, and eD accumulated in the light receiving units 2A, 2B, 2C, and 2D corresponding to the colors R, Gr, Gb, and B of FIG. The data can be independently read out to the vertical transfer register 31 and the second vertical transfer register 32).
[0112]
In addition, the signal charges eA, eB, eC, and eD corresponding to the colors R, Gr, Gb, and B, which are read independently, are respectively independently transferred to the vertical transfer registers 3 (the first vertical transfer register 31 and the first vertical transfer register 31). 2) in the vertical transfer register 32).
[0113]
Further, one horizontal transfer register 5 (5A, 5B, 5C and 5D in the present embodiment) is provided for one light receiving unit 2 (four light receiving units 2A, 2B, 2C and 2D in the present embodiment). As a result, the signal charges eA, eB, eC, and eD accumulated in each light receiving unit 2 are output in one unit, and the signal charges eA, eB corresponding to each of the colors R, Gr, Gb, and B are output. , EC, and eD, the output amplifier gain level can be adjusted during the signal processing, and the output amplifier gain level can be easily adjusted.
In addition, since it is possible to arbitrarily set the output amplifier gain level for each of the colors R, Gr, Gb, and B, the output amplifier gain level can be arbitrarily adjusted by, for example, a signal processing circuit provided at a subsequent stage. It can be set.
[0114]
Further, since the horizontal transfer register 5 has a configuration in which packets to which the signal charges eA, eB, eC, and eD are transferred from the vertical transfer register 3 and packets not to be transferred are formed alternately, as described above, one transfer is performed. By the horizontal transfer, signal charges for a total of four lines can be output. As a result, it is possible to obtain a frame rate approximately four times as high as that of the conventional solid-state imaging device using the previous pixel readout method at the same driving frequency (this multiple changes depending on the horizontal blanking period).
[0115]
Although the output units 6A, 6B, 6C, and 6D are different for each of the light receiving units 2A, 2B, 2C, and 2D, even if a deviation of the output amplifier gain level occurs between the output units 6, the deviation of the output amplifier gain is obtained. Is generated for each of the light receiving sections 2A, 2B, 2C, and 2D, so that it does not become a linear defect and becomes a dot, making it less noticeable.
[0116]
Further, also in the CCD image sensor 1 according to the present embodiment, it is possible to use the same timing of the charge reading operation and the timing of the charge transfer operation in the vertical direction as in the ordinary IT type image sensor. That is, the charge readout operation and the charge transfer operation in the vertical direction can be performed at the same timing as the IT method.
[0117]
Further, a transfer channel region (vertical transfer register) 3 is composed of first and second transfer channel regions 31 and 32, and these transfer channel regions 31 and 32 are provided on both sides of each light receiving section 2 in the corresponding column. The transfer electrodes (15 a, 15 b, 15 c, and 15 d) used for transferring the signal charges 2 can be composed of two layers of electrode materials because they are arranged separately. Characteristics such as simplification of the structure, high sensitivity, and improvement of the smear suppression ratio can be obtained.
[0118]
When the second channel stop region 9 is formed continuously through the vertically adjacent channel stop regions as shown in FIG. 12, the signal charge and the signal charge, the signal charge and Crosstalk of signal charges can be effectively prevented, and when a fixed potential is to be supplied to the channel stop region to adjust the height of the potential barrier, the supply end is led out of the image unit 4. Therefore, a wiring structure for supplying a fixed potential can be simplified.
[0119]
Here, in the present embodiment, two horizontal transfer registers 5 are provided above and below the image unit 4, respectively. Therefore, the horizontal transfer registers 5 are provided below the image unit 4 in the above-described embodiment. Compared to the case where four 5 are provided (see FIG. 1), the heat generation due to the concentration of the output unit 6 is suppressed. However, as described above, for example, between the adjacent horizontal transfer registers (the example in FIG. 12) The CCD image sensor 112 can be configured such that the transfer directions of the signal charges eA, eB, eC, and eD in the horizontal transfer registers 5A and 5B and the horizontal transfer registers 5C and 5D) are opposite to each other (see FIG. 17). .
The configuration of the other parts is the same as that of FIG. 11, and the same reference numerals are given and the duplicated description is omitted.
[0120]
In such a configuration, the first and second horizontal transfer electrodes 16 and 17 are arranged on the horizontal transfer register transfer gate 11 provided between the horizontal transfer registers 5A and 5B and the horizontal transfer registers 5C and 5D as shown in FIG. Can be achieved by the configuration shown in FIG.
[0121]
Thus, the horizontal transfer registers 5B and 5C transfer the signal charges eB and eC to one side (the left side in FIG. 17), and the horizontal transfer registers 5A and 5D transfer the signal charges eA and eD to the other side (the right side in FIG. 17). , And the signal charges eA, eB, eC, and eD can be output from output units (6B and 6C, output units 6A and 6D) provided in different directions.
Therefore, also in the present embodiment, in addition to the above-described functions and effects, heat generation can be suppressed by preventing concentration of each of the output units 6A, 6B, 6C, and 6D on one side.
[0122]
In the above-described embodiment, four horizontal transfer registers 5A, 5B, 5C, and 5D are provided as the horizontal transfer registers 5. However, in order to increase the frame rate, the number of horizontal transfer registers 5 is increased to eight, for example. Can be provided.
[0123]
It should be noted that the present invention is not limited to the above-described embodiment, and may take various other configurations without departing from the gist of the present invention.
[0124]
【The invention's effect】
According to the solid-state imaging device of the present invention, the signal charges accumulated in the four light receiving units corresponding to the four colors of the color filter having the arrangement rule of two vertical pixels × two horizontal pixels are color-separated and independently separated. Can output.
[0125]
As a result, pixel deterioration such as linear defects can be suppressed, and very high-precision and high-speed output amplifier gain level adjustment processing can be eliminated.
Further, even if a deviation of the output amplifier gain level occurs between the respective output units, the deviation does not become a linear defect but becomes a dot, so that it is less noticeable.
In addition, it is possible to adjust the difference between the output amplifier gain levels when processing the signal charge corresponding to each color. As described above, the output amplifier gain level for each color can be arbitrarily adjusted at a subsequent stage, so that the spectral characteristics can be arbitrarily adjusted.
Therefore, it is possible to provide a solid-state imaging device capable of easily adjusting the output amplifier gain level as compared with the related art.
[0126]
In addition, since signal charges accumulated in four light receiving units corresponding to four colors during one horizontal transfer can be color-separated and independently output, for example, a conventional all-pixel readout solid-state imaging device can be used. The frame rate can be increased in comparison.
When the transfer direction is reversed in every other column of the vertical transfer register, the frame rate can be further increased as compared with the conventional all-pixel readout solid-state imaging device.
[0127]
When the signal charges are transferred in at least one pair of adjacent horizontal transfer registers in opposite directions, heat generation due to concentration of the output unit can be suppressed.
[0128]
As described above, according to the present invention, it is possible to easily adjust the output amplifier gain level in the all-pixel readout type solid-state imaging device having the multi-channel output method, and further increase the number of pixels and increase the frame rate. It is possible to provide a solid-state imaging device that can respond to demands for realization.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing an embodiment in which a solid-state imaging device according to the present invention is applied to an image sensor having a two-layer four-phase CCD structure.
FIG. 2 is a diagram illustrating an example of a color filter provided on an image section of FIG. 1;
FIG. 3 is a schematic plan view illustrating a configuration of an image unit in FIG. 1;
FIG. 4 is a timing chart showing A and B read operations;
FIG. 5 is an operation conceptual diagram showing A and B read operations.
FIG. 6 is an operation conceptual diagram (part 1) illustrating a vertical transfer operation;
FIG. 7 is an operation conceptual diagram (part 2) illustrating a vertical transfer operation;
FIG. 8 is a schematic configuration diagram (part 1) showing a modification of FIG. 1;
FIG. 9 is a diagram showing a configuration of an electrode between adjacent horizontal transfer registers.
FIG. 10 is a schematic configuration diagram (part 2) showing a modification of FIG. 1;
FIG. 11 is a schematic configuration diagram showing another embodiment in which the solid-state imaging device according to the present invention is applied to an image sensor having a two-layer four-phase CCD structure.
FIG. 12 is a schematic plan view showing an image part of FIG. 11;
FIG. 13 is a timing chart showing A and B read operations.
FIG. 14 is an operation conceptual diagram showing A and B read operations.
FIG. 15 is a conceptual diagram (part 1) illustrating a vertical transfer operation.
FIG. 16 is a conceptual diagram (part 2) illustrating a vertical transfer operation.
FIG. 17 is a schematic configuration diagram showing a modification of FIG. 11;
FIG. 18 is a schematic configuration diagram (part 1) illustrating an example of a conventional CCD image sensor.
FIG. 19 is a schematic configuration diagram (part 2) illustrating an example of a conventional CCD image sensor.
FIG. 20 is a schematic configuration diagram (part 3) illustrating an example of a conventional CCD image sensor.
FIG. 21 is a schematic configuration diagram illustrating an example of a solid-state imaging device of an all-pixel readout method having a multi-channel output method.
[Explanation of symbols]
111, 112: CCD image sensor, 2, 2A, 2B, 2C, 2D: light receiving section, 3, 33: vertical transfer register (transfer channel area), 3: first transfer channel area , 32... Second transfer channel area, 4... Image part, 5A, 5B, 5C, 5D... Horizontal transfer register, 6A, 6B, 6C, 6D. Color filter, 11: transfer gate between horizontal transfer registers, eA, eB, eC, eD: signal charge, 16: first horizontal transfer electrode, 17: second horizontal transfer electrode

Claims (5)

On an image portion in which a large number of light receiving portions as pixels that photoelectrically convert into signal charges of an amount corresponding to the amount of incident light from a subject are arranged in a matrix, two vertical pixels × two horizontal pixels corresponding to each light receiving portion. A color filter arranged according to a pixel arrangement rule,
In the image section, a vertical transfer register is formed in common for the light receiving sections in each column,
The vertical transfer register is formed from first and second vertical transfer registers, and the first and second vertical transfer registers are separately disposed on both sides of a corresponding light receiving unit, respectively, and are provided at one end of the vertical transfer register. At least four horizontal transfer registers for independently transferring the signal charges read from the four light receiving units corresponding to the four pixels of the arrangement rule,
An output unit for outputting a signal charge is provided at a subsequent stage of each of the horizontal transfer registers. 2. The solid-state imaging device according to claim 1, wherein the signal charges are transferred in at least one pair of adjacent horizontal transfer registers in opposite directions. On an image portion in which a large number of light receiving portions as pixels that photoelectrically convert into signal charges of an amount corresponding to the amount of incident light from a subject are arranged in a matrix, two vertical pixels × two horizontal pixels corresponding to each light receiving portion. A color filter arranged according to a pixel arrangement rule,
In the image section, a vertical transfer register is formed in common for the light receiving sections in each column,
The vertical transfer register is formed from first and second vertical transfer registers, and the first and second vertical transfer registers are separately disposed on both sides of a corresponding light receiving unit, respectively, and are provided at one end of the vertical transfer register. Is provided with at least two horizontal transfer registers for independently transferring the signal charges accumulated in one of the four light receiving units corresponding to the four pixels of the arrangement rule, and the vertical transfer register At least two horizontal transfer registers for independently transferring signal charges accumulated in the other two light receiving units of the four light receiving units corresponding to the arrangement rule,
An output unit for outputting a signal charge is provided at a subsequent stage of each of the horizontal transfer registers. 4. The solid-state imaging device according to claim 3, wherein the signal transfer direction in the vertical transfer register is reversed every other column. 5. The solid-state imaging device according to claim 4, wherein the electrode portions of the vertical transfer electrodes provided on the vertical transfer register are formed upside down every other row.

Images