JP2004227486A - Semiconductor storage device equipped with high speed readout circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a readout circuit that reduces weight of bus cycles at a processor side and accelerates readout speed of the processor to a random accessible flash memory in a semiconductor memory device equipped with the memory. <P>SOLUTION: The readout circuit is provided with; an address decoder circuit, which inputs an address obtained by shifting an external address value to a low-order bit direction by one bit as the address signal of a first memory circuit, and which inputs an address obtained by shifting a value subtracting one from the external address value to the low-order bit direction by one bit as the address signal of a second memory circuit; and a control signal generation circuit, which activates an output validation signal sent out to one of the first and second memory circuits when the external address value is an even number, and which activates an output validation signal sent out to the other of the first and the other of the second memory circuit when the external address value is an odd number. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including a semiconductor memory such as a randomly accessible flash memory and a high-speed reading method thereof.
[0002]
[Prior art]
Semiconductor memories that can be randomly accessed by the processor include SRAM, DRAM, and flash memory. A non-volatile memory that is currently widely used is a flash memory, which is used for storing execution codes of processors and storing stored data.
[0003]
However, the flash memory has a lower access speed than the SRAM, and the processing speed of the entire processor may be limited to the slow access speed of the flash memory.
[0004]
FIG. 1 shows an example of a basic bus cycle of a processor. In FIG. 1, the memory is accessed once by using two basic clocks CLK of the processor. The low active (low_active) read enable signal RDX is activated (activated or enabled) at the falling timing of the first clock, and deactivated (deactivated or disabled) at the falling timing of the second clock.
[0005]
FIG. 2 shows an example in which a wait is inserted in the bus cycle of FIG. In FIG. 2, the memory is accessed once using the processor basic clock CLK by using two clocks and a wait for one clock. The low active (low_active) read enable signal RDX is activated at the falling timing of the first clock, and is deactivated at the falling timing of the second clock after the wait for one clock has elapsed.
[0006]
In the case of SRAM, access is possible even in the basic bus cycle as shown in FIG. 1, but in the case of flash memory, the response speed is slower than the basic clock CLK of the processor. Is not in time.
[0007]
In the example of FIG. 2, only a wait for one clock is included, but depending on the performance of the memory, a wait of two clocks or more may be required. For this reason, the reading speed is reduced by the amount of the inserted weight. For example, when the flash memory is used for storing the execution code of the processor, the processing speed is directly affected.
[0008]
As a conventional technique related to the present invention, Japanese Patent Application Laid-Open No. 5-250256 discloses parallel operation of a plurality of memory blocks and time-division switching control of an output validation control signal within one memory cycle. A memory access method for shortening the access time is shown.
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 5-250256
[Problems to be solved by the invention]
As described above, in the case of a conventional semiconductor memory device provided with a flash memory, the response speed is slower than the basic clock CLK of the processor, so that data output cannot be made without a wait as shown in FIG. However, if a wait is inserted in the bus cycle in accordance with the response speed of the flash memory, the speed at which the processor reads data from the memory is reduced by the inserted weight, which greatly affects the processing speed of the processor.
[0011]
The present invention has been made in view of the above points, and in a semiconductor memory device equipped with a randomly accessible flash memory, the number of bus cycles on the processor side is reduced, and the reading speed of the processor with respect to the memory is increased. An object of the present invention is to provide a readout circuit that performs the above.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problem, the invention described in claim 1 is directed to a first and second memory circuit that can be randomly accessed by a semiconductor memory device, and an external address value as an address signal to the first memory circuit. An address decoder circuit that outputs an address shifted by 1 bit in the bit direction and outputs an address obtained by subtracting 1 from an external address value by 1 bit in the lower bit direction as an address signal to the second memory circuit When the external address value is an even number, an output enable signal sent to one of the first and second memory circuits is activated, and when the external address value is an odd number, the first and second And a control signal generation circuit for activating an output enabling signal sent to the other of the two memory circuits.
[0013]
In order to solve the above problem, the invention described in claim 7 is such that when data is read from the first and second memory circuits that are randomly accessible, continuous addresses are continuously input as external addresses. A high-speed reading method for a semiconductor memory device enabling high-speed external access, wherein an address obtained by shifting an external address value by 1 bit in a lower bit direction is output as an address signal to the first memory circuit, and A procedure for outputting an address obtained by subtracting 1 from an external address value as an address signal to the second memory circuit by 1 bit in the lower bit direction; and when the external address value is an even number, When the output enable signal sent to one of the two memory circuits is activated and the external address value is an odd number, the first And having a procedure for the other activates the output enable signal is sent to the beauty second memory circuit.
[0014]
According to the semiconductor memory device and the high-speed read method of the present invention, by using an address decoder circuit and a control signal generation circuit, the bus cycle on the processor side is reduced and the memory access to the flash memory is accelerated at a relatively low cost. Is possible. Further, according to the semiconductor memory device and the high-speed read method of the present invention, it is possible to speed up the read cycle of the external bus to the limit of the data bus collision timing between the first and second flash memories.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
FIG. 3 shows the configuration of a high-speed read circuit according to an embodiment of the present invention.
[0017]
In the high-speed read circuit according to this embodiment, it is considered to increase only the read speed as a problem of the prior art. That is, it is assumed that the writing operation by the embedded application program or the like is not frequently performed. In such an application, it is considered that improving only the reading operation is sufficient to solve the above-described problem.
[0018]
As shown in FIG. 3, the semiconductor memory device 30 of this embodiment includes a first flash memory 33 and a second flash memory 34. In this embodiment, both the first flash memory 33 and the second flash memory 34 are randomly accessible flash memories. Further, the semiconductor memory device 30 of this embodiment is provided with an address decoder 31 and an output validation signal generation decoder 32.
[0019]
First, the configuration and operation of the address decoder 31 will be described, and the configuration and operation of the output validation signal generation decoder 32 will be described later.
[0020]
Address decoder 31, an address signal input from the outside _{(A n-1 ~A 0)} , the internal address _(A1 n-2 _{~A1 0)} of the first flash memory 33, the second flash memory 34 The decoded signal is output to the internal address (A2 _{n−2 to} A2 ₀ ).
[0021]
Here, assuming that the external address value inputted from the outside is A, the internal address of the first flash memory 33 is A1, and the internal address of the second flash memory 34 is A2, specifically, the address decoder 31 sends the first address. 1 address signal to the flash memory 33 is output as an address value A1 (A1 = A >> 1) obtained by shifting the external address value A by 1 bit in the lower bit direction. The address signal from the address decoder 31 to the second flash memory 34 is an address value A2 (A2 = (A-1) >> obtained by shifting the value obtained by subtracting 1 from the external address value A by 1 bit in the lower bit direction. 1) is output. Here, “>>” represents a bit shift in the lower direction.
In the semiconductor memory device 30 of this embodiment, when the continuous address is continuously input as the external address, the address decoder 31 includes the internal address of the first flash memory 33 and the internal address of the second flash memory 34. And a function of alternately designating.
[0022]
Here, FIG. 4 is a timing chart for explaining the operation of the high-speed read circuit of FIG. FIG. 5 shows an example of the address decoder 31 in the high-speed read circuit of FIG. In the example of FIG. 5, address signals (A _{n−1 to} A ₀ ) are input to the address decoder 31 from the outside. The address decoder 31 includes a plurality of OR circuits 11, 12, 13,. . . A plurality of XOR circuits 21, 22, 23,... Connected in parallel with the plurality of OR circuits. . . It consists of.
[0023]
Two adjacent bit lines (for example, A ₀ and A ₁ ) of the external address signal are connected to the input side of each OR circuit and each XOR circuit, respectively. The output of each OR circuit is connected to one input of the next-stage OR circuit and one input of the next-stage XOR circuit. Further, the output of each XOR circuit, respectively are connected to the bit line _A2 n-2 ~ A2 ₀ of the internal address signal of the second flash memory 34.
[0024]
If the address decoder 31 of FIG. 5, the bit line _{A n-1} to A ₁ of the external address signal, by respectively connected to the bit lines _A1 n-2 _{~A1 0} of the internal address signals in the first flash memory 33 The address signal from the address decoder 31 to the first flash memory 33 is output as an address value A1 obtained by shifting the external address value A by 1 bit in the lower bit direction.
[0025]
Furthermore, in the case of the address decoder 31 of FIG. 5, both two adjacent bit lines of the external address signal are connected to the inputs of each OR circuit and each XOR circuit, and the output of each OR circuit is connected to the OR circuit of the next stage. one input is connected to one input of the next stage XOR circuit, and is connected respectively to the output of the XOR circuit to the bit line A2 _n-2 ~ A2 ₀ of the internal address signal of the second flash memory 34 Thus, an address signal from the address decoder 31 to the second flash memory 34 is output as an address value A2 obtained by shifting the value obtained by subtracting 1 from the external address value A by 1 bit in the lower bit direction.
[0026]
Next, FIG. 7 shows an example of the output validation signal generation decoder 32 in the high-speed readout circuit of FIG. As shown in FIG. 7, the output validation signal generation decoder 32 includes an inverter 41, a first OR circuit 42, and a second OR circuit 43.
[0027]
On the input side of the output enable signal generation decoder 32, a signal A ₀ of the least significant bit of the address signal (A _{n−1 to} A ₀ ) input from the outside and a read enable signal RDX input from the outside. Supplied. The signal A _{0 of the} least significant bit is supplied to the input of the inverter 41 and is also supplied to one input of the first OR circuit 42. The output of the inverter 41 is connected to one input of the second OR circuit 43. The read enable signal RDX is supplied to the other input of the first OR circuit 42 and to the other input of the second OR circuit 43.
[0028]
The output enable signal generation decoder 32 configured as described above outputs the output enable signal / OE sent from the first OR circuit 42 to the first flash memory 33, and the second OR circuit 43 outputs the output enable signal / OE. Output enable signal / OE sent to the second flash memory 34 is output.
[0029]
FIG. 8 is a timing chart for explaining the operation of the output validation signal generation decoder 32 of FIG. As shown in FIG. 8, the read enable signal RDX input from the outside is always set to the enable state (LOW) during the read operation.
[0030]
After the read enable signal RDX is set to LOW, the after the elapse of a predetermined time, if the least significant bit A ₀ of the external address signal is 0 (even), the output enable signal generation decoder 32, the first The output enable signal / OE sent to the flash memory 33 is activated (transition from HIGH to LOW), and at the same time, the output enable signal / OE sent to the second flash memory 34 is deactivated (LOW). To HIGH).
[0031]
On the other hand, if the least significant bit A ₀ of the external address signal is 1 (odd number), the output enable signal / OE sent to the first flash memory 33 is inactivated (deactivated) by the output enable signal generation decoder 32 ( At the same time, the output enable signal / OE sent to the second flash memory 34 is activated (transition from HIGH to LOW).
[0032]
During the subsequent read operation, the high-speed read circuit of the semiconductor memory circuit of this embodiment shifts from the external address input cycle by about one cycle as long as consecutive addresses are continuously input as the external address, and the first flash memory 33. And the output of read data from either of the second flash memories 34 continue to be executed alternately. In this case, the weight of the bus cycle on the processor side can be reduced as compared with the prior art, thereby realizing high-speed data read processing.
[0033]
As shown in FIG. 4, in the semiconductor memory device of this embodiment, when continuous memory addresses are continuously input as external address signals, the internal addresses A1 of the first flash memory 33 and the second flash memory 34 are displayed. And A2 are alternately designated, and the output activation signal / OE sent to the flash memory on the side to which the internal address is designated are alternately activated, and the data read processing to the flash memory of the activated side chip Is executed.
[0034]
In the above description, the circuit configuration of the address decoder 31 is shown in FIG. 5, and the circuit configuration of the output activation signal generation decoder 32 is shown in FIG. 7. However, it is actually necessary to configure the circuit in consideration of timing.
[0035]
In the embodiment of FIG. 3, the delay control circuit 35 determines the delay time of the output enable signal / OE sent from the output enable signal generation decoder 32 to the first flash memory 33 and the second flash memory 34, respectively. As shown in the timing chart of FIG. The delay control circuit 35 can be configured using a conventionally known delay element.
[0036]
If the interval between the activation states of the output enable signal / OE sent from the output enable signal generation decoder 32 to the first and second flash memories 33 and 34 is too small due to the influence of external noise input or the like. There may be a collision between the data outputs from the data buses of the two flash memories. In order to prevent this, the delay control circuit 35 can be used to adjust the timing so that the data bus collision between the two internal flash memories does not occur.
[0037]
In the timing chart of FIG. 4, the activation of the output enable signal / OE sent to the first and second flash memories 33 and 34, respectively, with a slight delay from the rising timing of the clock CLK supplied from the processor side. Timing (falling) has occurred. This is because the delay time of the activation timing of the output enable signal / OE sent to the first and second flash memories 33 and 34 is adjusted by the action of the delay control circuit 35.
[0038]
In the semiconductor memory device of the above embodiment, high-speed access is realized by alternately accessing the two internal flash memories 33 and 34, and therefore, the access method needs to be devised. Specifically, the following processing is performed.
[0039]
First, with respect to reading of the first one word, the internal flash memories 33 and 34 each take a time corresponding to the conventional access cycle, and only when a continuous address is input thereafter, the internal flash memories 33 and 34 start from the external address input cycle. High-speed reading is realized with a shift of about a cycle. Therefore, it is assumed that the processor side accesses in consideration of them.
[0040]
Second, since the output activation signal / OE sent to the first flash memory 33 and the second flash memory 34 is generated and controlled internally, the row active read enable signal RDX inputted from the outside is controlled. Must always be in a read enable state (activated state) during reading.
[0041]
Third, for command processing such as writing and erasing, the chip enable signals CS1X and CS2X shown in FIG. 3 are controlled so that only one of the two flash memories 33 and 34 is in a chip enable state. Independently, command processing such as writing and erasing is performed. For example, the write command processing is performed by using the row active external write enable signal WRX shown in FIG.
[0042]
When performing command processing such as writing and erasing, the external address input value when accessing the first flash memory 33 in FIG. 3 is twice the actual address value A1 of the first flash memory 33. The external address input value when accessing the second flash memory 34 is set to a value that is twice the actual address value A2 of the second flash memory 34 plus one.
[0043]
FIG. 6 is a timing chart for explaining the operation when the high-speed read circuit of FIG. 3 is applied according to the actual electrical characteristics of the flash memory.
[0044]
In the example of FIG. 6, it is assumed that the read cycle time tRC of the flash memory according to the conventional method is 70 ns (10 ⁻⁹ seconds). As an actual electrical characteristic of this flash memory, the time tOE = 25 ns from the activation timing (falling) of the output enable signal / OE to the data output timing, and the inactivation timing (rising edge) of the output enable signal / OE. ) Until the output impedance of the flash memory reaches High-Z, tDF = 25 ns.
[0045]
In order to prevent a data bus collision between two internal flash memories, it is not possible to simply realize a double reading speed by the high-speed reading method according to the present invention. However, in the example of FIG. 6, by applying the high-speed read circuit of FIG. 3 to the flash memory having a response speed of tRC = 70 ns and accessing the two internal flash memories alternately, external access from the processor side , TRC can be increased to about 55 ns.
[0046]
As described above, according to the semiconductor memory device and the high-speed read method of the present embodiment, the read cycle of the external bus is limited to the collision timing of the data buses of both the first flash memory 33 and the second flash memory 34. It is possible to increase the speed.
[0047]
(Appendix 1)
Randomly accessible first and second memory circuits, an address obtained by shifting an external address value by one bit in the lower bit direction as an address signal to the first memory circuit, and the second memory circuit An address decoder circuit that outputs an address obtained by subtracting 1 from an external address value as an address signal to the lower bit direction, and the first and second memories when the external address value is an even number A control signal for activating an output enable signal sent to one of the circuits and activating an output enable signal sent to the other of the first and second memory circuits when the external address value is an odd number A semiconductor memory device comprising: a generation circuit.
[0048]
(Appendix 2)
The control signal generation circuit alternately activates output enable signals sent to the first and second memory circuits based on the least significant bit of the input external address signal and the input read enable signal. The semiconductor memory device according to appendix 1, wherein:
[0049]
(Appendix 3)
2. The semiconductor memory device according to claim 1, wherein when the data is read from the first and second memory circuits, continuous addresses are continuously input to the address decoder circuit as external addresses.
[0050]
(Appendix 4)
The control signal generation circuit receives a first logic circuit to which the least significant bit of the external address signal and the read enable signal are input, a signal obtained by inverting the least significant bit of the external address signal, and the read enable signal. The semiconductor memory device according to appendix 1, further comprising a second logic circuit.
[0051]
(Appendix 5)
The semiconductor memory device includes a delay control circuit that adjusts a delay time of an output enable signal sent from the control signal generation circuit to the first and second memory circuits, respectively. Semiconductor memory device.
[0052]
(Appendix 6)
The semiconductor memory device according to appendix 1, wherein both the first and second memory circuits are flash memories.
[0053]
(Appendix 7)
A high-speed reading method for a semiconductor memory device that enables high-speed external access by continuously inputting continuous addresses as external addresses when data is read from first and second memory circuits that are randomly accessible. An address obtained by shifting the external address value by 1 bit in the lower bit direction is output as an address signal to the first memory circuit, and 1 is subtracted from the external address value as an address signal to the second memory circuit. A procedure for outputting an address obtained by shifting the value by 1 bit in the lower bit direction; and, when the external address value is an even number, activates an output enable signal sent to one of the first and second memory circuits; When the external address value is an odd number, an output enable signal sent to the other of the first and second memory circuits is activated. Fast reading method of a semiconductor memory device characterized by having a procedure for reduction.
[0054]
(Appendix 8)
And a step of alternately activating output enable signals sent to the first and second memory circuits based on the least significant bit of the input external address signal and the input read enable signal. The high-speed reading method of the semiconductor memory device according to appendix 7, which is characterized in that
[0055]
(Appendix 9)
The activation procedure of the output enable signal includes a procedure for inputting the least significant bit of the external address signal and the read enable signal, a signal obtained by inverting the least significant bit of the external address signal, and the read enable signal. A method for high-speed reading of a semiconductor memory device according to appendix 7, wherein the method includes a procedure.
[0056]
(Appendix 10)
8. The semiconductor memory device high-speed reading method according to claim 7, further comprising a step of adjusting a delay time of the output enable signal sent to each of the first and second memory circuits.
[0057]
【The invention's effect】
As described above, according to the semiconductor memory device and the high-speed read method of the present invention, the number of wait cycles in the bus cycle on the processor side can be reduced at a relatively low cost by using the address decoder circuit and the output validation signal generation circuit. The memory access to the flash memory can be speeded up. Further, according to the semiconductor memory device and the high-speed read method of the present invention, it is possible to speed up the read cycle of the external bus to the limit of the data bus collision timing between the first and second flash memories.
[0058]
[Brief description of the drawings]
FIG. 1 is a timing diagram illustrating an example of a basic bus cycle of a processor.
FIG. 2 is a timing chart showing an example when one wait is inserted in the bus cycle of FIG. 1;
FIG. 3 is a block diagram showing a configuration of a high-speed read circuit according to an embodiment of the present invention.
4 is a timing chart for explaining the operation of the high-speed read circuit in FIG. 3;
5 is a circuit diagram showing an example of an address decoder in the high-speed read circuit of FIG. 3;
6 is a timing chart for explaining an operation when the high-speed read circuit of FIG. 3 is applied according to actual electrical characteristics of the flash memory.
7 is a circuit diagram showing an example of an output enable signal generation decoder in the high-speed read circuit of FIG. 3. FIG.
FIG. 8 is a timing diagram for explaining the operation of the output enable signal generation decoder of FIG. 7;
[Explanation of symbols]
30 Semiconductor Memory Device 31 Address Decoder 32 Output Enable Signal Generation Decoder 33 First Flash Memory 34 Second Flash Memory 35 Delay Control Circuit 41 Inverter 42 First OR Circuit 43 Second OR Circuit

Claims (8)

First and second randomly accessible memory circuits;
An address obtained by shifting an external address value by 1 bit in the lower bit direction as an address signal to the first memory circuit, and a value obtained by subtracting 1 from the external address value as an address signal to the second memory circuit An address decoder circuit that outputs an address shifted by 1 bit in the lower bit direction;
When the external address value is an even number, an output enable signal sent to one of the first and second memory circuits is activated, and when the external address value is an odd number, the first and second A semiconductor memory device comprising: a control signal generation circuit that activates an output enable signal sent to the other of the memory circuits. The control signal generation circuit alternately activates output enable signals sent to the first and second memory circuits based on the least significant bit of the input external address signal and the input read enable signal. 2. The semiconductor memory device according to claim 1, wherein: 2. The semiconductor memory device according to claim 1, wherein, when data is read from the first and second memory circuits, continuous addresses are continuously input to the address decoder circuit as external addresses. The control signal generation circuit receives a first logic circuit to which the least significant bit of the external address signal and the read enable signal are input, a signal obtained by inverting the least significant bit of the external address signal, and the read enable signal. The semiconductor memory device according to claim 1, further comprising a second logic circuit. 2. The semiconductor memory device according to claim 1, further comprising a delay control circuit that adjusts a delay time of an output enable signal sent from the control signal generation circuit to the first and second memory circuits. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein both the first and second memory circuits are flash memories. A high-speed reading method for a semiconductor memory device that enables high-speed external access by continuously inputting continuous addresses as external addresses when data is read from first and second memory circuits that are randomly accessible. ,
An address obtained by shifting an external address value by 1 bit in the lower bit direction as an address signal to the first memory circuit, and a value obtained by subtracting 1 from the external address value as an address signal to the second memory circuit To output an address shifted by 1 bit in the lower bit direction,
When the external address value is an even number, an output enable signal sent to one of the first and second memory circuits is activated, and when the external address value is an odd number, the first and second And a procedure for activating an output enable signal sent to the other of the memory circuits. And a step of alternately activating output enable signals sent to the first and second memory circuits based on the least significant bit of the input external address signal and the input read enable signal. 8. A high-speed reading method for a semiconductor memory device according to claim 7,

Images