JP2004220735A - Word line driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a word line driving method simple in circuit configuration and good in process efficiency. <P>SOLUTION: This method comprises: a step in which a voltage level of an input end of a level shift circuit is converted by converting a voltage level of a control end when a second circuit is turned on; and a step in which at least one voltage level is converted out of a first power source supply source and a second power source supply source and separating a voltage level of the control end and a voltage level of a word line by the second circuit. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a word line driving method, and more particularly to a word line driving method for driving a word line by a word line driver.
[0002]
[Prior art]
A flash memory is a non-volatile memory device and includes a floating gate electrode for storing electric charges and a control gate electrode for controlling the amount of electric charges stored in the floating gate electrode. Referring to FIGS. 1 and 2, FIG. 1 is an explanatory diagram showing functional blocks of a word line driver 10 according to the related art, and FIG. 2 is an explanatory diagram simply illustrating the word line driver 10 disclosed in FIG. It is. Prior art word line driver 10 is used to drive a voltage to word line 16. By connecting the word line 16 to the control gate electrode of the flash memory device, the word line driver 10 can write or erase data.
[0003]
The conventional word line driver 10 includes an address decoder 12, an isolating transistor N1, and a level shift circuit 14. An isolation transistor N1 is electrically connected between the address decoder 12 and the level shift circuit 14, and is used to isolate the address decoder 12 and the level shift circuit 14. A level shift circuit 14 is electrically connected to the word line 16 and is used for transmitting a voltage signal to the word line 16.
[0004]
For ease of explanation, under normal operation, a 3V voltage represents logic data "1" and a 0V voltage represents logic data "0" under normal operation. However, when writing or erasing the flash memory via word lines, different voltages need to be used. All voltages are provided from the plus word line power supply WLP and the minus word line power supply WLN. When the flash memory does not perform writing or erasing, the plus word line power supply WLP = 3V and the minus word line power supply WLN = 0V. However, it is necessary to use a high voltage of 10 V to erase the flash memory. Therefore, when performing the erase operation, the plus word line power supply WLP = 10V and the minus word line power supply WLN = 0V. On the other hand, when writing to the flash memory, it is necessary to use a high voltage of -10V, that is, when performing a write operation, the plus word line power supply WLP = 3V and the minus word line power supply WLN = -10V. The voltage values described above are examples taken up for ease of explanation, and the actual operating voltage is determined by the standard of each flash memory.
[0005]
The address decoder 12 is used to select a specific memory cell for writing or erasing data. When a specific memory cell to be subjected to a write operation is selected, the address decoder 12 outputs a 3V voltage to the word line driver 10 corresponding to the specific memory cell. At this time, the gate electrode 18 of the isolation transistor N1 is controlled to turn on the isolation transistor N1, and the 3V voltage can be passed. The 3V voltage subsequently turns on the transistor MN1, and the word line 16 receives the voltage of the minus word line power supply WLN. At the same time, the word line power supply providing the negative voltage is also changed to the minus word line power supply WLN = −10V. As a result, the word line 16 receives the voltage of -10 V, and data is written.
[0006]
When the word line driver 10 performs the erasing operation, it is the same as the method described above. In order to specify the position of the memory cell waiting for erasure, the address decoder 12 outputs a 0V voltage to the word line driver 10 corresponding to the specific memory cell. Similarly, the gate electrode 18 of the isolation transistor N1 is controlled to turn on the isolation transistor N1, so that the 0V voltage can be passed. The 0V voltage subsequently turns on the transistor MP1, and the word line 16 receives the voltage of the plus word line power supply WLP. At the same time, the word line power supply providing the positive voltage is also changed to the plus word line power supply WLP = 10V. As a result, the word line 16 receives the voltage of 10 V, and the data is erased.
[0007]
The plus word line power supply WLP and the minus word line power supply WLN according to the related art are electrically connected to a large number of memory cells. However, a problem occurs when the plus word line power supply WLP or the minus word line power supply WLN is switched from a general voltage value to a plus or minus high voltage value. Taking the write operation described above as an example, when the negative word line power supply WLN is switched to a negative high voltage of -10 V, this negative high voltage is applied not only to the memory cell being written but also to the negative word line power supply WLN. The data is transmitted to each connected memory cell. This transmits the high voltage value to be switched to the level shift circuit 14 and further transmits an inappropriate voltage value to the pin of the address decoder 12 corresponding to the memory cell not performing the write operation. Prior art isolation transistors N1 are used to protect the address decoder 12 because these inappropriate voltage values can destroy the address decoder 12. In order to pass the voltage value, each memory cell has an isolation transistor N1 that is selectively turned on or off. Each isolation transistor N1 is controlled by a voltage applied to the gate electrode 18 of the isolation transistor N1.
[0008]
However, the use of the isolation transistor N1 for each memory cell as in the prior art described above requires a huge number of isolation transistors N1, especially when a large array of memory cells is used. Is a problem. Further, the use of the isolation transistor N1 complicates the circuit layout of the memory and further complicates the manufacturing process.
[0009]
[Problems to be solved by the invention]
An object of the present invention is to provide a word line driving method which has a simple circuit structure and high process efficiency by not using an isolation transistor.
[0010]
[Means for Solving the Problems]
Accordingly, the present inventor has conducted intensive studies in view of the drawbacks found in the prior art, and as a result, provided a first circuit, a second circuit, and a control terminal provided between the first circuit and the second circuit. A first address decoder used to select a word line, a first power supply, a second power supply, connected to the first address decoder and the word line, and controlling a voltage level of the word line. A word line driver that is used for conversion and includes a level shift circuit that includes an input terminal connected to a second circuit of the first address decoder, and a control terminal of the control terminal when the second circuit is turned on. Converting a voltage level at an input terminal of the level shift circuit by converting a voltage level; and adjusting a voltage level of at least one of the first power supply source and the second power supply source. And that the second circuit isolates the voltage level of the control terminal from the voltage level of the word line. The present invention has been completed based on the findings. I let it.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention relates to a word line driving method, and more particularly to a method of driving a word line by a word line driver, comprising a first circuit, a second circuit, and a control terminal provided between the first circuit and the second circuit. A first address decoder used to select a word line, a first power supply, a second power supply, and a voltage level of the word line connected to the first address decoder and the word line. And a word line driver including a level shift circuit including an input terminal connected to the second circuit of the first address decoder, and the control terminal when the second circuit is turned on. Converting the voltage level of the input terminal of the level shift circuit by converting the voltage level of the first power supply source and the second power supply source. Converting at least one of the voltage level, the method comprising the steps of further isolating the voltage level of the said second circuit and the voltage level of the control end of the word lines, to form a method for driving a word line.
[0012]
In order to describe the method and characteristics of driving the word line in detail, a specific embodiment will be described below with reference to the drawings.
[0013]
【Example】
(First embodiment)
Referring to FIG. 3, FIG. 3 is an explanatory diagram showing functional blocks of the word line driver 30 according to the first embodiment of the present invention. The word line driver 30 includes a first address decoder 40 having a first circuit 32 and a second circuit 38, and the first circuit 32 and the second circuit 38 are used to select a word line WL. The second circuit 38 includes a PMOS transistor P2 and an NMOS transistor N2. The PMOS transistor P2 is connected to the second address decoder 34, and the NMOS transistor N2 is connected to the third address decoder 36.
[0014]
The word line driver 30 further includes a level shift circuit 42. The level shift circuit 42 is connected to the first power supply source WLP, the second power supply source WLN, the first address decoder 40, and the word line WL. Used to change the voltage level of WL. Changing the voltage level of the word line WL is because the word line driver 30 performs a data write operation or an erase operation on the flash memory cell FM. The word line WL is electrically connected to the control gate electrode 46 of the flash memory cell FM, or the word line driver 30 performs a write operation or an erase operation on the flash memory cell FM by controlling the word line WL. It is.
[0015]
The level shift circuit 42 is provided between the input terminal INP connected to the second circuit 38 of the first address decoder 40 and the input terminal INP of the level shift circuit 42 and the word line WL. It includes an input terminal INP and a latch circuit 44 electrically connected to the word line WL. Latch circuit 44 includes two inverters that function to invert the voltage level input to latch circuit 44. The level shift circuit 42 is further provided between the first power supply source WLP and the input terminal INP of the latch circuit 44, and is electrically connected to the first power supply source WLP and the input terminal INP of the latch circuit 44. A transistor P3, an NMOS transistor N3 provided between the second power supply source WLN and the input terminal INP of the latch circuit 44, and electrically connected to the second power supply source WLN and the input terminal INP of the latch circuit 44; including.
[0016]
The first address decoder 40 also has a control terminal BLKDECB provided between the first circuit 32 and the second circuit 38. To enable the word line driver 30 to drive the word line, first, while turning on the second circuit 38, the voltage level of the control terminal BLKDECB is changed, and the voltage of the input terminal INP of the level shift circuit 42 is changed. Change level. Further, the voltage level of the first power supply WLP and / or the second power supply WLN is also changed, and the second circuit 38 is used to isolate the voltage level of the control terminal BLKDECB from the voltage level of the word line. This voltage isolation function will be described in detail below.
[0017]
Each time the voltage of the input terminal INP of the level shift circuit 42 is changed, the latch circuit 44 is used to change the voltage level of the word line WL. Turning on the PMOS transistor P3 or the NMOS transistor N3 realizes that the input terminal INP of the latch circuit 44 is electrically connected to the first power supply source WLP or the second power supply source WLN.
[0018]
In order to more clearly explain the technique according to the invention, the following describes the data write and erase operations by giving several examples. For simplicity and to avoid confusion, the description of the present embodiment uses the voltage examples used in the description of the prior art. That is, when the flash memory does not perform a write operation or an erase operation, WLP = 3V and WLN = 0V. In order to erase data in the flash memory cell FM, a plus high voltage of 10 V is required. Therefore, when performing the erase operation, WLP = 10V and WLN = 0V. On the other hand, when writing data to the flash memory cell FM, a negative high voltage of -10 is required. Therefore, when performing a write operation, WLP = 3V and WLN = -10V.
[0019]
At the beginning of the erasing step, a low-active reset signal (RSTB) RSTB is maintained at RSV = 0V for a predetermined time, so that the input terminal INP obtains a 3V voltage. At this time, the reset signal RSTB can be switched to a voltage of 3V, and isolates the input terminal INP and the first power supply WLP. Subsequently, in order to select the memory cell FM waiting to be erased, a logic signal “0” is output from the first circuit 32, and the control terminal BLKDECB is set to 0V. Further, the second address decoder 34 outputs a 0V voltage and the third address decoder 36 outputs a 3V voltage or a voltage higher than 3V, so that the 0V voltage value of the control terminal BLKDECB is input to the input terminal INP of the latch circuit 44. Can be transmitted. On the other hand, a logic signal “1” is output from the first circuit 32 to the memory cell on which the erasing operation is not performed, the control terminal BLKDECB = 3V, and the input terminal INP of the latch circuit 44 is maintained at 3V.
[0020]
Similarly, at the beginning of the writing step, the input terminal INP obtains a voltage of 0 V by first maintaining the reset signal SET at 3 V for a predetermined time. At this time, the reset signal SET can be switched to 0V, and isolates the input terminal INP and the second power supply WLN. Then, in order to select the memory cell FM waiting for writing, the logic signal “1” is output from the first circuit 32, and the control terminal BLKDECB is set to 3V. Further, the second address decoder 34 outputs a 0V voltage and the third address decoder 36 outputs a 3V voltage or a voltage higher than 3V, so that the 3V voltage value of the control terminal BLKDECB is input to the input terminal INP of the latch circuit 44. Can be transmitted. On the other hand, the input terminal INP of the latch circuit 44 is maintained at 0 V for a memory cell on which no write operation is performed. When one of the following conditions is satisfied, the input terminal INP of the latch circuit 44 is maintained at 0V. The first condition is that the first circuit 32 outputs a 0V voltage. The second condition is that the output of the second address decoder 34 is a high voltage that turns off the PMOS transistor P2. The third condition is that the output of the third address decoder 36 is a low voltage that turns off the NMOS transistor N2.
[0021]
Referring to FIG. 4, FIG. 4 is a flowchart of steps for erasing data in the flash memory cell FM according to the present invention, and each step will be described below.
[0022]
Step 100: The erase operation is started.
[0023]
Step 102: An erasing operation is started on the flash memory cell FM by the reset signal RSTB = 0V. At this time, the voltage level of the input terminal INP of the level shift circuit 42 is increased to 3V which is the voltage level of the first power supply source WLP. , The voltage of the word line becomes 0V.
[0024]
Step 104: The first circuit 32 of the first address decoder 40 starts a normal decoding step, and since this is an erasing step, the first circuit 32 outputs a logic signal “0” and the control terminal BLKDECB = 0V, When the second address decoder 34 outputs 0V and the third address decoder 36 outputs 3V or a voltage higher than 3V, it becomes possible to transmit the 0V voltage of the control terminal BLKDECB to the input terminal INP of the latch circuit 44. After that, the latch circuit 44 inverts the 0V voltage, and the word line voltage becomes WL = 3V.
[0025]
Step 106: The level shift circuit 42 switches the voltage of the first power supply WLP from 3V to 10V. During this time, the second power supply source WLN is stably maintained at 0 V, and as a result of this voltage conversion, the word line voltage becomes WL = 10 V, and the data in the flash memory cell FM is erased.
[0026]
Step 108: Return the operation voltage to the initial state, that is, the level shift circuit 42 switches the voltage of the first power supply WLP from 10V to 3V, and the second power supply WLN is maintained at 0V, and this voltage is maintained. As a result of the conversion, the voltage of the word line becomes WL = 3 V, and thereafter, the process returns to step 102.
[0027]
Referring to FIG. 5, FIG. 5 is a flowchart of steps for writing data to the flash memory cell FM according to the present invention, and each step will be described below.
[0028]
Step 120: Write operation is started.
[0029]
Step 122: A write operation is started in the flash memory cell FM with a reset signal (high-active reset signal) SET = 3 V. At this time, the voltage level of the input terminal INP of the level shift circuit 42 is changed to the voltage of the second power supply source WLN. The voltage is reduced to the level of 0 V, and the voltage of the word line becomes 3 V.
[0030]
Step 124: The first circuit 32 of the first address decoder 40 starts a normal decoding step, and since this is a write step, the first circuit 32 outputs a logic signal “1”, and the control terminal BLKDECB = 3V, When the second address decoder 34 outputs 0V and the third address decoder 36 outputs 3V or a voltage higher than 3V, the 3V voltage of the control terminal BLKDECB can be transmitted to the input terminal INP of the latch circuit 44. After that, the latch circuit 44 inverts the 3V voltage, and the word line voltage WL becomes 0V.
[0031]
Step 126: The level shift circuit 42 switches the voltage of the first power supply WLP from 3V to 0V, and at the same time, the second power supply WLN goes from 0V to -10V, and as a result of this voltage conversion, The voltage becomes WL = −10 V, and data is written to the flash memory cell FM.
[0032]
Step 128: Return the operation voltage to the initial state, that is, the level shift circuit 42 switches the voltage of the first power supply WLP from 0V to 3V, and the second power supply WLN returns from -10V to 0V, As a result of the voltage conversion, the voltage of the word line becomes WL = 0 V, and thereafter, the process returns to step 122.
[0033]
To effectively protect the first circuit 32, the PMOS transistor P2 and the NMOS transistor N2 in the second circuit 38 are used to isolate the voltage level of the control terminal BLKDECB and the voltage level of the input terminal INP. . As an example, suppose that a voltage value of 0 V is applied to the gate electrode of the PMOS transistor P2 and a voltage value of 3 V or higher than 3 V is applied to the gate electrode of the NMOS transistor N2. And the gate electrode of the NMOS transistor N2, the first circuit 32 can be effectively protected without being destroyed by the plus or minus high voltage used in the level shift circuit 42. it can.
[0034]
For example, assume that input end INP has a voltage of -10V. In this case, since the gate electrode of the NMOS transistor N2 can apply a voltage of 3V or a voltage value higher than 3V, the -10V voltage can reach the contact point K via the NMOS transistor N2. However, since the 0V voltage value is applied to the gate electrode of the PMOS transistor P2, the -10V voltage cannot reach the control terminal BLKDECB via the PMOS transistor P2. Similarly, assume that input INP has a 10V voltage. In this case, since the gate electrode of the NMOS transistor N2 can apply a voltage of 3V or a voltage value higher than 3V, the 10V voltage cannot reach the contact K via the NMOS transistor N2. Therefore, in the two states described above, the first circuit 32 is not destroyed by the plus or minus high voltage used in the level shift circuit 42. Further, while the first circuit 32 is protected from positive or negative high voltage, the PMOS transistor P2 and the NMOS transistor N2 can pass normal 0V voltage and 3V voltage.
[0035]
(Second embodiment)
In the present invention, other modifications of the word line driver 30 are possible besides the word line driver 30 shown in FIG. Referring to FIG. 6, FIG. 6 is an explanatory diagram showing functional blocks of a word line driver 230 according to the second embodiment of the present invention. The word line driver 230 is similar to the word line driver 30 shown in FIG. The only difference is that the positions of the PMOS transistor P2 and the NMOS transistor N2 in the second circuit 38 are reversed. The NMOS transistor N2 of the word line driver 230 is connected to the second address decoder 34, and the PMOS transistor P2 is connected to the third address decoder 36.
[0036]
(Third embodiment)
FIG. 7 is an explanatory diagram showing functional blocks of the word line driver 330 according to the third embodiment of the present invention. The word line driver 330 is similar to the word line driver 30 shown in FIG. The only difference is that the word line driver 330 does not include the PMOS transistor P3 and the NMOS transistor N3 in the level shift circuit 42. Rather than the reset signal RSTB controlling the PMOS transistor P3 and the reset signal SET controlling the NMOS transistor N3, the first circuit 32 of the word line driver 330 replaces the PMOS transistor P3 and the NMOS transistor N3 and replaces these transistors. A function can be performed, which reduces the complexity of the word line driver 330.
[0037]
(Fourth embodiment)
FIG. 8 is an explanatory diagram showing functional blocks of the word line driver 430 of the fourth embodiment according to the present invention. Word line driver 430 is similar to word line driver 30 shown in FIG. The only difference is that the word line driver 430 does not include the PMOS transistor P3 in the level shift circuit 42. Rather than the reset signal RSTB controlling the PMOS transistor P3, the first circuit 32 of the word line driver 430 can perform the same function of the PMOS transistor P3 instead of the PMOS transistor P3, so that the word line driver 430 Complexity is reduced.
[0038]
(Fifth embodiment)
FIG. 9 is an explanatory diagram showing functional blocks of a word line driver 530 of the fifth embodiment according to the present invention. Word line driver 530 is similar to word line driver 30 shown in FIG. The only difference is that the word line driver 530 does not include the NMOS transistor N3 in the level shift circuit 42. Rather than the reset signal SET controlling the NMOS transistor N3, the first circuit 32 of the word line driver 530 can perform the same function of the NMOS transistor N3 instead of the NMOS transistor N3, so that the word line driver 530 Complexity is reduced.
[0039]
The above is a preferred embodiment of the present invention, and does not limit the scope of the present invention. Therefore, any modifications or changes that can be made by those skilled in the art, which are made in the spirit of the present invention and which have an equivalent effect on the present invention, fall within the scope of the claims of the present invention. Shall be.
[0040]
【The invention's effect】
Compared with the prior art, the word line driver 30, 230, 330, 430, 530 according to the present invention does not require the isolation transistor N1 of the word line driver 10 according to the prior art. Instead, the word line driver 30, 230, 330, 430, 530 according to the present invention uses the output of the second address decoder 34 and the third address decoder 36 to form the isolation transistor N1 of the word line driver 10 according to the prior art. Perform similar functions. Further, the first address decoder 40, the second address decoder 34 and the third address decoder 36 shown in FIGS. 3, 6, 7, 8 and 9 correspond to the address decoder 12 shown in FIGS. Is similar to In other words, the address decoders 34, 36, 40 according to the present invention can replace the address decoder 12 and the isolation transistor N1 according to the prior art without adding new circuits. This means that the PMOS transistor P2 and the NMOS transistor N2 are selectively used by using the outputs of the second address decoder 34 and the third address decoder 36 to isolate the voltage level of the control terminal BLKDECB from the voltage level of the word line WL. It is achieved by turning it on or off.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing functional blocks of a word line driver according to a conventional technique.
FIG. 2 is a diagram schematically illustrating the word line driver disclosed in FIG. 1;
FIG. 3 is an explanatory diagram showing functional blocks of a word line driver according to the first embodiment of the present invention.
FIG. 4 is a flow chart of steps for erasing data in a flash memory cell according to the present invention.
FIG. 5 is a flowchart of steps for writing data to a flash memory cell according to the present invention.
FIG. 6 is an explanatory diagram showing functional blocks of a word line driver according to a second embodiment of the present invention.
FIG. 7 is an explanatory diagram showing functional blocks of a word line driver according to a third embodiment of the present invention.
FIG. 8 is an explanatory diagram showing functional blocks of a word line driver according to a fourth embodiment of the present invention.
FIG. 9 is an explanatory diagram showing functional blocks of a word line driver according to a fifth embodiment of the present invention.
[Explanation of symbols]
10 Word line driver
12 Address decoder
14 Level shift circuit
16 word lines
18 Gate electrode
30 word line driver
32 First circuit
34 Second address decoder
36 Third address decoder
38 Second circuit
40 First Address Decoder
42 Level shift circuit
44 Latch circuit
230 word line driver
330 word line driver
430 word line driver
530 word line driver
N1 isolation transistor
N2, N3, MN1 NMOS transistors
P2, P3, MP1 PMOS transistor

Claims (14)

A method for driving a word line by a word line driver, the word line driver comprising:
A first address decoder comprising a first circuit and a second circuit, and a control terminal provided between the first circuit and the second circuit, and used to select the word line;
A first power supply, a second power supply, connected to the first address decoder and the word line, used to convert a voltage level of the word line, and a second circuit of the first address decoder; A level shift circuit including an input terminal connected to the
The method comprises:
(A) converting the voltage level of the input terminal of the level shift circuit by converting the voltage level of the control terminal when the second circuit is turned on;
(B) converting a voltage level of at least one of the first power supply source and the second power supply source, and further separating the voltage level of the control terminal from the voltage level of the word line by the second circuit; And a step of driving the word line. 2. The word line driving method according to claim 1, wherein both the voltage levels of the first power supply source and the second power supply source are converted in step (b). The level shift circuit further includes a latch circuit provided between the input terminal of the level shift circuit and the word line, and electrically connected to the input terminal of the level shift circuit and the word line, or 3. The word of claim 2, wherein the method further comprises: (c) the latch circuit changing the voltage level of the word line when the voltage level at the input of the level shift circuit is changed. Line drive method. 4. The word line driving method according to claim 3, wherein said latch circuit includes a plurality of inverters. The level shift circuit is a P-type transistor provided between the first power supply source and an input terminal of the latch circuit, and further electrically connected to the first power supply source and an input terminal of the latch circuit. And an N-type transistor provided between the second power supply source and the input terminal of the latch circuit, and further electrically connected to the second power supply source and the input terminal of the latch circuit, Alternatively, the method further comprises the step of: (d) switching one of the P-type transistor and the N-type transistor so that an input terminal of the latch circuit is connected to the first power supply source and the second power supply source. 4. The word line driving method according to claim 3, further comprising a step of being electrically connected to one of the word lines. 6. The word line driving method according to claim 5, wherein said P-type transistor is a PMOS transistor, and said N-type transistor is an NMOS transistor. The level shift circuit is a P-type transistor provided between the first power supply source and an input terminal of the latch circuit, and further electrically connected to the first power supply source and an input terminal of the latch circuit. Or the method comprises the step of: (d) electrically connecting an input of the latch circuit to the first power supply by switching the P-type transistor. The word line driving method according to claim 3. 8. The word line driving method according to claim 7, wherein said P-type transistor is a PMOS transistor. An N-type transistor provided between the second power supply and the input terminal of the latch circuit, and further including an N-type transistor electrically connected to the input terminal of the second power supply and the latch circuit, or 4. The method of claim 3, wherein the method includes the step of: (d) electrically connecting an input of the latch circuit to the second power supply by switching the N-type transistor. Word line drive method. 10. The word line driving method according to claim 9, wherein said N-type transistor is an NMOS transistor. 2. The word line driving method according to claim 1, wherein the word line is connected to a gate electrode of a flash memory cell, and is used for writing or erasing the flash memory cell. 2. The word line driving method according to claim 1, wherein said second circuit of said first address decoder includes a P-type transistor and an N-type transistor. 13. The word line driving method according to claim 12, wherein the P-type transistor is a PMOS transistor and the N-type transistor is an NMOS transistor. 13. The word line driving method according to claim 12, wherein the P-type transistor is connected to a second address decoder, and the N-type transistor is connected to a third address decoder.

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