JP2004178622A - Power supply device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply device for reducing electric power consumption. <P>SOLUTION: The device is used for a flash memory to supply an operation voltage thereof. The flash memory comprises a plurality of memory blocks and a plurality of decoders corresponding to the memory blocks, each of the memory blocks has a plurality of memory cells used for storing data, and each of the decoders selects memory cells in corresponded memory blocks, respectively. The device is connected to the decoders, has at least three voltage sources used for outputting voltages having different voltage levels, respectively, and controls the voltage sources so as to the voltage difference between a high voltage level and a low voltage level of a decoder in a standby state becomes lower than that of the decoder in an operating state. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a power supply device used for a flash memory, and more particularly to a power supply device with low power consumption.
[0002]
[Prior art]
In recent years, the demand for portable electronic products has increased, and with this, the market share of flash memory technology and applied products has been further expanding. The so-called portable electronic products include digital cameras, mobile phones, game machines, personal digital assistants (PDAs), and answering machines. In these electronic products, for example, flash memories are widely used for films of digital cameras, memories of personal digital assistants, and other programmable integrated circuits.
[0003]
Flash memory is a type of non-volatile storage medium, whose principle is to change the threshold voltage of a transistor or a memory cell to control the switching of the gate channel to achieve the purpose of storing data. Further, data stored in the storage medium is not lost due to interruption of power supply. Such a flash memory has a special structure as an ERP (Electrically Erasable and Programmable Read-Only Memory, hereinafter referred to as an EEPROM). That is, the flash memory changes the threshold voltage according to the number of electrons stored in the floating gate.
[0004]
Generally, the number of electrons stored in a floating gate using FN tunneling (Fowler-Nordheim tunneling) or hot electron injection (hot electron injection) in order to program an EPROM. Control. Therefore, if the number of electrons on the floating gate decreases, the threshold voltage of the flash memory also decreases, and the binary value "0" is stored in the flash memory. Similarly, if the number of electrons on the floating gate increases, the threshold voltage of the flash memory also increases, and the binary value "1" is stored in the flash memory.
[0005]
FIG. 1 shows a conventional flash memory 10. According to FIG. 1, the flash memory 10 includes a control circuit 11, a memory 12, a sense amplifier 14, a page buffer 16, a drive circuit 18, and a power supply unit 20. The control circuit 11 outputs a control signal to control the operation of the flash memory 10. The memory 12 comprises a plurality of memory blocks 22, each of which comprises a plurality of memory cells 24. The memory cells 24 are arranged in an array and store binary values. In addition, each memory block 22 includes a plurality of transistors 25, and the transistors 25 control access to the memory cells 24 according to their conducting states.
[0006]
As described above, the memory cell 24 determines the stored binary value according to the number of electrons stored in the floating gate. Therefore, when the memory cell 24 becomes conductive, the number of electrons stored in the floating gate affects the corresponding threshold voltage and further affects the magnitude of the output current. The sense amplifier 14 is electrically connected to the control circuit 11 and reads a corresponding binary number in the memory cell 24 according to a control signal output from the control circuit 11. The sense amplifier 14 calculates the voltage or current output from the memory cell 24 to accurately determine the binary value stored in the memory cell 24. The page buffer 16 is electrically connected to the control circuit 11, performs a related write operation on the memory cell 24 according to a control signal output from the control circuit 11, and stores a binary value in the memory cell 24.
[0007]
The drive circuit 18 includes a plurality of decoders 28 and accesses a corresponding memory cell 24 in the corresponding memory block 22 according to a control signal output from the control circuit 11. Each decoder 28 corresponds to each memory block 22 in the memory 12, for example, the decoder 28a corresponds to the memory block 22a, and the decoder 28b corresponds to the memory block 22b. The decoder 28 includes a plurality of word line drivers 30 each electrically connected to the memory block 22, a memory cell 24 placed on the same row, and a select gate driver electrically connected to the memory block 22. 32 and transistors 25, each located in a different column. The memory cells 24 in the memory block 22 to be processed by the select gate driver 32 and the word line driver 30 are selected. Further, the power supply means 20 is used to provide a necessary operating voltage to each decoder 28, for example, to provide a driving voltage necessary to control the conduction of the memory cell 24 and the transistor 25.
[0008]
FIG. 2 discloses the power supply means 20 according to FIG. 1, and FIG. 3 discloses the word line driver 30 according to FIG. According to FIG. 2, the power supply means 20 comprises a plurality of voltage sources 34, each providing an output voltage having a different voltage level, and a switch 36 for selecting the output voltage generated by the voltage source 34. The selected output voltage is output to the drive circuit 18 via the plurality of output terminals A, B, C, D, that is, each decoder 28 is provided as a required operating voltage. For example, suppose that the voltage sources 34a, 34b, 34c, 34d, and 34e output 7V, 3V, 1.5V, 0V, and -10V, respectively, and the decoder 28a processes the corresponding memory block 22a according to the control signal of the control circuit 11. Then, the access of the memory cells 24 on each word line of the memory block 22a is controlled by outputting the first drive voltage (0V) or the second drive voltage (-10V) by each word line driver 30. As a result, the voltage source 34 e can output −10 V to one word line driver 30 of the decoder 28 via the output terminal C selected by the switch 36. Then, the voltage source 34d can output 0 V to another word line driver 30 of the decoder 28 via the output terminal D selected by the switch 36. As described above, the word line to be processed and the memory cell 24 thereon can be selected.
[0009]
As shown in FIG. 3, the word line driver 30 can be formed of an integrated circuit using complementary metal oxide semiconductor transistors. That is, the word line driver 30 includes a plurality of complementary metal oxide semiconductor transistors 38. The word line driver 30 includes a P-type metal oxide semiconductor transistor 40 and an N-type metal oxide semiconductor transistor 42. The transistors 40 and 42 are electrically connected to the first drive voltage and the second drive voltage, respectively. Connected. FIG. 3 shows only one complementary metal oxide semiconductor transistor 38 for explanation.
[0010]
The drive circuit 18 generates a selection signal according to the control signal of the control circuit 11 and controls the operations of the word line driver 30 and the select gate driver 32 in each decoder. For example, when the control circuit 11 accesses the memory cell 24 in the memory block 22a, the drive circuit 18 outputs a corresponding selection signal to the decoder 28a after receiving the control signal of the control circuit 11. At this time, the memory block 22a is in an operation state (active), and the other decoder 28b does not receive the selection signal. Accordingly, the other decoder 28b enters a standby state (standby). Therefore, the decoder 28a controls the word line driver 30 to access the memory cells 24 on each word line in the memory block 22a. That is, when accessing the memory cell 24 on the word line of the n-th row, the selection signal keeps the P-type metal oxide semiconductor transistor 40 non-conductive and turns the N-type metal oxide semiconductor transistor 42 conductive. Let Therefore, the n-th row word line is brought close to the second drive voltage by the second drive voltage (−10 V), and all the memory cells 24 electrically connected to the n-th row word line are turned on. Allow access operations to continue. Conversely, the memory cells 24 on other word lines in the memory block 22a are kept off. Therefore, the selection signal makes the P-type metal oxide semiconductor transistor 40 conductive and keeps the N-type metal oxide semiconductor transistor 42 non-conductive. Therefore, the first drive voltage prevents word lines other than the n-th word line from being accessed close to the first drive voltage.
[0011]
Similarly, the memory cells 24 in the memory block 22b in the standby state are also non-conductive, that is, since the word line driver 30 of the decoder 28b has not received any selection signal, Will be inaccessible. The structure and operation method of the select gate driver 32 are almost the same as those of the word line driver 30, and the select gate driver 32 is driven by the select signal and the third and fourth drive voltages (7V and 0V) output from the output terminals A and B. , And the conduction state of the transistor 25 on each bit line. Here, the description of the same operation as above is omitted.
[0012]
As described above, when accessing the memory block 22a in the operating state, the power supply means 20 outputs the first and second drive voltages to the word line driver 30 in the decoder 28a. For the memory block 22b in the standby state, the word line driver 30 of the decoder 28b also receives the first and second drive voltages output from the power supply means 20. However, the decoder 28b does not receive any selection signal corresponding to the control signal output from the control circuit 11. For this reason, both the P-type metal oxide semiconductor transistor 40 and the N-type metal oxide semiconductor transistor 42 in the word line driver 30 are in a non-conductive state, and the first and the second output from the power supply means 20 are respectively provided. Receive drive voltage.
[0013]
As a result, the first and second drive voltages cause the complementary metal oxide semiconductor transistor 38 to generate a reverse bias. For example, a reverse bias is applied between the source of the P-type metal oxide semiconductor transistor 40 and the substrate, and a junction leakage current is generated, thereby causing unnecessary power consumption. For the same reason, the select gate driver 32 corresponding to the memory block in the standby state also generates a leakage current under the influence of the reverse bias generated by the third and fourth drive voltages. When the output of the current is fixed, the leakage current generated by the reverse bias of the decoder 28b further reduces the output current of the decoder 28a, so that the actual driving current of the decoder 28a is reduced and the driving efficiency is reduced.
[0014]
[Problems to be solved by the invention]
Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a power supply unit capable of reducing power consumption.
[0015]
[Means for Solving the Problems]
The inventor of the present invention has conducted intensive studies in view of the drawbacks of the conventional technology, and as a result, has been used for a flash memory, a power supply device for supplying an operating voltage of the flash memory, the flash memory, a plurality of And a plurality of decoders corresponding to the plurality of memory blocks, wherein the plurality of memory blocks comprise a plurality of memory cells used for storing data, and the plurality of memory cells correspond to the plurality of decoders. Selecting a memory cell in a block, wherein the power supply comprises at least three voltage sources connected to the plurality of decoders and each used to output a voltage having a different voltage level, and in a standby state; The voltage difference between the high voltage level and the low voltage level of the decoder is the high voltage level of the operating decoder. The structure for controlling the voltage source to be lower than the voltage difference between the low voltage level, it is possible to reduce power consumption.
[0016]
A plurality of switches, each of which corresponds to one decoder, and is electrically connected between the voltage source and the corresponding decoder, wherein the decoder is a word line driver or a select gate driver. As a result, a power supply device that can reduce power consumption is obtained.
[0017]
Hereinafter, the present invention will be described specifically.
[0018]
The power supply device according to claim 1, wherein the power supply device is used for a flash memory and supplies an operation voltage of the flash memory, wherein the flash memory corresponds to a plurality of memory blocks and the plurality of memory blocks. A plurality of decoders, wherein the plurality of memory blocks include a plurality of memory cells used for storing data, and the plurality of decoders select memory cells in the corresponding memory blocks, and The supply device includes at least three voltage sources connected to the plurality of decoders and used to output voltages having different voltage levels, wherein a high voltage level and a low voltage level of the decoder in a standby state are provided. The voltage difference is lower than the voltage difference between the high and low voltage levels of the decoder in the operating state. It is configured to control the voltage source.
[0019]
The power supply device according to claim 2, wherein the power supply device according to claim 1 further includes a plurality of switches, each of the plurality of switches corresponding to one decoder, and the power supply device connected to the voltage source. It is electrically connected between the corresponding decoder and is used for selectively outputting a voltage generated by the voltage source to the corresponding decoder.
[0020]
According to a third aspect of the present invention, the decoder according to the first aspect is a word line driver.
[0021]
According to a fourth aspect of the present invention, when the word line driver according to the third aspect is in an operating state, the high voltage level is a ground voltage and the low voltage level is a negative voltage.
[0022]
According to a fifth aspect of the present invention, when the word line driver according to the fourth aspect is in a standby state, the high voltage level is a positive voltage and the low voltage level is a ground voltage.
[0023]
The power supply means according to claim 6 is characterized in that the decoder according to claim 1 is a select gate driver.
[0024]
The power supply means according to claim 7, wherein when the select gate driver according to claim 6 is in an operating state, the high voltage level is a first plus voltage and the low voltage level is a ground voltage. I do.
[0025]
The power supply means according to claim 8, wherein when the select gate driver according to claim 7 is in a standby state, the high voltage level is a second plus voltage, the low voltage level is a ground voltage, and The second plus voltage is lower than the first plus voltage.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention provides a low-power-consumption power supply device, which is used for a flash memory and supplies an operation voltage of the flash memory, wherein the flash memory includes a plurality of memory blocks. And a plurality of decoders corresponding to the plurality of memory blocks, wherein the plurality of memory blocks include a plurality of memory cells used for storing data, and the plurality of decoders correspond to the plurality of memory blocks. Selecting a memory cell, the power supply comprising at least three voltage sources connected to the plurality of decoders and used to output voltages having different voltage levels, wherein the high voltage of the decoder in a standby state is provided. The voltage difference between the voltage level and the low voltage level is determined by the high and low voltage levels of the operating decoder. Controlling the voltage source to be lower than the voltage difference between Le.
[0027]
In order to detail the structure and features of such a power supply device, a specific embodiment will be described below with reference to FIG.
[0028]
FIG. 4 shows a power supply means 50 according to the present invention. The power supply means 50 includes a plurality of voltage sources 52 each providing an output voltage having a different voltage level, and a switch 54 for selecting an output voltage generated by the voltage source 52. The selected output voltage is output to the drive circuit 18 via the plurality of output terminals A, B, C, and D, and each decoder 28 provides a required operation voltage. Each voltage source 52 is electrically connected to each switch 54, and each switch 54 is connected to one decoder 28. For example, switch 54a is connected to decoder 28a, and switch 54b is connected to decoder 28b. The operation of the power supply means 50 will be described in detail below.
[0029]
For example, the voltage sources 52a, 52b, 52c, 52d, 52e output 7V, 3V, 1.5V, 0V, and -10V, respectively. When the decoder 28a performs the processing of the corresponding memory block 22a according to the control signal of the control circuit 11, each word line driver 30 performs the first operation in order to access the memory cell 24 on each word line in the memory block 22a. A driving voltage (0 V) or a second driving voltage (-10 V) must be output. Thus, the voltage source 52e outputs -10V to the word line driver 30 via the output terminal C selected by the switch 54a, and the voltage source 52d outputs the word line via the output terminal D selected by the switch 54a. Output 0V to the driver 30.
[0030]
In addition, the select gate driver 32 must receive a third drive voltage (7V) and a fourth drive voltage (0V) to control access to the memory cells 24 on each bit line. Thus, the voltage source 52a outputs 7 V to the select gate driver 32 via the output terminal A selected by the switch 54a, and the voltage source 52c outputs the select gate driver signal via the output terminal B selected by the switch 54a. 32 is output to 0V.
[0031]
In the memory block 28b in the standby state, the voltage source 52c outputs 1.5 V to the word line driver 30 via the output terminal C selected by the switch 54b, and the voltage source 52d outputs the output terminal selected by the switch 54b. 0V is output to the word line driver 30 via D. The voltage source 52b outputs 3 V to the select gate driver 32 via the output terminal A selected by the switch 54b, and the voltage source 52c outputs the voltage to the select gate driver 32 via the output terminal B selected by the switch 54b. Outputs 0V.
[0032]
As described above, the drive circuit 18 generates a selection signal according to the control signal of the control circuit 11, and the selection signal is used to control the operation of the word line driver 30 and the select gate driver 32 in each decoder 28. When the control circuit 11 accesses the memory cell 24 in the memory block 22a, the drive circuit 18 receives a control signal from the control circuit 11, and then inputs a selection signal to the decoder 28a to operate the memory block 22a. Let Since the other decoder 28b does not receive any selection signal, the other memory block 22b enters a standby state.
[0033]
Therefore, the decoder 28a controls the word line driver 30 to access the memory cells 24 on each word line in the memory block 22a. That is, when the memory cell 24 on the word line of the n-th row is accessed, the selection signal keeps the P-type metal oxide semiconductor transistor 40 non-conductive and the N-type metal oxide semiconductor transistor 42 conductive. . Accordingly, the second drive voltage (−10 V) brings the n-th word line closer to the second drive voltage, and conducts the memory cells 24 electrically connected to the n-th word line so that the memory cells 24 can be accessed. I do. Conversely, the memory cells 24 on the other word lines in the memory block 22a remain non-conductive, so that the selection signal turns on the P-type metal oxide semiconductor transistor 40 and the N-type metal oxide semiconductor transistor 42 is made non-conductive. For this reason, the first drive voltage (0 V) brings word lines other than the n-th word line closer to the first drive voltage and maintains the non-conductive state.
[0034]
However, for the memory block 22b in the standby state, the decoder 28b does not receive any selection signal, and the power supply means 50 outputs the first drive voltage (1.5V) and the second drive voltage (0V) by the switch 54b. I do. Thereby, as disclosed in FIG. 3, the voltage difference between the first and second drive voltages is increased even though the first and second drive voltages generate a reverse bias in the complementary metal oxide semiconductor transistor 38. Being small, the leakage current is correspondingly reduced. Similarly, the voltage difference (3 V) between the third and fourth drive voltages input to the select gate driver 32 is correspondingly reduced, and accordingly, the leakage current is correspondingly reduced. Therefore, in this embodiment, the leakage current can be greatly reduced, and the influence of the leakage current on the actual driving current can be reduced, so that the overall driving efficiency of the driving circuit can be increased.
[0035]
Note that the power supply means 50 is not limited to the above-described configuration, and is applicable to a modified or improved power supply means within the scope of the claims of the present invention.
[0036]
【The invention's effect】
As described above, according to the present invention, a plurality of switches selectively output the necessary drive voltage to each decoder, and the voltage difference between the high and low drive voltages received by the decoder of the memory block in the standby state is changed to the operation state. The voltage difference of the decoder of a certain memory block is made smaller. For this reason, the leakage current generated by the decoder of the memory block corresponding to the standby state can be greatly reduced, and not only the unnecessary power consumption can be reduced by reducing the current, but also the decoder of the memory block corresponding to the operation state can be reduced. Drive efficiency can be increased.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a conventional flash memory.
FIG. 2 is an explanatory diagram illustrating a power supply unit disclosed in FIG. 1;
FIG. 3 is an explanatory diagram illustrating the word line driver disclosed in FIG. 1;
FIG. 4 is an explanatory diagram showing power supply means in the present invention.
[Explanation of symbols]
Reference Signs List 10 flash memory 11 control circuit 12 memory 14 sense amplifier 16 page buffer 18 drive circuit 20, 50 power supply means 22, 22a, 22b memory block 24 memory cell 25 transistor 28, 28a, 28b decoder 30 word line driver 32 select gate driver 34 , 34a, 34b, 34c, 34d, 34e, 52, 52a, 52b, 52c, 52d, 52e Voltage source 36, 54 Switch 38 Complementary metal oxide semiconductor transistor 40 P-type metal oxide semiconductor transistor 42 N-type metal oxide film Semiconductor transistor

Claims (8)

A power supply device used for a flash memory and supplying an operation voltage of the flash memory,
The flash memory includes a plurality of memory blocks and a plurality of decoders corresponding to the plurality of memory blocks, the plurality of memory blocks including a plurality of memory cells used for storing data, and A decoder selects a corresponding memory cell in the memory block,
The power supply includes at least three voltage sources connected to the plurality of decoders and used to output voltages having different voltage levels, the high voltage level and the low voltage level of the decoder in a standby state. A voltage difference between the high voltage level and the low voltage level of the decoder in the operating state. The power supply device further comprises a plurality of switches, each of the plurality of switches corresponding to one decoder, and electrically connected between the voltage source and the corresponding decoder, and a selection switch. 2. The power supply according to claim 1, wherein the power supply is used to output a voltage generated by the voltage source to the corresponding decoder. The power supply of claim 1, wherein the decoder is a word line driver. 4. The power supply according to claim 3, wherein the high voltage level is a ground voltage and the low voltage level is a negative voltage when the word line driver is in an operating state. 5. The power supply according to claim 4, wherein the word line driver is in a standby state, wherein the high voltage level is a positive voltage and the low voltage level is a ground voltage. The power supply according to claim 1, wherein the decoder is a select gate driver. 7. The power supply according to claim 6, wherein when the select gate driver is in an operation state, the high voltage level is a first plus voltage and the low voltage level is a ground voltage. When the select gate driver is in a standby state, the high voltage level is a second plus voltage, the low voltage level is a ground voltage, and the second plus voltage is lower than the first plus voltage. The power supply according to claim 7, characterized in that:

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