JP2004220689A - Optical disk apparatus and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method of an optical disk apparatus for stably outputting a laser diode during shift periods. <P>SOLUTION: In the method, when reproducing data, a control voltage VRDC_R is output from a first voltage output circuit 14 so that output power of a light-emitting element is maintained constant, and when the data are deleted or recorded, a control voltage VRDC_W is output from the output circuit 14 so that at least a part of a current flowing into the light emitting element is maintained constant, and a control voltage VWDC_W is output from a second voltage output circuit 16 so that the output power of the light emitting is maintained to be constant. Before shifting to the deletion or recording of the data, the control voltage of the output circuit 16 is set to a value which the subtracted the difference between the control voltages VRDC_R and the VRDC_W, and the control voltage VWDC_W. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【００２３】
また、データの再生のフレームからデータの消去又は記録を行うフレームに移行する前に、ＤＡ回路３８に設定する設定値ＷＤＡＣ２は関係式（２）を用いて算出することができる。
【００２４】
【数２】

【００２５】
以上のように、設定値ＷＤＡＣ２の値を定めることができる。なお、ＡＣＣ回路３４による定電流制御では、実際のレーザダイオード１０の出力電力をフィードバックに利用していないため、レーザダイオード１０の温度の影響により設定値ＷＤＡＣ２とレーザダイオード１０の出力電力との関係が変動し易い。従って、レーザダイオード１０の測定温度Ｔ２が測定温度Ｔ１に対して所定の温度範囲内にない場合には、上記処理をやり直し、関係式（１）及び（２）を再度求めて設定値ＷＤＡＣ１及びＷＤＡＣ２を算出する。
【００２６】
次に、ＡＴＩＰＳＹＮＣに同期して、データの消去及び記録を行う第２フレームに移行する。切替タイミング回路４６は、ＡＴＩＰＳＹＮＣの立ち上がりに応じて、ＥＦＭＧ信号を立ち下げ、スイッチＳＷ１をｂ１側に、スイッチＳＷ２をａ２側に切り替える。
【００２７】
処理部４４は、ＤＡ回路２８にＷＲＤＡ信号を出力する。ＤＡ回路２８は、ＷＲＤＡ信号をデジタル／アナログ変換してＡＣＣ回路２４に出力する。ＡＣＣ回路２４は、アナログ変換されたＷＲＤＡ信号を受けて、このＷＲＤＡ信号で定められる制御電圧を第１電圧出力回路１４から出力させ、ＬＤドライバ１２の第１電流源５０から出力される駆動電流がＷＲＤＡ信号によって定められる一定の電流値に維持されるように定電流制御を行う。このとき、ＷＲＤＡ信号で定められる駆動電流は、データの記録中における基底パワー（ボトムパワー）を決定するものであり、レーザダイオード１０が光らない程度の電流値とされる。このとき、第１電圧出力回路１４が出力する制御電圧を電圧値ＶＲＤＣ＿Ｗ（記録時のＶＲＤＣ）という。
【００２８】
一方、処理部４４はＤＡ回路３６に対してＷＤＡＣ１信号を出力する。ＤＡ回路３６は、ＷＤＡＣ１信号をデジタル／アナログ変換してＡＰＣ回路３２に出力する。ＡＰＣ回路３２は、アナログ変換されたＷＤＡＣ１信号を受けて、レーザダイオード１０からの出力電力がディスク上のデータの消去を行うために適した電力となるように第２電圧出力回路１６から出力される制御電圧を制御する。レーザダイオード１０の出力パワーはＦＭＤ回路４８によって読み取られ、フィードバック信号としてＳ／Ｈ回路４０へ出力される。ＥＮＤＥＣ４２は、データの消去のタイミングに同期してＷＡＰＣ信号を出力し、ＦＭＤ回路４８からのフィードバック信号をＳ／Ｈ回路４０にサンプルホールドさせる。ＡＰＣ回路３２はこのサンプリング値を受けて、消去時のレーザダイオード１０のパワーがＷＤＡＣ１信号によって定められる一定値に維持されるように第２電圧出力回路１６から出力される制御電圧をフィードバック制御する。
【００２９】
同時に、ＥＮＤＥＣ４２は、データの消去時にＲＡＰＣ信号を出力することによって、ＦＭＤ回路４８からのフィードバック信号をＳ／Ｈ回路３０にサンプルホールドさせる。ＡＰＣ回路２２は、このサンプリング値を受けて、光ディスク装置がデータの再生処理に切り替えられた際にレーザダイオード１０の出力パワーが再生に適した値となるように調整を行う。
【００３０】
また、ＥＮＤＥＣ４２は、ディスク上のデータを消去するタイミングでＰＥＯ信号を出力する。これによって、スイッチＳＷ４が閉じられ、第２電圧出力回路１６とＬＤドライバ１２とが接続される。ＡＣＣ回路２４によって制御されたＬＤドライバ１２の第１電流源５０からの電流と、ＡＰＣ回路３２によって制御されたＬＤドライバ１２の第２電流源５２からの電流との合成電流がレーザダイオード１０の駆動電流として出力され、ディスク上のデータが消去される。このときの第２電圧出力回路１６の制御電圧を電圧値ＶＷＤＣ＿Ｗ（記録時のＶＷＤＣ）とし、レーザダイオード１０からの出力電力を電力値ＦＭＤ＿Ｗとする。
【００３１】
また、ディスク上にデータを記録する際には、処理部４４はＤＡ回路２０から電圧値ＶＷＤＣ＿Ｗが出力されるように設定する。増幅器１８からは、電圧値ＶＷＤＣ＿Ｗを増幅率ＡＴＴだけ増幅させた制御電圧が出力される。
【００３２】
ＥＮＤＥＣ４２は、ディスク上にデータを記録するタイミングでＰＷＯ信号を出力し、スイッチＳＷ５を閉じることにより増幅器１８とＬＤドライバ１２とを接続する。これによって、ＡＣＣ回路２４によって制御されたＬＤドライバ１２の第１電流源５０からの電流と、電圧値ＶＷＤＣ＿Ｗ×増幅率ＡＴＴ倍の制御電圧ＶＷＤＣ＿Ｗによって制御された第３電流源５４からの電流との合成電流がレーザダイオード１０に駆動電流として供給され、ディクス上にデータが記録される。
【００３３】
【発明が解決しようとする課題】
上記従来技術では、データの再生を行うフレームからデータの消去又は記録を行うフレームに移行する前に、第２電圧出力回路１６に接続されたＡＣＣ回路３４に対してＷＤＡＣ２信号を出力してデータの消去又は記録に適したレーザ出力が得られるようにパワーの先出し制御を行った後に、第２電圧出力回路１６の制御がＡＣＣ回路３４による定電流制御からＡＰＣ回路３２による定電力制御に切り替えられる。
【００３４】
しかしながら、データの再生を行うフレームからデータの消去又は記録を行うフレームに移行する際には、第１電圧出力回路１４もＡＰＣ回路２２による定電力制御からＡＣＣ回路２４による定電流制御に切り替えられるため、第１電圧出力回路１４からの制御電圧が電圧値ＶＲＤＣ＿Ｒから電圧値ＶＲＤＣ＿Ｗに安定するまでに時間を要する。そのため、データの消去又は記録を行うフレームの開始初期において、レーザダイオード１０の基底パワーが安定せず、図５のように、ディスク上のデータを消去する際のレーザ出力は２点鎖線で示すように変化し、ディスク上にデータを記録する際のレーザ出力は１点鎖線で示すように変化し、余分なパワーが出力される問題が生ずる。
【００３５】
このレーザダイオード１０からの異常な出力によって、ディスク上のデータの消去及び記録の品質が低下する。同時に、光ディスク装置のサーボ制御を行うための制御信号の取得を困難にし、サーボ制御の破綻を招く原因となる。さらに、レーザ出力が不必要に高くなるためにレーザダイオードの特性を劣化させたり、寿命を短くさせる問題も引き起こす。
【００３６】
本発明は、上記従来技術の問題を鑑み、少なくとも上記課題の１つを解決すべく、移行期間のレーザダイオードの出力を安定に行うことができる光ディスク装置及び光ディスク装置の制御方法を提供することを目的とする。
【００３７】
【課題を解決するための手段】
上記課題を解決できる本発明は、第１の制御信号を出力する第１の制御信号出力手段と、第２の制御信号を出力する第２の制御信号出力手段と、を含み、前記第１及び第２の制御信号に基づいて発光素子の出力を制御してデータ再生及び消去又は記録を行う光ディスク装置であって、データの再生時において、前記第１の制御信号出力手段を制御して発光素子の出力電力が一定に維持されるように前記第１の制御信号として第１制御値を出力させる第１の定電力制御手段と、データの消去又は記録時において、前記第１の制御信号出力手段を制御して発光素子に流れる電流の少なくとも一部が一定に維持されるように前記第１の制御信号として第２制御値を出力させる第１の定電流制御手段と、データの再生時において、前記第２の制御信号出力手段を制御して発光素子に流れる電流の少なくとも一部が一定に維持されるように前記第２の制御信号として第３制御値を出力させる第２の定電流制御手段と、データの消去又は記録時において、前記第２の制御信号出力手段を制御して発光素子の出力電力が一定に維持されるように前記第２の制御信号として第４制御値を出力させる第２の定電力制御手段と、前記第１の制御信号出力手段の制御を前記第１の定電力制御手段から前記第１の定電流制御手段に切り替え、前記第２の制御信号出力手段の制御を前記第２の定電流制御手段から前記第２の定電力制御手段に切り替える切替手段と、を含み、前記切替手段によって前記第２の制御信号出力手段の制御が前記第２の定電流制御手段から前記第２の定電力制御手段へと切り替える前に、前記第２の制御信号出力手段から前記第２の制御信号として前記第４制御値から前記第１制御値と前記第２制御値との差を引いた値を出力させることを特徴とする。
【００３８】
また、本発明の別の形態は、第１及び第２の制御信号に基づいて発光素子の出力を制御してデータの再生及び消去又は記録を行う光ディスク装置の制御方法であって、データの再生時において、発光素子の出力電力が一定に維持されるように前記第１の制御信号として第１制御値を出力させ、発光素子に流れる電流の少なくとも一部が一定に維持されるように前記第２の制御信号として第３制御値を出力させる第１の工程と、データの消去又は記録時において、発光素子に流れる電流の少なくとも一部が一定に維持されるように前記第１の制御信号として第２制御値を出力させ、発光素子の出力電力が一定に維持されるように前記第２の制御信号として第４制御値を出力させる第２の工程と、を含み、前記第１の工程から前記第２の工程に移行する前に、前記第２の制御信号として前記第４制御値から前記第１制御値と前記第２制御値との差を引いた値を出力させる工程を有することを特徴とする。
【００３９】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して説明する。本発明の実施の形態における光ディスク装置は、図１及び図２に示した従来の光ディスク装置と同様の構成を含んでいる。
【００４０】
図３に、本実施の形態におけるディスク上のデータの再生、消去及び記録時のタイミングチャートを示す。このタイミングチャートの例では、第１フレームにおいてディスクのデータの再生が行われ、その後第２フレームにおいてデータの消去及び記録に移行する。
【００４１】
第１フレームでは、切替タイミング回路４６から出力されるＥＦＭＧ信号が“Ｌレベル”にあり、スイッチＳＷ１がａ１側に接続され、スイッチＳＷ２はｂ２側に接続される。従って、第１電圧出力回路１４はＡＰＣ回路２２によって制御され、第２電圧出力回路１６はＡＣＣ回路３４によって制御されることとなる。ＥＮＤＥＣ４２からはＬＤＯＮ信号が常時出力され、スイッチＳＷ３が閉じられ、第１電圧出力回路１４とＬＤドライバ１２が接続される。
【００４２】
第１フレームのデータの再生において、レーザダイオード１０の駆動電流は従来技術と同様に制御される。すなわち、処理部４４からＤＡ回路２６にＲＥＤＡ信号が設定される。一方、ＦＭＤ回路４８によってレーザダイオード１０の出力パワーが読み出され、そのサンプリング値がＡＰＣ回路２２にフィードバックされることによってレーザダイオード１０の出力パワーがＲＥＤＡ信号によって規定される一定値に維持される。このとき、第１電圧出力回路１４から出力される制御電圧は電圧値ＶＲＤＣ＿Ｒである。
【００４３】
例えば、相変化を利用したディスクを対象とした場合、データの再生にはリードパワーＰ_ＲＤ：１ｍＷが得られるように制御電圧の電圧値ＶＲＤＣ＿Ｒが調整される。
【００４４】
一方、データを再生する間、ＥＮＤＥＣ４２はＰＥＯ信号及びＰＷＯ信号を“Ｌレベル”に維持して出力する。これによってＳＷ４及びＳＷ５は開放され、第２電圧出力回路１６及び増幅器１８がＬＤドライバ１２から切り離される。
【００４５】
本実施の形態の光ディスク装置では、データの再生を行うフレームからデータの消去及び記録を行うフレームに移行する前に、処理部４４からＤＡ回路３８にＷＤＡＣ２’信号を設定する。ＤＡ回路３８は、ＷＤＡＣ２’信号をデジタル／アナログ変換してＡＣＣ回路３４へ出力する。ＡＣＣ回路３４は、アナログ変換されたＷＤＡＣ２’信号を受けて、第２電圧出力回路１６からＷＤＡＣ２’信号によって規定される制御電圧が出力されるように制御を行う。ＷＤＡＣ２’信号の設定値の求め方については後に詳述する。
【００４６】
ディスクからのデータの再生が終了すると、ＡＴＩＰＳＹＮＣの立ち上がりに同期してデータの消去及び再生を行う第２フレームに移行する。切替タイミング回路４６は、ＡＴＩＰＳＹＮＣの立ち上がりに応じてＥＦＭＧ信号を“Ｈレベル”に立ち上げ、スイッチＳＷ１をｂ１側に接続し、スイッチＳＷ２をａ２側に接続する。これによって、第１電圧出力回路１４はＡＣＣ回路２４によって定電流制御され、第２電圧出力回路１６はＡＰＣ回路３２によって定電力制御されることとなる。
【００４７】
処理部４４は、ＤＡ回路２８にＷＲＤＡ信号を出力する。ＷＲＤＡ信号はアナログ信号に変換されてＡＣＣ回路２４に出力される。ＡＣＣ回路２４は、ＷＲＤＡ信号を受けて第１電圧出力回路１４に対して定電流制御を行う。このとき、第１電圧出力回路１４から出力される制御電圧は、その制御電圧を受けたＬＤドライバ１２の第１電流源５０からの駆動電流がレーザダイオード１０を発光させない程度の電流となるように制御される。常時“Ｈレベル”にあるＬＤＯＮ信号によってスイッチＳＷ３は閉じられており、第１電圧出力回路１４からの制御電圧を受けたＬＤドライバ１２の第１電流源５０からレーザダイオード１０に駆動電流が出力される。
【００４８】
第１電圧出力回路１４の制御がＡＰＣ回路２２による定電力制御からＡＣＣ回路２４による定電流制御に切り替えられた直後においては、第１電圧出力回路１４から出力される制御電圧は定電力制御時の電圧値ＶＲＤＣ＿Ｒから定電流制御時の電圧値ＶＲＤＣ＿Ｗへ向かって減少し、最終的にＷＲＤＡ信号で規定される制御電圧ＶＲＤＣ＿Ｗで安定する。このような制御電圧の変化に伴って、ＬＤドライバ１２の第１電流源５０から出力される駆動電流も減少する。
【００４９】
一方、処理部４４は、ＤＡ回路３６に対してＷＤＡＣ１信号を出力する。ＤＡ回路３６は、ＷＤＡＣ１信号をデジタル／アナログ変換してＡＰＣ回路３２へ出力する。レーザダイオード１０の出力パワーはＦＭＤ回路４８によって読み取られ、そのサンプリング値がＡＰＣ回路３２にフィードバックされて、ＡＰＣ回路３２はレーザダイオード１０の出力パワーをＷＤＡＣ１信号によって規定されるパワーに定電力制御する。
【００５０】
データの消去を行うときには、ＥＮＤＥＣ４２によってデータを消去するタイミングに同期させてＰＥＯ信号を“Ｈレベル”に設定し、スイッチＳＷ４を閉じることで第２電圧出力回路１６からの制御電圧値ＶＷＤＣ＿ＷをＬＤドライバ１２に入力する。その結果、ＬＤドライバ１２の第２電流源５２から制御電圧値ＶＷＤＣ＿Ｗに応じた駆動電流が供給される。レーザダイオード１０は、第１電流源５０及び第２電流源５２からの駆動電流の合成電流によって発光し、ディスク上のデータが消去される。
【００５１】
また、ディスク上にデータを記録する際には、処理部４４はＤＡ回路２０から電圧値ＶＷＤＣ＿Ｗが出力されるように設定する。増幅器１８からは電圧値ＶＷＤＣ＿Ｗを増幅率ＡＴＴだけ増幅させた制御電圧が出力される。さらに、ＥＮＤＥＣ４２のＰＷＯ信号に基づいてデータを記録するタイミングに同期させてスイッチＳＷ５を閉じることによって増幅器１８とＬＤドライバ１２とが接続される。ＬＤドライバ１２の第３電流源５４は、増幅器１８からの制御電圧を受けて、その制御電圧によって規定される駆動電流をレーザダイオード１０に供給する。その結果、第１電流源５０からの駆動電流と、第３電流源５４からの駆動電流との合成電流によってレーザダイオード１０が発光し、そのレーザダイオード１０の出力によってディクス上にデータが記録される。
【００５２】
例えば、相変化を利用したディスクでは、イレースパワーＰ_ＥＲ：５ｍＷ及びライトパワーＰ_ＷＲ：１１ｍＷが得られるように電圧値ＶＲＤＣ＿Ｗ及びＶＷＤＣ＿Ｗが調整される。
【００５３】
このとき、データの再生のフレームが終了する前にＷＤＡＣ２’信号をＤＡ回路３８に設定することによって第２電圧出力回路１６の制御電圧は予め適値に昇圧されており、第１電圧出力回路１４の出力の変動を打ち消すように第２電圧出力回路１６の制御電圧が昇圧されることとなり、レーザダイオード１０の出力パワーはＷＤＡＣ１信号によって規定されるパワーに維持される。その結果、フレームの開始直後のレーザダイオード１０の出力パワーの変動を最小限に抑制することができる。
【００５４】
＜ＷＲＤＡＣ２’信号の設定値の算出方法＞
ＷＲＤＡＣ２’信号の設定値は、図４に示すように、第１電圧出力回路１４の制御電圧、第２電圧出力回路１６の制御電圧及びＦＭＤ回路４８で読み取ったレーザダイオード１０の出力電力との関係から求めることができる。
【００５５】
まず、ＥＦＭＧ信号を“Ｌレベル”に設定して第１電圧出力回路１４とＡＰＣ回路２２とを接続する。処理部４４からＤＡ回路２６に設定値ＲＥＤＡを出力する。ＤＡ回路２６からの設定値ＲＥＤＡ及びＦＭＤ回路４８からのフィードバック信号を受けたＡＰＣ回路２２の定電力制御によって、第１電圧出力回路１４から設定値ＲＥＤＡで規定される一定の制御電圧ＶＲＤＣ＿Ｒが出力される。このときの、制御電圧ＶＲＤＣ＿ＲをＡＤコンバータによって取得する。
【００５６】
ＬＤドライバ１２は、制御電圧ＶＲＤＣ＿Ｒを受けて、制御電圧ＶＲＤＣ＿Ｒに応じた駆動電流を第１電流源からレーザダイオード１０へ供給する。レーザダイオード１０は、第１電流源５０からの駆動電流によって発光する。このときのレーザダイオード１０の出力パワーＦＭＤ＿ＲをＦＭＤ回路４８によって取得する。
【００５７】
ＤＡ回路２６の設定値ＲＥＤＡ、第１電圧出力回路１４からの制御電圧ＶＲＤＣ＿Ｒ及びレーザダイオード１０の出力パワーＦＭＤ＿Ｒとの関係は図４のＡ点で示される。
【００５８】
次に、ＥＦＭＧ信号を“Ｈレベル”に設定して第１電圧出力回路１４とＡＣＣ回路２４とを接続する。処理部４４は、ＡＤコンバータを用いて第１電圧出力回路１４からの制御電圧を読み取りながら、第１電圧出力回路１４の制御電圧が電圧値ＶＲＤＣ＿ＲとなるようにＤＡ回路２８の設定値を調整する。このときのＤＡ回路２８の設定値をＷＲＤＡ＿１とする。また、ＦＭＤ回路４８を用いてレーザダイオード１０の出力パワーを読み取りながら、レーザダイオード１０が全く発光しない状態（図４のＢ点）となるようにＤＡ回路２８の設定値を調整する。このときのＤＡ回路２８の設定値をＷＲＤＡ＿２とする。これによって、設定値ＷＲＤＡ＿１と設定値ＷＲＤＡ＿２との電位差ΔＶＲを求めることができる。
【００５９】
一方、ＥＦＭＧ信号が“Ｈレベル”であるので第２電圧出力回路１６はＡＰＣ回路３２に接続されている。処理部４４は、ＤＡ回路２８にＷＲＤＡ１信号を設定する。ＤＡ回路２８によってアナログ変換されたＷＲＤＡ１信号を受けたＡＰＣ回路３２は、レーザダイオード１０の出力パワーがデータの消去に適したパワーＦＭＤ＿Ｗ（図４のＣ点）となるように第２電圧出力回路１６の制御電圧を定電力制御する。このとき、第２電圧出力回路１６から出力されている制御電圧ＶＷＤＣ＿ＷをＡＤコンバータによって取得する。
【００６０】
続いて、ＥＦＭＧ信号を“Ｌレベル”とし、第２電圧出力回路１６の制御をＡＣＣ回路３４による定電流制御に切り替える。処理部４４は、ＡＤコンバータによって第２電圧出力回路１６から出力される制御電圧を読み取りながら、その制御電圧が電圧値ＶＷＤＣ＿ＷとなるようにＤＡ回路３８の設定値を調整する。調整後のＤＡ回路３８の設定値が従来のＷＤＡＣ２信号となる。ＷＤＡＣ２’信号は、ＷＤＡＣ２信号から電圧差ΔＶＲを引いた値とする。
【００６１】
以上のように求められたＷＤＡＣ２’信号をデータの再生を行うフレームが終了する前にＤＡ回路３８に設定すると、第２電圧出力回路１６の制御がＡＣＣ回路３４からＡＰＣ回路３２に切り替えられる前に第２電圧出力回路１６の制御電圧をＷＤＡＣ２’信号に対応する電圧値まで予備的に昇圧しておくことができる。このときの第２電圧出力回路１６からの制御電圧はデータの消去に適した制御電圧ＶＷＤＣ＿Ｗから制御電圧ＶＲＤＣ＿Ｒと制御電圧ＶＲＤＣ＿Ｗとの差を引いた値となり、従来のＷＤＡＣ２信号に対応する電圧値に比べて電圧差ΔＶＲ分に相当する値だけ低い電圧値となる。この差は、ＡＰＣ回路２２からＡＣＣ回路２４に切り替えられた際の第１電圧出力回路１４の制御電圧の差に相当する。従って、ＡＣＣ回路２４に切り替えられた第１電圧出力回路１４からの制御電圧の変動は、ＡＰＣ回路３２によって定電力制御される第２電圧出力回路１６からの制御電圧によって吸収されることとなり、レーザダイオード１０の異常な出力を抑制することができる。
【００６２】
以上のように、本実施の形態によれば、データの再生からデータの消去又は記録に移行する際に、レーザダイオードの出力を安定化させることができる。その結果、データの記録品位の低下を抑制すると共に、光ディスク装置のサーボ制御の破綻を防ぐことができる。
【００６３】
なお、本発明の光ディスク装置及び光ディスクの制御方法は、上記実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内において変更を加えた態様とすることができる。
【００６４】
【発明の効果】
本発明によれば、光ディスク装置においてデータの再生時からデータの消去又は記録時に移行する際のレーザダイオードの異常な出力を防ぐことができる。その結果、例えば、データの記録品質の低下を防ぐことができ、光ディスク装置のサーボ破綻を抑制することができる。
【図面の簡単な説明】
【図１】光ディスク装置の構成を示すブロック図である。
【図２】光ディスク装置のＬＤドライバの構成を示す図である。
【図３】本発明の実施の形態における光ディスク装置の制御のタイミングチャートを示す図である。
【図４】本発明の実施の形態におけるＤＡ回路の設定値の取得方法を説明する図である。
【図５】従来の光ディスク装置の制御におけるタイミングチャートを示す図である。
【図６】従来のＤＡ回路の設定値の取得方法を説明する図である。
【符号の説明】
１０ レーザダイオード、１２ ＬＤドライバ、１４ 第１電圧出力回路、１６ 第２電圧出力回路、１８ 増幅器、２０，２６，２８，３６，３８ デジタル／アナログ変換回路（ＤＡ回路）、２２，３２ 定電力制御回路（ＡＰＣ回路）、２４，３４ 定電流制御回路（ＡＣＣ回路）、３０，４０ サンプル／ホールド回路（Ｓ／Ｈ回路）、４２ ＥＮＤＥＣ、４４ 処理部、４６ 切替タイミング回路、４８ ＦＭＤ回路、５０ 第１電流源、５２ 第２電流源、５４ 第３電流源、６０ 温度測定回路。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an optical disk device capable of performing servo control stably and a control method of the optical disk device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, optical disk devices such as a CD-R capable of recording data and a CD-RW capable of recording and erasing data have been widely used.
[0003]
Recording of data in such an optical disk device is performed by irradiating a laser beam to an organic dye material as a recording material and burning a recording mark (pit). Reproduction of data is performed by irradiating a recording mark recorded on the recording surface of the disk with laser light and detecting its reflection. At this time, the laser light is applied to the recording surface of the disk through the lens, and it is necessary to perform focus servo control for controlling the lens position so as to be in an optimal state for recording or reproduction.
[0004]
In addition, in order to reproduce, erase, and record data at an accurate position on the disk, the guide groove is accurately traced using reflection of a laser beam from a guide groove (Groove) previously engraved on the disk. It is also necessary to perform tracking servo control for controlling the lens position in such a manner as to perform the above.
[0005]
Further, it is necessary to detect the optimum laser beam power for data reproduction, erasure, and recording, and perform each of the reproduction, erasure, and recording processes while maintaining the optimum power by constant current control or constant power control. .
[0006]
As shown in FIG. 1, a conventional optical disk device includes a laser diode (LD) 10, a laser diode driver (LD driver) 12, a first voltage output circuit 14, a second voltage output circuit 16, an amplifier 18, a constant power control circuit. (APC circuits) 22, 32, constant current control circuits (ACC circuits) 24, 34, a plurality of digital / analog conversion circuits (DA circuits) 20, 26, 28, 36, 38, a plurality of sample / hold circuits (S / H) Circuit) 30 and 40. Further, a processing unit 44 for controlling these circuits and an ENDEC 42 for controlling a signal for switching each switch and the like are also included. Further, an FMD circuit 48 for detecting the output power of the laser diode 10 by a photoelectric conversion element such as a photodiode and outputting a feedback signal is provided.
[0007]
The first voltage output circuit 14 is connected to the APC circuit 22 or the ACC circuit 24 via the switch SW1. The APC circuit 22 is connected to the DA circuit 26 and the S / H circuit 30, and the ACC circuit 24 is connected to the DA circuit 28. The DA circuits 26 and 28 are connected to the processing unit 44. The S / H circuit 30 is connected to the FMD circuit 48.
[0008]
Similarly, the second voltage output circuit 16 is connected to the APC circuit 32 or the ACC circuit 34 via the switch SW2. The APC circuit 32 is connected to a DA circuit 36 and an S / H circuit 40, and the ACC circuit 34 is connected to a DA circuit 38. Further, the DA circuits 36 and 38 are connected to the processing unit 44. The S / H circuit 40 is connected to the FMD circuit 48.
[0009]
The amplifier 18 is connected to the DA circuit 20, and the DA circuit 20 is connected to the processing unit 44.
[0010]
As shown in FIG. 2, the first voltage output circuit 14, the second voltage output circuit 16, and the amplifier 18 are connected to the first current source 50 and the second current source 52 included in the LD driver 12 via switches SW3 to SW5. And the third current source 54. Upon receiving a control voltage from the first voltage output circuit 14, the second voltage output circuit 16, or the amplifier 18, the first current source 50, the second current source 52, and the third current source 54 of the LD driver 12 are connected to the laser diode 10. Outputs drive current. When reproducing data, the current from the first current source 50, when erasing data, the combined current from the first current source 50 and the second current source 52, and when recording data, from the first current source 50 and the third current source 54. The laser diode 10 is caused to emit light by the combined current, and data is reproduced, erased, or recorded.
[0011]
FIG. 5 shows a timing chart when reproducing, erasing, and recording data on the disk. The optical disk device reads an ATIP reference signal (ATIPSYNC) engraved on the disk, and starts processing of each frame in synchronization with the rise of the ATIP reference signal. In the example of the timing chart, the reproduction of the data of the disk is performed in the first frame, and thereafter, the processing shifts to the erasing and recording of the data of the disk from the second frame.
[0012]
In the first frame, the EFMG signal output from the switching timing circuit 46 is set to “L level”, and the switch SW1 is connected to the a1 side and the switch SW2 is connected to the b2 side corresponding to the EFMG signal. As a result, the first voltage output circuit 14 is controlled by the APC circuit 22, and the second voltage output circuit 16 is controlled by the ACC circuit 34. The LDON signal is constantly output from the ENDEC 42, the switch SW3 is closed, and the first voltage output circuit 14 and the LD driver 12 are connected.
[0013]
In order to reproduce data, the processing unit 44 outputs a REDA signal to the DA circuit 26. The DA circuit 26 receives the REDA signal from the processing unit 44, converts the REDA signal from digital to analog, and outputs it to the APC circuit 22. The APC circuit 22 receives the REDA signal converted from the DA circuit 26 into an analog signal, and causes the first voltage output circuit 14 to output the control voltage VRDC_R to the LD driver 12. The LD driver 12 receives the control voltage VRDC_R, outputs a drive current from the first current source 50 to the laser diode 10, and causes the laser diode 10 to emit light. The pits or lands on the disk are read by the output of the laser diode 10 to reproduce data.
[0014]
Here, the output power of the laser diode 10 is read by the FMD circuit 48 and fed back to the S / H circuit 30 as a feedback signal. While data is being read from the disk, the ENDEC 42 outputs the RAPC signal as "H level" to the S / H circuit 30, and causes the S / H circuit 30 to sample and hold the feedback signal. The sampled value is output to the APC circuit 22. Based on the sampled value, the APC circuit 22 controls the first voltage output circuit 14, and during data reproduction, the power of the laser diode 10 is changed to a constant power determined by the REDA signal. Thus, the control voltage from the first voltage output circuit 14 is adjusted. The output power of the laser diode 10 controlled by the APC is set to a power value FMD_R.
[0015]
On the other hand, before shifting from a frame in which data is reproduced to a frame in which data is erased or recorded, the processing unit 44 outputs a WDAC2 signal to the DA circuit 38 to control the control voltage output from the second voltage output circuit 16. In advance. This is because when the second voltage output circuit 16 is switched from the constant current control by the ACC circuit 34 to the constant power control by the APC circuit 32, the delay in following the control voltage output from the second voltage output circuit 16 is reduced. This is for suppressing.
[0016]
As shown in FIG. 6, the set value of the WRDAC2 signal is obtained in advance from the relationship between the control voltage of the second voltage output circuit 16 and the output power of the laser diode 10 read by the FMD circuit 48.
[0017]
First, the EFMG signal is set to “H level”, the second voltage output circuit 16 is connected to the APC circuit 32, and the processing unit 44 outputs the set value Y1 to the DA circuit 36. The APC circuit 32 receives the set value Y1 from the DA circuit 36 and the feedback signal from the FMD circuit 48, and causes the second voltage output circuit 16 to output a constant control voltage V1 defined by the set value Y1. The LD driver 12 receives the control voltage V1 and supplies a drive current from the second current source 52 to the laser diode 10 according to the control voltage V1. The laser diode 10 receives a drive current from the first current source 50 receiving the control voltage value VRDC_W from the first voltage output circuit 14 controlled by the ACC circuit 24, and a drive current from the second current source 52 receiving the control voltage V1. It emits light by the combined current with the driving current of. At this time, the output of the laser diode 10 read by the FMD circuit 48 is defined as power W1. The relationship between the set value Y1 of the DA circuit 36, the control voltage value V1 from the second voltage output circuit 16, and the output power W1 of the laser diode 10 is shown by point A in FIG.
[0018]
Similarly, the set value Y2 is output from the processing unit 44 to the DA circuit 36, and the control voltage value V2 and the output power W2 of the laser diode 10 are obtained from the second voltage output circuit 16 at that time (point B in FIG. 6). At this time, since the output powers W1 and W2 of the laser diode 10 are finally used to interpolate the set values to the DA circuits 36 and 38, the output powers W1 and W2 are set to values close to the output power suitable for erasing or recording data. It is desirable that the output of the laser diode 10 be set within a range that can be approximated by a straight line. For example, when a disk using phase change is targeted, it is preferable to select from a range of 10 mW to 20 mW. Further, the temperature T1 of the laser diode 10 at this time is measured by the temperature measurement circuit 60.
[0019]
Next, the EFMG signal is set to “L level”, the second voltage output circuit 16 is connected to the ACC circuit 34, and the processing unit 44 outputs the set value Y3 to the DA circuit 38. The ACC circuit 34 receives the output of the set value Y3 from the DA circuit 38 and performs control so that the control voltage from the second voltage output circuit 16 becomes a constant value defined by the set value Y3. At this time, the set value Y3 is adjusted so that the control voltage output from the second voltage output circuit 16 becomes equal to the voltage value V1, and the set value Y3 at that time is obtained.
[0020]
Similarly, using the ACC circuit 34, a set value Y4 at which the control voltage output from the second voltage output circuit 16 becomes equal to the voltage value V2 is obtained. The temperature T2 of the laser diode 10 at this time is obtained by the temperature measurement circuit 60.
[0021]
Assuming that the output of the laser diode 10 suitable for erasing data is the power FMD_W, the set value WDAC1 set in the DA circuit 36 can be calculated by the relational expression (1). The relational expression (1) is for linearly approximating the output of the laser diode 10 based on the powers W1 and W2 obtained above, and calculating a set value WDAC1 at which the output power WE is output.
[0022]
(Equation 1)

[0023]
Further, before shifting from the data reproduction frame to the data erasing or recording frame, the set value WDAC2 set in the DA circuit 38 can be calculated using the relational expression (2).
[0024]
(Equation 2)

[0025]
As described above, the value of the set value WDAC2 can be determined. In the constant current control by the ACC circuit 34, since the actual output power of the laser diode 10 is not used for feedback, the relationship between the set value WDAC2 and the output power of the laser diode 10 is affected by the temperature of the laser diode 10. Easy to fluctuate. Therefore, when the measured temperature T2 of the laser diode 10 is not within the predetermined temperature range with respect to the measured temperature T1, the above processing is performed again, and the relational expressions (1) and (2) are obtained again to obtain the set values WDAC1 and WDAC2. Is calculated.
[0026]
Next, in synchronization with ATIPSYNC, the process shifts to a second frame in which data is erased and recorded. The switching timing circuit 46 lowers the EFMG signal in response to the rise of ATIPSYNC, and switches the switch SW1 to the b1 side and the switch SW2 to the a2 side.
[0027]
The processing unit 44 outputs a WRDA signal to the DA circuit 28. The DA circuit 28 converts the WRDA signal from digital to analog and outputs it to the ACC circuit 24. The ACC circuit 24 receives the analog-converted WRDA signal, causes the first voltage output circuit 14 to output a control voltage defined by the WRDA signal, and outputs a drive current output from the first current source 50 of the LD driver 12. The constant current control is performed so as to be maintained at a constant current value determined by the WRDA signal. At this time, the drive current determined by the WRDA signal determines the base power (bottom power) during data recording, and has a current value such that the laser diode 10 does not emit light. At this time, the control voltage output from the first voltage output circuit 14 is referred to as a voltage value VRDC_W (VRDC at the time of recording).
[0028]
On the other hand, the processing unit 44 outputs a WDAC1 signal to the DA circuit 36. The DA circuit 36 converts the WDAC1 signal from digital to analog and outputs it to the APC circuit 32. The APC circuit 32 receives the analog-converted WDAC1 signal and outputs it from the second voltage output circuit 16 so that the output power from the laser diode 10 becomes a power suitable for erasing data on the disk. Control the control voltage. The output power of the laser diode 10 is read by the FMD circuit 48 and output to the S / H circuit 40 as a feedback signal. The ENDEC 42 outputs a WAPC signal in synchronization with the data erasing timing, and causes the S / H circuit 40 to sample and hold the feedback signal from the FMD circuit 48. The APC circuit 32 receives this sampling value, and performs feedback control of the control voltage output from the second voltage output circuit 16 so that the power of the laser diode 10 at the time of erasing is maintained at a constant value determined by the WDAC1 signal.
[0029]
At the same time, the ENDEC 42 causes the S / H circuit 30 to sample and hold the feedback signal from the FMD circuit 48 by outputting the RAPC signal when erasing data. The APC circuit 22 receives this sampling value and adjusts the output power of the laser diode 10 to a value suitable for reproduction when the optical disk device is switched to data reproduction processing.
[0030]
The ENDEC 42 outputs a PEO signal at the timing of erasing data on the disk. As a result, the switch SW4 is closed, and the second voltage output circuit 16 and the LD driver 12 are connected. The combined current of the current from the first current source 50 of the LD driver 12 controlled by the ACC circuit 24 and the current from the second current source 52 of the LD driver 12 controlled by the APC circuit 32 drives the laser diode 10. It is output as a current and the data on the disk is erased. At this time, the control voltage of the second voltage output circuit 16 is a voltage value VWDC_W (VWDC at the time of recording), and the output power from the laser diode 10 is a power value FMD_W.
[0031]
When recording data on the disk, the processing unit 44 sets the DA circuit 20 to output the voltage value VWDC_W. The amplifier 18 outputs a control voltage obtained by amplifying the voltage value VWDC_W by the amplification factor ATT.
[0032]
The ENDEC 42 outputs a PWO signal at the timing of recording data on the disk, and connects the amplifier 18 and the LD driver 12 by closing the switch SW5. Thus, the current from the first current source 50 of the LD driver 12 controlled by the ACC circuit 24 and the current from the third current source 54 controlled by the control voltage VWDC_W having a voltage value VWDC_W × amplification factor ATT times. The combined current is supplied to the laser diode 10 as a drive current, and data is recorded on the disk.
[0033]
[Problems to be solved by the invention]
In the above-described conventional technique, before shifting from a frame in which data is reproduced to a frame in which data is erased or recorded, a WDAC2 signal is output to an ACC circuit 34 connected to the second voltage output circuit 16 to output data. After performing the advance control of the power so that a laser output suitable for erasing or recording is obtained, the control of the second voltage output circuit 16 is switched from the constant current control by the ACC circuit 34 to the constant power control by the APC circuit 32.
[0034]
However, when shifting from a frame in which data is reproduced to a frame in which data is erased or recorded, the first voltage output circuit 14 is also switched from constant power control by the APC circuit 22 to constant current control by the ACC circuit 24. It takes time for the control voltage from the first voltage output circuit 14 to stabilize from the voltage value VRDC_R to the voltage value VRDC_W. Therefore, the initial power of the laser diode 10 is not stable at the beginning of the start of a frame for erasing or recording data. As shown in FIG. 5, the laser output when erasing data on the disk is indicated by a two-dot chain line. And the laser output at the time of recording data on the disk changes as shown by the dashed line, which causes a problem that extra power is output.
[0035]
Due to the abnormal output from the laser diode 10, the quality of data erasure and recording on the disk is degraded. At the same time, it becomes difficult to obtain a control signal for performing servo control of the optical disk device, which causes a breakdown of servo control. Further, since the laser output becomes unnecessarily high, the characteristics of the laser diode are degraded and the life of the laser diode is shortened.
[0036]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the related art, and provides at least one of the above-described problems in providing an optical disk device and a control method of the optical disk device that can stably output a laser diode during a transition period. Aim.
[0037]
[Means for Solving the Problems]
The present invention that can solve the above problems includes a first control signal output unit that outputs a first control signal, and a second control signal output unit that outputs a second control signal. What is claimed is: 1. An optical disk device for controlling data output of a light emitting element based on a second control signal to reproduce, erase, or record data, wherein the data is reproduced by controlling the first control signal output means. Constant power control means for outputting a first control value as the first control signal so that the output power of the first control signal is maintained constant, and the first control signal output means for erasing or recording data. And a first constant current control unit that outputs a second control value as the first control signal so that at least a part of the current flowing through the light emitting element is maintained constant. The second control signal A second constant current control means for controlling a force means to output a third control value as the second control signal so that at least a part of a current flowing to the light emitting element is maintained constant; At the time of recording, a second constant power control means for controlling the second control signal output means to output a fourth control value as the second control signal so that the output power of the light emitting element is kept constant. Switching the control of the first control signal output means from the first constant power control means to the first constant current control means, and changing the control of the second control signal output means to the second constant current Switching means for switching from the control means to the second constant power control means, wherein the control of the second control signal output means is performed by the switching means from the second constant current control means to the second constant power control means. Before switching to control means , Characterized in that to output the second minus the difference between the second control value and the first control value from said fourth control value as said second control signal from the control signal output means.
[0038]
Another embodiment of the present invention is a method for controlling an optical disc apparatus for reproducing, erasing, or recording data by controlling an output of a light emitting element based on first and second control signals. At this time, a first control value is output as the first control signal so that the output power of the light emitting element is kept constant, and the first control value is output so that at least a part of the current flowing through the light emitting element is kept constant. A first step of outputting a third control value as a second control signal, and the first control signal such that at least a part of a current flowing through the light emitting element is kept constant during data erasing or recording. Outputting a second control value, and outputting a fourth control value as the second control signal so that the output power of the light emitting element is kept constant. Move to the second step Before, it characterized by having a step of outputting a value obtained by subtracting the difference between the second control value and the first control value from said fourth control value as the second control signal.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The optical disk device according to the embodiment of the present invention has the same configuration as the conventional optical disk device shown in FIGS.
[0040]
FIG. 3 shows a timing chart at the time of reproducing, erasing, and recording data on the disk in the present embodiment. In the example of the timing chart, the reproduction of the data of the disc is performed in the first frame, and thereafter, the operation shifts to the erasing and recording of the data in the second frame.
[0041]
In the first frame, the EFMG signal output from the switching timing circuit 46 is at “L level”, the switch SW1 is connected to the a1 side, and the switch SW2 is connected to the b2 side. Therefore, the first voltage output circuit 14 is controlled by the APC circuit 22, and the second voltage output circuit 16 is controlled by the ACC circuit 34. The LDON signal is constantly output from the ENDEC 42, the switch SW3 is closed, and the first voltage output circuit 14 and the LD driver 12 are connected.
[0042]
In reproducing the data of the first frame, the drive current of the laser diode 10 is controlled in the same manner as in the related art. That is, the processing unit 44 sets the REDA signal to the DA circuit 26. On the other hand, the output power of the laser diode 10 is read out by the FMD circuit 48, and the sampling value is fed back to the APC circuit 22, whereby the output power of the laser diode 10 is maintained at a constant value defined by the REDA signal. At this time, the control voltage output from the first voltage output circuit 14 is the voltage value VRDC_R.
[0043]
For example, in the case of a disk using a phase change, the voltage value VRDC_R of the control voltage is adjusted so that read power P _RD : 1 mW is obtained for data reproduction.
[0044]
On the other hand, while reproducing the data, the ENDEC 42 maintains the PEO signal and the PWO signal at the “L level” and outputs them. Thereby, SW4 and SW5 are opened, and the second voltage output circuit 16 and the amplifier 18 are disconnected from the LD driver 12.
[0045]
In the optical disk device of the present embodiment, the processing unit 44 sets the WDAC2 'signal to the DA circuit 38 before shifting from the frame for reproducing data to the frame for erasing and recording data. The DA circuit 38 converts the WDAC2 ′ signal from digital to analog and outputs the signal to the ACC circuit 34. The ACC circuit 34 receives the analog-converted WDAC 2 ′ signal and controls the second voltage output circuit 16 to output a control voltage defined by the WDAC 2 ′ signal. A method of obtaining the set value of the WDAC2 'signal will be described later in detail.
[0046]
When the reproduction of the data from the disk is completed, the process shifts to the second frame in which the data is erased and reproduced in synchronization with the rise of ATIPSYNC. The switching timing circuit 46 raises the EFMG signal to “H level” in response to the rise of ATIPSYNC, connects the switch SW1 to the b1 side, and connects the switch SW2 to the a2 side. As a result, the first voltage output circuit 14 is controlled by the ACC circuit 24 at a constant current, and the second voltage output circuit 16 is controlled by the APC circuit 32 at a constant power.
[0047]
The processing unit 44 outputs a WRDA signal to the DA circuit 28. The WRDA signal is converted to an analog signal and output to the ACC circuit 24. The ACC circuit 24 receives the WRDA signal and performs constant current control on the first voltage output circuit 14. At this time, the control voltage output from the first voltage output circuit 14 is set so that the drive current from the first current source 50 of the LD driver 12 that has received the control voltage is a current that does not cause the laser diode 10 to emit light. Controlled. The switch SW3 is closed by the LDON signal which is always at the “H level”, and the drive current is output to the laser diode 10 from the first current source 50 of the LD driver 12 receiving the control voltage from the first voltage output circuit 14. You.
[0048]
Immediately after the control of the first voltage output circuit 14 is switched from the constant power control by the APC circuit 22 to the constant current control by the ACC circuit 24, the control voltage output from the first voltage output circuit 14 is The voltage value decreases from the voltage value VRDC_R toward the voltage value VRDC_W at the time of the constant current control, and finally stabilizes at the control voltage VRDC_W defined by the WRDA signal. With such a change in the control voltage, the drive current output from the first current source 50 of the LD driver 12 also decreases.
[0049]
On the other hand, the processing unit 44 outputs a WDAC1 signal to the DA circuit 36. The DA circuit 36 converts the WDAC1 signal from digital to analog and outputs the signal to the APC circuit 32. The output power of the laser diode 10 is read by the FMD circuit 48, and the sampling value is fed back to the APC circuit 32. The APC circuit 32 controls the output power of the laser diode 10 to a constant power specified by the WDAC1 signal.
[0050]
When erasing data, the PEO signal is set to “H” level in synchronization with the timing of erasing data by the ENDEC 42, and the switch SW4 is closed to change the control voltage value VWDC_W from the second voltage output circuit 16 to the LD driver. Input to 12. As a result, a drive current corresponding to the control voltage value VWDC_W is supplied from the second current source 52 of the LD driver 12. The laser diode 10 emits light by the combined current of the drive currents from the first current source 50 and the second current source 52, and the data on the disk is erased.
[0051]
When recording data on the disk, the processing unit 44 sets the DA circuit 20 to output the voltage value VWDC_W. The amplifier 18 outputs a control voltage obtained by amplifying the voltage value VWDC_W by the amplification factor ATT. Further, the amplifier 18 and the LD driver 12 are connected by closing the switch SW5 in synchronization with the timing of recording data based on the PWO signal of the ENDEC 42. The third current source 54 of the LD driver 12 receives a control voltage from the amplifier 18 and supplies a drive current defined by the control voltage to the laser diode 10. As a result, the laser diode 10 emits light by the combined current of the drive current from the first current source 50 and the drive current from the third current source 54, and data is recorded on the disk by the output of the laser diode 10. .
[0052]
For example, in a disk using a phase change, the voltage values VRDC_W and VWDC_W are adjusted such that an erase power P _{ER of} 5 mW and a write power P _{WR of} 11 mW are obtained.
[0053]
At this time, by setting the WDAC2 ′ signal to the DA circuit 38 before the end of the data reproduction frame, the control voltage of the second voltage output circuit 16 has been boosted to an appropriate value in advance, and the first voltage output circuit 14 As a result, the control voltage of the second voltage output circuit 16 is boosted so as to cancel the fluctuation of the output, and the output power of the laser diode 10 is maintained at the power specified by the WDAC1 signal. As a result, fluctuations in the output power of the laser diode 10 immediately after the start of the frame can be minimized.
[0054]
<Method of calculating set value of WRDAC2 ′ signal>
The set value of the WRDAC2 'signal is, as shown in FIG. 4, a relationship between the control voltage of the first voltage output circuit 14, the control voltage of the second voltage output circuit 16, and the output power of the laser diode 10 read by the FMD circuit 48. Can be obtained from
[0055]
First, the EFMG signal is set to “L level”, and the first voltage output circuit 14 and the APC circuit 22 are connected. The processing unit 44 outputs the set value REDA to the DA circuit 26. By the constant power control of the APC circuit 22 receiving the set value REDA from the DA circuit 26 and the feedback signal from the FMD circuit 48, a constant control voltage VRDC_R defined by the set value REDA is output from the first voltage output circuit 14. You. At this time, the control voltage VRDC_R is obtained by the AD converter.
[0056]
The LD driver 12 receives the control voltage VRDC_R and supplies a drive current according to the control voltage VRDC_R to the laser diode 10 from the first current source. The laser diode 10 emits light by the driving current from the first current source 50. The output power FMD_R of the laser diode 10 at this time is obtained by the FMD circuit 48.
[0057]
The relationship between the set value REDA of the DA circuit 26, the control voltage VRDC_R from the first voltage output circuit 14, and the output power FMD_R of the laser diode 10 is shown by point A in FIG.
[0058]
Next, the EFMG signal is set to “H level” and the first voltage output circuit 14 and the ACC circuit 24 are connected. While reading the control voltage from the first voltage output circuit 14 using the AD converter, the processing unit 44 adjusts the set value of the DA circuit 28 so that the control voltage of the first voltage output circuit 14 becomes the voltage value VRDC_R. . The set value of the DA circuit 28 at this time is WRDA_1. Further, while reading the output power of the laser diode 10 using the FMD circuit 48, the setting value of the DA circuit 28 is adjusted so that the laser diode 10 does not emit any light (point B in FIG. 4). The set value of the DA circuit 28 at this time is WRDA_2. Thereby, the potential difference ΔVR between the set value WRDA_1 and the set value WRDA_2 can be obtained.
[0059]
On the other hand, since the EFMG signal is at “H level”, the second voltage output circuit 16 is connected to the APC circuit 32. The processing unit 44 sets the WRDA1 signal in the DA circuit 28. The APC circuit 32, which has received the WRDA1 signal analog-converted by the DA circuit 28, sets the second voltage output circuit 16 so that the output power of the laser diode 10 becomes the power FMD_W (point C in FIG. 4) suitable for erasing data. Is controlled at a constant power. At this time, the control voltage VWDC_W output from the second voltage output circuit 16 is obtained by the AD converter.
[0060]
Subsequently, the EFMG signal is set to “L level”, and the control of the second voltage output circuit 16 is switched to the constant current control by the ACC circuit 34. While reading the control voltage output from the second voltage output circuit 16 by the AD converter, the processing unit 44 adjusts the set value of the DA circuit 38 so that the control voltage becomes the voltage value VWDC_W. The set value of the DA circuit 38 after the adjustment becomes the conventional WDAC2 signal. The WDAC2 ′ signal has a value obtained by subtracting the voltage difference ΔVR from the WDAC2 signal.
[0061]
If the WDAC2 ′ signal obtained as described above is set in the DA circuit 38 before the end of the frame for reproducing data, the control of the second voltage output circuit 16 is performed before the control of the second voltage output circuit 16 is switched from the ACC circuit 34 to the APC circuit 32. The control voltage of the second voltage output circuit 16 can be preliminarily boosted to a voltage value corresponding to the WDAC2 'signal. At this time, the control voltage from the second voltage output circuit 16 becomes a value obtained by subtracting the difference between the control voltage VRDC_R and the control voltage VRDC_W from the control voltage VWDC_W suitable for erasing data, and becomes a voltage value corresponding to the conventional WDAC2 signal. The voltage value becomes lower by a value corresponding to the voltage difference ΔVR. This difference corresponds to the difference between the control voltages of the first voltage output circuit 14 when switching from the APC circuit 22 to the ACC circuit 24. Therefore, the fluctuation of the control voltage from the first voltage output circuit 14 switched to the ACC circuit 24 is absorbed by the control voltage from the second voltage output circuit 16 controlled by the APC circuit 32 at a constant power, and An abnormal output of the diode 10 can be suppressed.
[0062]
As described above, according to the present embodiment, it is possible to stabilize the output of the laser diode when transitioning from data reproduction to data erasure or recording. As a result, it is possible to prevent the data recording quality from deteriorating and to prevent the servo control of the optical disk device from being broken.
[0063]
It should be noted that the optical disk device and the optical disk control method of the present invention are not limited to the above-described embodiment, but may be modified without departing from the scope of the present invention.
[0064]
【The invention's effect】
According to the present invention, it is possible to prevent an abnormal output of the laser diode when the optical disk apparatus shifts from reproducing data to erasing or recording data. As a result, for example, a decrease in data recording quality can be prevented, and servo failure of the optical disk device can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an optical disk device.
FIG. 2 is a diagram illustrating a configuration of an LD driver of the optical disc device.
FIG. 3 is a diagram showing a timing chart of control of the optical disc device in the embodiment of the present invention.
FIG. 4 is a diagram illustrating a method for obtaining a set value of a DA circuit according to the embodiment of the present invention.
FIG. 5 is a diagram showing a timing chart in control of a conventional optical disk device.
FIG. 6 is a diagram illustrating a conventional method of acquiring a set value of a DA circuit.
[Explanation of symbols]
Reference Signs List 10 laser diode, 12 LD driver, 14 first voltage output circuit, 16 second voltage output circuit, 18 amplifier, 20, 26, 28, 36, 38 digital / analog conversion circuit (DA circuit), 22, 32 constant power control Circuit (APC circuit), 24, 34 constant current control circuit (ACC circuit), 30, 40 sample / hold circuit (S / H circuit), 42 ENDEC, 44 processing unit, 46 switching timing circuit, 48 FMD circuit, 50th 1 current source, 52 second current source, 54 third current source, 60 temperature measurement circuit.

Claims (2)

First control signal output means for outputting a first control signal;
Second control signal output means for outputting a second control signal,
An optical disc device for controlling data output of a light emitting element based on the first and second control signals to perform data reproduction and erasure or recording,
At the time of data reproduction, a first constant power for controlling the first control signal output means to output a first control value as the first control signal so that the output power of the light emitting element is kept constant. Control means;
When erasing or recording data, the first control signal output means is controlled to output a second control value as the first control signal so that at least a part of the current flowing through the light emitting element is kept constant. First constant current control means for causing
At the time of data reproduction, the second control signal output means is controlled to output a third control value as the second control signal so that at least a part of the current flowing through the light emitting element is kept constant. 2 constant current control means;
A second control signal output means for controlling the second control signal output means to output a fourth control value as the second control signal so that the output power of the light emitting element is kept constant during data erasing or recording; Constant power control means,
The control of the first control signal output means is switched from the first constant power control means to the first constant current control means, and the control of the second control signal output means is controlled by the second constant current control means Switching means for switching from the first constant power control means to the second constant power control means;
Including
Before the control of the second control signal output means is switched from the second constant current control means to the second constant power control means by the switching means, the second control signal output means outputs the second control signal. An optical disk device for outputting a value obtained by subtracting a difference between the first control value and the second control value from the fourth control value as the control signal. A method for controlling an optical disk device for reproducing, erasing, or recording data by controlling an output of a light emitting element based on first and second control signals,
During data reproduction, a first control value is output as the first control signal so that the output power of the light emitting element is kept constant, and at least a part of the current flowing through the light emitting element is kept constant. A first step of outputting a third control value as the second control signal;
When erasing or recording data, a second control value is output as the first control signal so that at least a part of the current flowing through the light emitting element is kept constant, and the output power of the light emitting element is kept constant A second control signal to output a fourth control value as the second control signal,
Before shifting from the first step to the second step, a value obtained by subtracting a difference between the first control value and the second control value from the fourth control value is output as the second control signal. A method for controlling an optical disk device, comprising a step of causing the optical disk device to perform a control.

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