JP2004318996A - Optical disk device and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method of an optical disk device capable of stably controlling an output of a laser diode for a transition period. <P>SOLUTION: The control method of an optical disk device which comprises a first voltage output circuit 14 for outputting a first control signal and a second voltage output circuit 16 for outputting a second control signal, and which controls an output of a light emitting element based on the first control signal in reproducing data and controls an output of the light emitting element based on the first control signal at the time of erasing or recording data, and the method comprises, in reproducing data, a process for performing constant power control of the first voltage output circuit 14 and also performing constant current control so that the control signal outputted from the second voltage output circuit 16 is almost equal to a value in erasing or recording data, and comprises, in erasing or recording data, a process for performing constant current control of the first voltage output circuit 14 and also performing constant power control of the second voltage output circuit 16. As a result, for example, the recording quality of the data can be prevented from deteriorating, and servo failure of the optical disk device can be suppressed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【００２３】
また、データの再生のフレームからデータの消去又は記録を行うフレームに移行する前に、ＤＡ回路３８に設定する設定値ＷＤＡＣ２は関係式（２）を用いて算出することができる。
【００２４】
【数２】

【００２５】
以上のように、設定値ＷＤＡＣ２の値を定めることができる。なお、ＡＣＣ回路３４による定電流制御では、実際のレーザダイオード１０の出力電力をフィードバックに利用していないため、レーザダイオード１０の温度の影響により設定値ＷＤＡＣ２とレーザダイオード１０の出力電力との関係が変動し易い。従って、レーザダイオード１０の測定温度Ｔ２が測定温度Ｔ１に対して所定の温度範囲内にない場合には、上記処理をやり直し、関係式（１）及び（２）を再度求めて設定値ＷＤＡＣ１及びＷＤＡＣ２を算出する。
【００２６】
次に、ＡＴＩＰＳＹＮＣに同期して、データの消去及び記録を行う第２フレームに移行する。切替タイミング回路４６は、ＡＴＩＰＳＹＮＣの立ち上がりに応じて、ＥＦＭＧ信号を“Ｈレベル”に立ち上げ、スイッチＳＷ１をｂ１側に、スイッチＳＷ２をａ２側に切り替える。
【００２７】
処理部４４は、ＤＡ回路２８にＷＲＤＡ信号を出力する。ＤＡ回路２８は、ＷＲＤＡ信号をデジタル／アナログ変換してＡＣＣ回路２４に出力する。ＡＣＣ回路２４は、アナログ変換されたＷＲＤＡ信号を受けて、このＷＲＤＡ信号で定められる制御電圧を第１電圧出力回路１４から出力させ、ＬＤドライバ１２の第１電流源５０から出力される駆動電流がＷＲＤＡ信号によって定められる一定の電流値に維持されるように定電流制御を行う。このとき、ＷＲＤＡ信号で定められる駆動電流は、データの記録中における基底パワー（ボトムパワー）を決定するものであり、レーザダイオード１０が光らない十分小さい電流値とされる。このとき、第１電圧出力回路１４が出力する制御電圧を電圧値ＶＲＤＣ＿Ｗ（記録時のＶＲＤＣ）という。
【００２８】
一方、処理部４４はＤＡ回路３６に対してＷＤＡＣ１信号を出力する。ＤＡ回路３６は、ＷＤＡＣ１信号をデジタル／アナログ変換してＡＰＣ回路３２に出力する。ＡＰＣ回路３２は、アナログ変換されたＷＤＡＣ１信号を受けて、レーザダイオード１０からの出力電力がディスク上のデータの消去を行うために適した電力となるように第２電圧出力回路１６から出力される制御電圧を制御する。レーザダイオード１０の出力パワーはＦＭＤ回路４８によって読み取られ、フィードバック信号としてＳ／Ｈ回路４０へ出力される。ＥＮＤＥＣ４２は、データの消去のタイミングに同期してＷＡＰＣ信号を出力し、ＦＭＤ回路４８からのフィードバック信号をＳ／Ｈ回路４０にサンプルホールドさせる。ＡＰＣ回路３２はこのサンプリング値を受けて、消去時のレーザダイオード１０のパワーがＷＤＡＣ１信号によって定められる一定値に維持されるように第２電圧出力回路１６から出力される制御電圧をフィードバック制御する。
【００２９】
同時に、ＥＮＤＥＣ４２は、データの消去時にＲＡＰＣ信号を出力することによって、ＦＭＤ回路４８からのフィードバック信号をＳ／Ｈ回路３０にサンプルホールドさせる。ＡＰＣ回路２２は、このサンプリング値を受けて、光ディスク装置がデータの再生処理に切り替えられた際にレーザダイオード１０の出力パワーが再生に適した値となるように調整を行う。
【００３０】
また、ＥＮＤＥＣ４２は、ディスク上のデータを消去するタイミングでＰＥＯ信号を出力する。これによって、スイッチＳＷ４が閉じられ、第２電圧出力回路１６とＬＤドライバ１２とが接続される。ＡＣＣ回路２４によって制御されたＬＤドライバ１２の第１電流源５０からの電流と、ＡＰＣ回路３２によって制御されたＬＤドライバ１２の第２電流源５２からの電流との合成電流がレーザダイオード１０の駆動電流として出力され、ディスク上のデータが消去される。このときの第２電圧出力回路１６の制御電圧を電圧値ＶＷＤＣ＿Ｗ１（記録時のＶＷＤＣ）とし、レーザダイオード１０からの出力電力を電力値ＦＭＤ＿Ｗとする。
【００３１】
また、ＡＴＴ回路２０には第２電圧出力回路１６から電圧値ＶＷＤＣ＿Ｗが設定され、電圧値ＶＷＤＣ＿Ｗ１を減衰率ＡＴＴだけ減衰させた電圧値が増幅器１８へ出力される。増幅器１８は、ＡＴＴ回路２０からの出力を受けて、レーザダイオード１０の出力がデータの消去時の電力値ＦＭＤ＿Ｗのε倍となるように増幅を行う。εの値は、個々のディスクに対して固有の値としてディスクのウォブルのＡＴＩＰに記録されており、ＡＴＩＰから読み出されて設定される。
【００３２】
ディスク上にデータを記録する際には、ＥＮＤＥＣ４２は、ディスク上にデータを記録するタイミングでＰＷＯ信号を出力し、スイッチＳＷ５を閉じることにより増幅器１８とＬＤドライバ１２とを接続する。これによって、ＡＣＣ回路２４によって制御されたＬＤドライバ１２の第１電流源５０からの電流と、増幅器１８の制御電圧によって制御された第３電流源５４からの電流との合成電流がレーザダイオード１０に駆動電流として供給され、ディクス上にデータが記録される。
【００３３】
【発明が解決しようとする課題】
上記従来技術では、データの再生を行うフレームからデータの消去又は記録を行うフレームに移行する前に、第２電圧出力回路１６に接続されたＡＣＣ回路３４に対してＷＤＡＣ２信号を出力してデータの消去又は記録に適したレーザ出力が得られるようにパワーの先出し制御を行った後に、第２電圧出力回路１６の制御がＡＣＣ回路３４による定電流制御からＡＰＣ回路３２による定電力制御に切り替えられる。
【００３４】
しかしながら、データの再生を行うフレームからデータの消去又は記録を行うフレームに移行する際には、第１電圧出力回路１４もＡＰＣ回路２２による定電力制御からＡＣＣ回路２４による定電流制御に切り替えられるため、第１電圧出力回路１４からの制御電圧が電圧値ＶＲＤＣ＿Ｒから電圧値ＶＲＤＣ＿Ｗに安定するまでに時間を要する。そのため、データの消去又は記録を行うフレームの開始初期において、レーザダイオード１０の基底パワーが安定せず、図５の２点鎖線に示すようにディスク上のデータを消去する際のレーザ出力が徐々に安定状態に向かって変化する。また、図５の１点鎖線で示すようにディスク上にデータを記録する際のレーザ出力が変動し、切り替え初期に余分なパワーが出力される問題が生ずる。
【００３５】
このレーザダイオード１０からの異常な出力によって、ディスク上のデータの消去及び記録の品質が低下する。同時に、光ディスク装置のサーボ制御を行うための制御信号の取得を困難にし、サーボ制御の破綻を招く原因となる。さらに、レーザ出力が不必要に高くなるためにレーザダイオード１０の特性を劣化させ、寿命を短くさせる問題も引き起こす。
【００３６】
本発明は、上記従来技術の問題を鑑み、少なくとも上記課題の１つを解決すべく、移行期間のレーザダイオードの出力を安定に行うことができる光ディスク装置及び光ディスク装置の制御方法を提供することを目的とする。
【００３７】
【課題を解決するための手段】
上記課題を解決できる本発明は、第１の制御信号を出力する第１の制御信号出力手段と、第２の制御信号を出力する第２の制御信号出力手段と、を含み、データの再生時において前記第１の制御信号に基づいて発光素子の出力を制御し、データの消去又は記録時において前記第２の制御信号に基づいて発光素子の出力を制御する光ディスク装置であって、データの再生時において、前記第１の制御信号出力手段を定電力制御する第１の定電力制御手段と、データの消去又は記録時において、前記第１の制御信号出力手段を定電流制御する第１の定電流制御手段と、データの再生時において、前記第２の制御信号出力手段を定電流制御する第２の定電流制御手段と、データの消去又は記録時において、前記第２の制御信号出力手段を定電力制御する第２の定電力制御手段と、前記第１の制御信号出力手段の制御を前記第１の定電力制御手段から前記第１の定電流制御手段に切り替え、前記第２の制御信号出力手段の制御を前記第２の定電流制御手段から前記第２の定電力制御手段に切り替える切替手段と、を含み、前記切替手段によって前記第２の制御信号出力手段の制御が前記第２の定電流制御手段から前記第２の定電力制御手段へと切り替えられる前に、前記第２の制御信号出力手段から出力される制御信号がデータの消去又は記録時における値と略等しい値になるように前記第２の制御信号出力手段を定電流制御することを特徴とする。
【００３８】
さらに、上記本発明の光ディスク装置において、前記光学素子を駆動するドライバと、データの消去又は記録時において前記ドライバと前記第１の制御信号出力手段との電気的接続を切るスイッチと、を有することが好適である。
【００３９】
また、上記課題を解決できる本発明の別の形態は、第１の制御信号を出力する第１の制御信号出力手段と、第２の制御信号を出力する第２の制御信号出力手段とを含み、データの再生時において前記第１の制御信号に基づいて発光素子の出力を制御し、データの消去又は記録時において前記第２の制御信号に基づいて発光素子の出力を制御する光ディスク装置の制御方法であって、データの再生時において、前記第１の制御信号出力手段を定電力制御すると共に、前記第２の制御信号出力手段から出力される制御信号がデータの消去又は記録時における値と略等しい値になるように定電流制御する工程と、データの消去又は記録時において、前記第１の制御信号出力手段を定電流制御すると共に、前記第２の制御信号出力手段を定電力制御する工程と、を含むことを特徴とする。
【００４０】
上記本発明の光ディスク装置の制御方法において、前記光ディスク装置は、前記光学素子を駆動するドライバを有し、前記ドライバと前記第１の制御信号出力手段とはスイッチを介して接続されており、データの再生時からデータの消去又は記録時に移行する際に、前記スイッチを用いて前記ドライバと前記第１の制御信号出力手段との電気的な接続を切る工程を有することが好適である。
【００４１】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して説明する。本発明の実施の形態における光ディスク装置は、図１及び図２に示した従来の光ディスク装置と同様の構成を含んでいる。
【００４２】
図３に、本実施の形態におけるディスク上のデータの再生、消去及び記録時のタイミングチャートを示す。このタイミングチャートの例では、第１フレームにおいてディスクのデータの再生が行われ、その後第２フレームにおいてデータの消去及び記録に移行する。
【００４３】
第１フレームでは、切替タイミング回路４６から出力されるＥＦＭＧ信号が“Ｌレベル”にあり、スイッチＳＷ１がａ１側に接続され、スイッチＳＷ２はｂ２側に接続される。従って、第１電圧出力回路１４はＡＰＣ回路２２によって制御され、第２電圧出力回路１６はＡＣＣ回路３４によって制御されることとなる。ＥＮＤＥＣ４２からはＬＤＯＮ信号が常時出力され、スイッチＳＷ３が閉じられ、第１電圧出力回路１４とＬＤドライバ１２が接続される。
【００４４】
第１フレームのデータの再生において、レーザダイオード１０の駆動電流は従来技術と同様に制御される。すなわち、処理部４４からＤＡ回路２６にＲＥＤＡ信号が設定される。一方、ＦＭＤ回路４８によってレーザダイオード１０の出力パワーが読み出され、そのサンプリング値がＡＰＣ回路２２にフィードバックされることによってレーザダイオード１０の出力パワーがＲＥＤＡ信号によって規定される一定値に維持される。このとき、第１電圧出力回路１４から出力される制御電圧は電圧値ＶＲＤＣ＿Ｒである。
【００４５】
例えば、相変化を利用したディスクを対象とした場合、データの再生にはリードパワーＰ_ＲＤ：１ｍＷが得られるように制御電圧の電圧値ＶＲＤＣ＿Ｒが調整される。
【００４６】
また、データを再生する間、ＥＮＤＥＣ４２はＰＥＯ信号及びＰＷＯ信号を“Ｌレベル”に維持して出力する。これによってＳＷ４及びＳＷ５は開放され、第２電圧出力回路１６及び増幅器１８がＬＤドライバ１２から切り離される。
【００４７】
本実施の形態の光ディスク装置では、データの再生を行うフレームからデータの消去及び記録を行うフレームに移行する際に、ＬＤドライバ１２から第１電圧出力回路１４を切り離すことが特徴的である。
【００４８】
データの再生を行うフレームの終了前に、処理部４４はＤＡ回路３８にＷＤＡＣ３信号を出力して、第２電圧出力回路１６から出力される制御電圧を先行的に昇圧する。これにより、データの再生時におけるＡＣＣ回路３４による定電流制御からデータの消去時及び記録時におけるＡＰＣ回路３２による定電力制御へと移行する際に第２電圧出力回路１６から出力される制御電圧の追従をスムーズに行うためである。
【００４９】
ＤＡ回路３８は、ＷＤＡＣ３信号を受けて、ＷＤＡＣ３信号をデジタル／アナログ変換してＡＣＣ回路３４へ出力する。ＡＣＣ回路３４は、アナログ変換されたＷＤＡＣ３信号を受けて、第２電圧出力回路１６からＷＤＡＣ３信号によって規定される制御電圧値ＶＷＤＣ＿Ｗ２が出力されるように制御を行う。制御電圧値ＶＷＤＣ＿Ｗ２は、レーザダイオード１０から電力値ＦＭＤ＿Ｗが出力されるときの制御電圧値である。
【００５０】
ＷＤＡＣ３信号、出力比ε及び減衰率ＡＴＴの設定値の算出方法については後に詳細に説明する。
【００５１】
この時点では、ＰＥＯ信号及びＰＷＯ信号は“Ｌレベル”に維持されているので、スイッチＳＷ４及びＳＷ５は開放されており、第２電圧出力回路１６及び増幅器１８からの制御電圧はＬＤドライバ１２には伝達されない。
【００５２】
ディスクからのデータの再生が終了すると、ＡＴＩＰＳＹＮＣの立ち上がりに同期してデータの消去及び記録を行う第２フレームに移行する。切替タイミング回路４６は、ＡＴＩＰＳＹＮＣの立ち上がりに応じてＥＦＭＧ信号を“Ｈレベル”に立ち上げ、スイッチＳＷ１をｂ１側に接続し、スイッチＳＷ２をａ２側に接続する。これによって、第１電圧出力回路１４はＡＣＣ回路２４によって定電流制御され、第２電圧出力回路１６はＡＰＣ回路３２によって定電力制御されることとなる。
【００５３】
また、ＥＮＤＥＣ４２はスイッチＳＷ３に対するＬＤＯＮ信号を“Ｌレベル”にして、第１電圧出力回路１４とＬＤドライバ１２とを切り離す。
【００５４】
処理部４４は、ＤＡ回路２８にＷＲＤＡ信号を出力する。ＷＲＤＡ信号はアナログ信号に変換されてＡＣＣ回路２４に出力される。ＡＣＣ回路２４は、ＷＲＤＡ信号を受けて第１電圧出力回路１４に対して定電流制御を行う。但し、ＬＤＯＮ信号は“Ｌレベル”とされており、スイッチＳＷ３は開かれているため、第１電圧出力回路１４からの制御電圧はＬＤドライバ１２へ伝達されず、第１電流源５０からレーザダイオード１０へは駆動電流が出力されない。
【００５５】
処理部４４は、ＤＡ回路３６に対してＷＤＡＣ４信号を出力する。ＤＡ回路３６は、ＷＤＡＣ４信号をデジタル／アナログ変換してＡＰＣ回路３２へ出力する。ＡＰＣ回路３２は、アナログ変換されたＷＤＡＣ４信号を受けて、レーザダイオード１０からの出力電力がディスク上のデータの消去に適した電力ＦＭＤ＿Ｗとなるように第２電圧出力回路１６の出力を制御する。
【００５６】
データの消去を行うときには、ＥＮＤＥＣ４２によってデータを消去するタイミングに同期させてＰＥＯ信号を“Ｈレベル”に設定し、スイッチＳＷ４を閉じることで第２電圧出力回路１６からの制御電圧値をＬＤドライバ１２に入力する。ＬＤドライバ１２では、第２電圧出力回路１６からの制御電圧値を受けて、第２電流源５２からレーザダイオード１０へ駆動電流が供給される。レーザダイオード１０はこの駆動電流により発光させられ、ディスク上のデータの消去が行われる。このとき、第１電圧出力回路１４とＬＤドライバ１２とは切り離されているので、レーザダイオード１０は第２電流源５２からの駆動電流のみで発光させられる。
【００５７】
レーザダイオード１０の出力パワーはＦＭＤ回路４８によって読み取られ、フィードバック信号としてＳ／Ｈ回路４０へ出力される。ＥＮＤＥＣ４２は、データ消去のタイミングに同期してＷＡＰＣ信号を出力し、フィードバック信号をＳ／Ｈ回路４０にサンプルホールドさせる。ＡＰＣ回路３２は、このサンプリング値を受けて、レーザダイオード１０の出力が電力値ＦＭＤ＿Ｗに維持されるように第２電圧出力回路１６から出力される制御電圧を制御する。このときの制御電圧がＶＷＤＣ＿Ｗ２である。
【００５８】
また、ディスク上にデータを記録する際には、ＥＮＤＥＣ４２によってデータを消去するタイミングに同期させて、ＰＷＯ信号を“Ｈレベル”に設定し、スイッチＳＷ５を閉じる。
【００５９】
ＡＴＴ回路２０は第２電圧出力回路１６からの制御電圧値ＶＷＤＣ＿Ｗ２を受けて、この制御信号を減衰率ＡＴＴだけ減衰させて増幅器１８へ出力する。増幅器１８は、ＡＴＴ回路２０からの出力を増幅してＬＤドライバ１２へ出力する。ＬＤドライバ１２の第３電流源５４は、増幅器１８からの制御電圧を受けて、その制御電圧によって規定される駆動電流をレーザダイオード１０に供給する。その結果、第３電流源５４からの駆動電流によってレーザダイオード１０が発光し、そのレーザダイオード１０の出力によってディクス上にデータが記録される。
【００６０】
このとき、レーザダイオード１０の出力はデータの消去時の電力値ＦＭＤ＿Ｗのε倍に制御される。すなわち、データの消去時に比べてほぼ出力比ε倍の駆動電流がレーザダイオード１０に供給されることとなる。出力比εは、個々のディスクに対して固有の値としてディスクのウォブルのＡＴＩＰに記録されており、ＡＴＩＰから読み出されて設定される。
【００６１】
例えば、相変化を利用したディスクでは、イレースパワーＰ_ＥＲ：５ｍＷ及びライトパワーＰ_ＷＲ：１１ｍＷが得られるように電圧値ＶＷＤＣ＿Ｗ２が調整される。このときの出力比εは、イレースパワーＰ_ＥＲとライトパワーＰ_ＷＲとの比とほぼ等しい約２．２と算出される。
【００６２】
データの再生のフレームが終了する前にＷＤＡＣ３信号をＤＡ回路３８に設定することで、第２電圧出力回路１６の制御電圧はデータの消去時の電圧値と等しい値に予め昇圧しておくことができる。また、データの消去及び記録を行うフレームにおいては、スイッチＳＷ３を開くことによって、第１電圧出力回路１４とＬＤドライバ１２との接続が遮断され、第１電圧出力回路１４の制御電圧の変動に伴うレーザダイオード１０の出力パワーの変動を最小限に抑制することができる。
【００６３】
なお、現在広く用いられている光ディスク装置では、ＬＤドライバ１２は通常ピックアップ内蔵型であり、第１電圧出力回路１４からの制御電圧によって消去時及び記録時のベースパワーを制御していることが多く、データの消去時及び記録時にスイッチＳＷ３を開放することができないことがある。このような場合、第１電圧出力回路１４とＬＤドライバ１２との間に新たなスイッチを設けて、消去時及び記録時にそのスイッチを開放させても良い。
【００６４】
＜ＷＤＡＣ３信号の設定値の算出方法＞
ＷＤＡＣ３信号の設定値は、第２電圧出力回路１６の制御電圧及びＦＭＤ回路４８で読み取ったレーザダイオード１０の出力電力との関係から求めることができる。以下では、ＬＤＯＮ信号は“Ｌレベル”とし、スイッチＳＷ３が開かれた状態、すなわち、第１電圧出力回路１４とＬＤドライバ１２が切り離され、第１電流源５０からレーザダイオード１０へは駆動電流が出力されない状態で処理を行う。
【００６５】
まず、ＥＦＭＧ信号を“Ｈレベル”に設定して、第１電圧出力回路１４とＡＣＣ回路２４とを接続し、第２電圧出力回路１６とＡＰＣ回路３２とを接続する。処理部４４は、ＤＡ回路２８にＷＲＤＡ４信号を設定する。ＤＡ回路２８によってアナログ変換されたＷＲＤＡ４信号を受けたＡＰＣ回路３２は、レーザダイオード１０の出力パワーがデータの消去に適した電力値ＦＭＤ＿Ｗとなるように第２電圧出力回路１６の制御電圧を定電力制御する。このとき、処理部４４は、第２電圧出力回路１６から出力されている制御電圧値ＶＷＤＣ＿Ｗ２をＡＤコンバータ（図示しない）を用いて取得する。
【００６６】
続いて、ＥＦＭＧ信号を“Ｌレベル”とし、第２電圧出力回路１６の制御をＡＣＣ回路３４による定電流制御に切り替える。処理部４４は、ＡＤコンバータ（図示しない）によって第２電圧出力回路１６から出力される制御電圧を読み取りながら、その制御電圧が電圧値ＶＷＤＣ＿Ｗ２となるようにＤＡ回路３８の設定値を調整する。調整後のＤＡ回路３８の設定値が従来のＷＤＡＣ３信号となる。
【００６７】
以上のように求められたＷＤＡＣ３信号をデータの再生を行うフレームが終了する前にＤＡ回路３８に設定すると、第２電圧出力回路１６の制御がＡＣＣ回路３４からＡＰＣ回路３２に切り替えられる前に第２電圧出力回路１６の制御電圧をＷＤＡＣ３信号に対応する電圧値まで予備的に昇圧しておくことができる。このときの第２電圧出力回路１６からの制御電圧はデータの消去に適した制御電圧ＶＷＤＣ＿Ｗ２と等しい値となる。データの再生時からデータの消去時及び記録時への移行に伴うレーザダイオード１０の出力の変動を低減し、データの記録品位の低下を抑制すると共に、光ディスク装置のサーボ制御の破綻を防ぐことができる。
【００６８】
＜ライトパワーＰ_ＷＲの設定方法＞
ライトパワーＰ_ＷＲを規定する減衰率ＡＴＴの設定方法について説明する。以下においても、ＬＤＯＮ信号は“Ｌレベル”とし、スイッチＳＷ３が開かれた状態で処理を行う。
【００６９】
まず、ＥＦＭＧ信号を“Ｈレベル”に設定して第２電圧出力回路１６とＡＰＣ回路３２とを接続すると共に、ＥＮＤＥＣ４２によってＰＥＯ信号を“Ｈレベル”に設定してスイッチＳＷ４を閉じる。このとき、ＰＷＯ信号は“Ｌレベル”に設定し、スイッチＳＷ５は開放状態とする。
【００７０】
この状態で、処理部４４からＤＡ回路３６に対して信号を出力し、ＡＰＣ回路３２及びＳ／Ｈ回路４０によってＦＭＤ回路４８で読み取られるレーザダイオード１０の出力がディスクへのデータの記録に用いられる中間のパワー７ｍＷとなるように調整を行う。このとき、ＤＡ回路３６に設定される信号値をＷＤＡＣ＿７として処理部４４に記憶する。
【００７１】
レーザダイオード１０を駆動する第２電圧出力回路１６からの制御電圧とレーザーダイオード１０の出力とは原点０を通る比例関係にあるので、レーザダイオード１０の出力が７ｍＷとなるときのＤＡ回路３６の設定値ＷＤＡＣ＿７に基づいてイレースパワーＰ_ＥＲの下限値４ｍＷ及び上限値１０ｍＷでのＤＡ回路３６の設定値ＷＤＡＣ＿４及びＷＤＡＣ＿１０とをそれぞれ算出する。
【００７２】
次に、ディスクのＡＴＩＰから固有の出力比εを読み出す。この出力比εを用いて、イレースパワーＰ_ＥＲとして下限値４ｍＷ、中間値７ｍＷ及び上限値１０ｍＷが設定されているときのライトパワーＰ_ＷＲの目標出力パワーを算出する。
【００７３】
記録ストラテジによって異なるが、実験に基づいて例えば数式（３）による演算を行うことによってライトパワーＰ_ＷＲの目標出力パワーを算出することができる。
【００７４】
【数３】

但し、ｘは出力比εを％に変換したものであり、ｙは目標出力パワーである。
【００７５】
次に、ＥＮＤＥＣ４２によってＰＥＯ信号を“Ｌレベル”に設定してスイッチＳＷ４を開放すると共に、ＰＷＯ信号を“Ｈレベル”に設定してスイッチＳＷ５を閉じる。ＤＡ回路３８には、設定値ＷＤＡＣ＿４，ＷＤＡＣ＿７及びＷＤＡＣ＿１０を順に設定して、ＦＭＤ回路４８を用いてレーザダイオード１０の実際の出力を測定出力パワーとして取得する。
【００７６】
処理部４４は、ＤＡ回路３８への設定値毎に目標出力パワーと測定出力パワーとの比較を行い、これらが一致するまでＡＴＴ回路２０の減衰率ＡＴＴを調整する。設定値毎に目標出力パワーと測定出力パワーとが一致すると、その時点の減衰率ＡＴＴが処理部４４に記憶される。例えば、ＤＡ回路３８に設定値ＷＤＡＣ＿４を設定した場合、目標出力パワーと測定出力パワーとが一致した時点の減衰率がＡＴＴ（４）として記憶される。同様に、設定値ＷＤＡＣ＿７及びＷＤＡＣ＿１０に対する減衰率がＡＴＴ（７）及びＡＴＴ（１０）として記憶される。
【００７７】
このようにして、所定の出力比εにおけるイレースパワーＰ_ＥＲ４ｍＷ，７ｍＷ及び１０ｍＷに対する適切な減衰率ＡＴＴが調整される。イレースパワーＰ_ＥＲに対して減衰率ＡＴＴは、図４に破線で示すように、２次曲線となるが、図４に実線で示すように、任意のイレースパワーＰ_ＥＲに対する適切な減衰率ＡＴＴを数式（４）又は（５）を用いて直線近似により算出することができる。
【００７８】
【数４】

【００７９】
ここで、数式（４）はイレースパワーＰ_ＥＲが４ｍＷ〜７ｍＷにある場合、数式（５）はイレースパワーＰ_ＥＲが７ｍＷ〜１０ｍＷにある場合に使用する。
【００８０】
すなわち、個々のディスクに対するデータの記録に適した出力比εが定められると、その出力比εにおける任意のイレースパワーＰ_ＥＲに対する減衰率ＡＴＴを設定することができる。このように、減衰率ＡＴＴをイレースパワーＰ_ＥＲの設定値に応じて変化させることによって、イレースパワーＰ_ＥＲによらず一定のライトパワーＰ_ＷＲでデータの記録を行うことが可能となる。
【００８１】
このように、イレースパワーＰ_ＥＲの変更範囲における下限値、中間値及び上限値に対する減衰率ＡＴＴを一旦求めておくことによって、その後は上記数式（４）及び数式（５）を用いて任意のイレースパワーＰ_ＥＲに対する適切な減衰率ＡＴＴを算術的に求めることができるため、出力比εの調整に用いられるデータ量を低減でき、調整時間も短縮することができる。
【００８２】
また、本実施の形態では出力比εの調整をＡＴＴ回路２０の減衰率ＡＴＴを用いて行っているが、増幅器１８の増幅率を用いて調整しても良い。さらに、減衰率ＡＴＴ及び増幅率の両方を用いて調整しても良い。
【００８３】
なお、本発明の光ディスク装置及び光ディスクの制御方法は、上記実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内において変更を加えた態様とすることができる。
【００８４】
【発明の効果】
本発明によれば、光ディスク装置においてデータの再生時からデータの消去又は記録時に移行する際のレーザダイオードの異常な出力を防ぐことができる。その結果、例えば、データの記録品質の低下を防ぐことができ、光ディスク装置のサーボ破綻を抑制することができる。
【図面の簡単な説明】
【図１】光ディスク装置の構成を示すブロック図である。
【図２】光ディスク装置のＬＤドライバの構成を示す図である。
【図３】本発明の実施の形態における光ディスク装置の制御のタイミングチャートを示す図である。
【図４】本発明の実施の形態におけるＤＡ回路の設定値の取得方法を説明する図である。
【図５】従来の光ディスク装置の制御におけるタイミングチャートを示す図である。
【図６】従来のＤＡ回路の設定値の取得方法を説明する図である。
【符号の説明】
１０ レーザダイオード、１２ ＬＤドライバ、１４ 第１電圧出力回路、１６ 第２電圧出力回路、１８ 増幅器、２０ 減衰回路（ＡＴＴ回路）、２６，２８，３６，３８ デジタル／アナログ変換回路（ＤＡ回路）、２２，３２ 定電力制御回路（ＡＰＣ回路）、２４，３４ 定電流制御回路（ＡＣＣ回路）、３０，４０ サンプル／ホールド回路（Ｓ／Ｈ回路）、４２ ＥＮＤＥＣ、４４ 処理部、４６ 切替タイミング回路、４８ ＦＭＤ回路、５０ 第１電流源、５２ 第２電流源、５４ 第３電流源、６０ 温度測定回路。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an optical disk device capable of performing servo control stably and a control method of the optical disk device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, optical disk devices such as a CD-R capable of recording data and a CD-RW capable of recording and erasing data have been widely used.
[0003]
Recording of data in such an optical disk device is performed by irradiating a laser beam to an organic dye material as a recording material and burning a recording mark (pit). Reproduction of data is performed by irradiating a recording mark recorded on the recording surface of the disk with laser light and detecting its reflection. At this time, the laser light is applied to the recording surface of the disk through the lens, and it is necessary to perform focus servo control for controlling the lens position so as to be in an optimal state for recording or reproduction.
[0004]
In addition, in order to reproduce, erase, and record data at an accurate position on the disk, the guide groove is accurately traced using reflection of a laser beam from a guide groove (Groove) previously engraved on the disk. It is also necessary to perform tracking servo control for controlling the lens position in such a manner as to perform the above.
[0005]
Further, it is necessary to detect the optimum laser beam power for data reproduction, erasure, and recording, and perform each of the reproduction, erasure, and recording processes while maintaining the optimum power by constant current control or constant power control. .
[0006]
As shown in FIG. 1, a conventional optical disk device includes a laser diode (LD) 10, a laser diode driver (LD driver) 12, a first voltage output circuit 14, a second voltage output circuit 16, an amplifier 18, and an attenuation circuit (ATT). Circuit) 20, constant power control circuits (APC circuits) 22, 32, constant current control circuits (ACC circuits) 24, 34, a plurality of digital / analog conversion circuits (DA circuits) 26, 28, 36, 38, a plurality of samples Hold circuits (S / H circuits) 30 and 40 are included. Further, a processing unit 44 that controls these circuits and stores necessary control values and an ENDEC 42 that controls a signal for switching each switch and the like are also included. Further, an FMD circuit 48 for detecting the output power of the laser diode 10 by a photoelectric conversion element such as a photodiode and outputting a feedback signal is provided.
[0007]
The first voltage output circuit 14 is connected to the APC circuit 22 or the ACC circuit 24 via the switch SW1. The APC circuit 22 is connected to the DA circuit 26 and the S / H circuit 30, and the ACC circuit 24 is connected to the DA circuit 28. The DA circuits 26 and 28 are connected to the processing unit 44. The S / H circuit 30 is connected to the FMD circuit 48.
[0008]
Similarly, the second voltage output circuit 16 is connected to the APC circuit 32 or the ACC circuit 34 via the switch SW2. The APC circuit 32 is connected to a DA circuit 36 and an S / H circuit 40, and the ACC circuit 34 is connected to a DA circuit 38. Further, the DA circuits 36 and 38 are connected to the processing unit 44. The S / H circuit 40 is connected to the FMD circuit 48.
[0009]
The amplifier 18 is connected to the ATT circuit 20, and the ATT circuit 20 is connected to the processing unit 44. The ATT circuit 20 includes an attenuator (attenuator), and attenuates the output voltage from the second voltage output circuit 16 before sending it to the amplifier 18.
[0010]
As shown in FIG. 2, the first voltage output circuit 14, the second voltage output circuit 16, and the amplifier 18 are connected to the first current source 50 and the second current source 52 included in the LD driver 12 via switches SW3 to SW5. And the third current source 54. Upon receiving a control voltage from the first voltage output circuit 14, the second voltage output circuit 16, or the amplifier 18, the first current source 50, the second current source 52, and the third current source 54 of the LD driver 12 are connected to the laser diode 10. Outputs drive current. When reproducing data, the current from the first current source 50, when erasing data, the combined current from the first current source 50 and the second current source 52, and when recording data, from the first current source 50 and the third current source 54. The laser diode 10 is caused to emit light by the combined current, and data is reproduced, erased, or recorded.
[0011]
FIG. 5 shows a timing chart when reproducing, erasing, and recording data on the disk. The optical disk device reads an ATIP reference signal (ATIPSYNC) engraved on the disk, and starts processing of each frame in synchronization with the rise of the ATIP reference signal. In the example of the timing chart, the reproduction of the data of the disk is performed in the first frame, and thereafter, the processing shifts to the erasing and recording of the data of the disk from the second frame.
[0012]
In the first frame, the EFMG signal output from the switching timing circuit 46 is set to “L level”, and the switch SW1 is connected to the a1 side and the switch SW2 is connected to the b2 side corresponding to the EFMG signal. As a result, the first voltage output circuit 14 is controlled by the APC circuit 22 and the second voltage output circuit 16 is controlled by the ACC circuit 34. The LDON signal is constantly output from the ENDEC 42, the switch SW3 is closed, and the first voltage output circuit 14 and the LD driver 12 are connected.
[0013]
In order to reproduce data, the processing unit 44 outputs a REDA signal to the DA circuit 26. The DA circuit 26 receives the REDA signal from the processing unit 44, converts the REDA signal from digital to analog, and outputs it to the APC circuit 22. The APC circuit 22 receives the REDA signal converted from the DA circuit 26 into an analog signal, and causes the first voltage output circuit 14 to output the control voltage value VRDC_R to the LD driver 12. The LD driver 12 receives the control voltage value VRDC_R, outputs a drive current from the first current source 50 to the laser diode 10, and causes the laser diode 10 to emit light. The pits or lands on the disk are read by the output of the laser diode 10 to reproduce data.
[0014]
Here, the output power of the laser diode 10 is read by the FMD circuit 48 and fed back to the S / H circuit 30 as a feedback signal. While data is being read from the disk, the ENDEC 42 outputs the RAPC signal as "H level" to the S / H circuit 30, and causes the S / H circuit 30 to sample and hold the feedback signal. The sampled value is output to the APC circuit 22. Based on the sampled value, the APC circuit 22 controls the first voltage output circuit 14, and during data reproduction, the power of the laser diode 10 is changed to a constant power determined by the REDA signal. Thus, the control voltage from the first voltage output circuit 14 is adjusted. The output power of the laser diode 10 controlled by the APC is set to a power value FMD_R.
[0015]
On the other hand, before shifting from a frame in which data is reproduced to a frame in which data is erased or recorded, the processing unit 44 outputs a WDAC2 signal to the DA circuit 38 to control the control voltage output from the second voltage output circuit 16. In advance. This is because when the second voltage output circuit 16 is switched from the constant current control by the ACC circuit 34 to the constant power control by the APC circuit 32, the delay in following the control voltage output from the second voltage output circuit 16 is reduced. This is for suppressing.
[0016]
The set value of the WDAC2 signal can be obtained in advance from the relationship between the control voltage of the second voltage output circuit 16 and the output power of the laser diode 10 read by the FMD circuit 48, as shown in FIG.
[0017]
First, the EFMG signal is set to “H level”, the second voltage output circuit 16 is connected to the APC circuit 32, and the processing unit 44 outputs the set value Y1 to the DA circuit 36. The APC circuit 32 receives the set value Y1 from the DA circuit 36 and the feedback signal from the FMD circuit 48, and causes the second voltage output circuit 16 to output a constant control voltage V1 defined by the set value Y1. The LD driver 12 receives the control voltage V1 and supplies a drive current from the second current source 52 to the laser diode 10 according to the control voltage V1. The laser diode 10 receives a drive current from the first current source 50 receiving the control voltage value VRDC_W from the first voltage output circuit 14 controlled by the ACC circuit 24, and a drive current from the second current source 52 receiving the control voltage V1. It emits light by the combined current with the driving current of. At this time, the output of the laser diode 10 read by the FMD circuit 48 is defined as power W1. The relationship between the set value Y1 of the DA circuit 36, the control voltage value V1 from the second voltage output circuit 16, and the output power W1 of the laser diode 10 is shown by point A in FIG.
[0018]
Similarly, the set value Y2 is output from the processing unit 44 to the DA circuit 36, and the control voltage value V2 and the output power W2 of the laser diode 10 are obtained from the second voltage output circuit 16 at that time (point B in FIG. 6). For example, when a disk using phase change is targeted, it is preferable to select from a range of 10 mW to 20 mW. Further, the temperature T1 of the laser diode 10 at this time is measured by the temperature measurement circuit 60.
[0019]
Next, the EFMG signal is set to “L level”, the second voltage output circuit 16 is connected to the ACC circuit 34, and the processing unit 44 outputs the set value Y3 to the DA circuit 38. The ACC circuit 34 receives the output of the set value Y3 from the DA circuit 38 and performs control so that the control voltage from the second voltage output circuit 16 becomes a constant value defined by the set value Y3. At this time, the set value Y3 is adjusted so that the control voltage output from the second voltage output circuit 16 becomes equal to the voltage value V1, and the set value Y3 at that time is obtained.
[0020]
Similarly, using the ACC circuit 34, a set value Y4 at which the control voltage output from the second voltage output circuit 16 becomes equal to the voltage value V2 is obtained. The temperature T2 of the laser diode 10 at this time is obtained by the temperature measurement circuit 60.
[0021]
Assuming that the output of the laser diode 10 suitable for erasing data is the power FMD_W, the set value WDAC1 set in the DA circuit 36 can be calculated by the relational expression (1). The relational expression (1) is for linearly approximating the output of the laser diode 10 based on the powers W1 and W2 obtained above, and calculating a set value WDAC1 at which the output power WE is output.
[0022]
(Equation 1)

[0023]
Further, before shifting from the data reproduction frame to the data erasing or recording frame, the set value WDAC2 set in the DA circuit 38 can be calculated using the relational expression (2).
[0024]
(Equation 2)

[0025]
As described above, the value of the set value WDAC2 can be determined. In the constant current control by the ACC circuit 34, since the actual output power of the laser diode 10 is not used for feedback, the relationship between the set value WDAC2 and the output power of the laser diode 10 is affected by the temperature of the laser diode 10. Easy to fluctuate. Therefore, when the measured temperature T2 of the laser diode 10 is not within the predetermined temperature range with respect to the measured temperature T1, the above processing is performed again, and the relational expressions (1) and (2) are obtained again to obtain the set values WDAC1 and WDAC2. Is calculated.
[0026]
Next, in synchronization with ATIPSYNC, the process shifts to a second frame in which data is erased and recorded. The switching timing circuit 46 raises the EFMG signal to “H level” in response to the rise of ATIPSYNC, and switches the switch SW1 to the b1 side and the switch SW2 to the a2 side.
[0027]
The processing unit 44 outputs a WRDA signal to the DA circuit 28. The DA circuit 28 converts the WRDA signal from digital to analog and outputs it to the ACC circuit 24. The ACC circuit 24 receives the analog-converted WRDA signal, causes the first voltage output circuit 14 to output a control voltage defined by the WRDA signal, and outputs a drive current output from the first current source 50 of the LD driver 12. The constant current control is performed so as to be maintained at a constant current value determined by the WRDA signal. At this time, the drive current determined by the WRDA signal determines a base power (bottom power) during data recording, and has a sufficiently small current value that the laser diode 10 does not emit light. At this time, the control voltage output from the first voltage output circuit 14 is referred to as a voltage value VRDC_W (VRDC at the time of recording).
[0028]
On the other hand, the processing unit 44 outputs a WDAC1 signal to the DA circuit 36. The DA circuit 36 converts the WDAC1 signal from digital to analog and outputs it to the APC circuit 32. The APC circuit 32 receives the analog-converted WDAC1 signal and outputs it from the second voltage output circuit 16 so that the output power from the laser diode 10 becomes a power suitable for erasing data on the disk. Control the control voltage. The output power of the laser diode 10 is read by the FMD circuit 48 and output to the S / H circuit 40 as a feedback signal. The ENDEC 42 outputs a WAPC signal in synchronization with the data erasing timing, and causes the S / H circuit 40 to sample and hold the feedback signal from the FMD circuit 48. The APC circuit 32 receives this sampling value, and performs feedback control of the control voltage output from the second voltage output circuit 16 so that the power of the laser diode 10 at the time of erasing is maintained at a constant value determined by the WDAC1 signal.
[0029]
At the same time, the ENDEC 42 causes the S / H circuit 30 to sample and hold the feedback signal from the FMD circuit 48 by outputting the RAPC signal when erasing data. The APC circuit 22 receives this sampling value and adjusts the output power of the laser diode 10 to a value suitable for reproduction when the optical disk device is switched to data reproduction processing.
[0030]
The ENDEC 42 outputs a PEO signal at the timing of erasing data on the disk. As a result, the switch SW4 is closed, and the second voltage output circuit 16 and the LD driver 12 are connected. The combined current of the current from the first current source 50 of the LD driver 12 controlled by the ACC circuit 24 and the current from the second current source 52 of the LD driver 12 controlled by the APC circuit 32 drives the laser diode 10. It is output as a current and the data on the disk is erased. At this time, the control voltage of the second voltage output circuit 16 is a voltage value VWDC_W1 (VWDC at the time of recording), and the output power from the laser diode 10 is a power value FMD_W.
[0031]
The voltage value VWDC_W is set in the ATT circuit 20 from the second voltage output circuit 16, and a voltage value obtained by attenuating the voltage value VWDC_W 1 by the attenuation rate ATT is output to the amplifier 18. The amplifier 18 receives the output from the ATT circuit 20 and performs amplification so that the output of the laser diode 10 becomes ε times the power value FMD_W at the time of data erasure. The value of ε is recorded in the ATIP of the wobble of the disc as a value unique to each disc, and is read from the ATIP and set.
[0032]
When recording data on the disk, the ENDEC 42 outputs a PWO signal at the timing of recording data on the disk, and connects the amplifier 18 and the LD driver 12 by closing the switch SW5. As a result, a combined current of the current from the first current source 50 of the LD driver 12 controlled by the ACC circuit 24 and the current from the third current source 54 controlled by the control voltage of the amplifier 18 is supplied to the laser diode 10. It is supplied as a drive current and data is recorded on the disk.
[0033]
[Problems to be solved by the invention]
In the above-described conventional technique, before shifting from a frame in which data is reproduced to a frame in which data is erased or recorded, a WDAC2 signal is output to an ACC circuit 34 connected to the second voltage output circuit 16 to output data. After performing the advance control of the power so that a laser output suitable for erasing or recording is obtained, the control of the second voltage output circuit 16 is switched from the constant current control by the ACC circuit 34 to the constant power control by the APC circuit 32.
[0034]
However, when shifting from a frame in which data is reproduced to a frame in which data is erased or recorded, the first voltage output circuit 14 is also switched from constant power control by the APC circuit 22 to constant current control by the ACC circuit 24. It takes time for the control voltage from the first voltage output circuit 14 to stabilize from the voltage value VRDC_R to the voltage value VRDC_W. Therefore, the base power of the laser diode 10 is not stabilized at the beginning of the start of a frame in which data is erased or recorded, and the laser output when erasing data on the disk is gradually increased as shown by the two-dot chain line in FIG. Changes towards a stable state. In addition, as shown by a dashed line in FIG. 5, the laser output at the time of recording data on the disk fluctuates, and a problem arises that extra power is output at the beginning of switching.
[0035]
Due to the abnormal output from the laser diode 10, the quality of data erasure and recording on the disk is degraded. At the same time, it becomes difficult to obtain a control signal for performing servo control of the optical disk device, which causes a breakdown of servo control. Further, since the laser output becomes unnecessarily high, the characteristics of the laser diode 10 are degraded, and the problem of shortening the life is also caused.
[0036]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the related art, and provides at least one of the above-described problems in providing an optical disk device and a control method of the optical disk device that can stably output a laser diode during a transition period. Aim.
[0037]
[Means for Solving the Problems]
The present invention that can solve the above-mentioned problems includes a first control signal output unit that outputs a first control signal and a second control signal output unit that outputs a second control signal. An optical disk device that controls the output of the light emitting element based on the first control signal and controls the output of the light emitting element based on the second control signal when erasing or recording data; A first constant power control means for controlling the first control signal output means at a constant power, and a first constant power control for controlling the first control signal output means at a constant current when erasing or recording data. A current control unit, a second constant current control unit that controls the second control signal output unit with a constant current at the time of data reproduction, and a second control signal output unit at the time of data erasure or recording. Constant power control Switching the control of the second constant power control means and the first control signal output means from the first constant power control means to the first constant current control means; Switching means for switching control from the second constant current control means to the second constant power control means, wherein the control of the second control signal output means is controlled by the second constant current control by the switching means. Before the control unit is switched to the second constant power control unit, the control signal output from the second control signal output unit is set to a value substantially equal to a value at the time of erasing or recording data. The second control signal output means is controlled by a constant current.
[0038]
Further, in the optical disc device of the present invention, a driver for driving the optical element and a switch for disconnecting the driver and the first control signal output means when erasing or recording data are provided. Is preferred.
[0039]
Another embodiment of the present invention that can solve the above-described problem includes a first control signal output unit that outputs a first control signal, and a second control signal output unit that outputs a second control signal. Controlling the output of the light emitting element based on the first control signal during data reproduction, and controlling the output of the light emitting element based on the second control signal during data erasing or recording A method of performing constant power control on the first control signal output means at the time of data reproduction, and controlling the control signal output from the second control signal output means with a value at the time of data erasure or recording. Performing a constant current control so as to have substantially equal values, and performing a constant current control on the first control signal output means and a constant power control on the second control signal output means during data erasing or recording. Characterized in that it comprises a step.
[0040]
In the method for controlling an optical disk device according to the present invention, the optical disk device has a driver for driving the optical element, and the driver and the first control signal output unit are connected via a switch, and It is preferable to include a step of disconnecting the electrical connection between the driver and the first control signal output means by using the switch when a transition is made from data reproduction to data erasure or data recording.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The optical disk device according to the embodiment of the present invention has the same configuration as the conventional optical disk device shown in FIGS.
[0042]
FIG. 3 shows a timing chart at the time of reproducing, erasing, and recording data on the disk in the present embodiment. In the example of the timing chart, the reproduction of the data of the disc is performed in the first frame, and thereafter, the operation shifts to the erasing and recording of the data in the second frame.
[0043]
In the first frame, the EFMG signal output from the switching timing circuit 46 is at “L level”, the switch SW1 is connected to the a1 side, and the switch SW2 is connected to the b2 side. Therefore, the first voltage output circuit 14 is controlled by the APC circuit 22, and the second voltage output circuit 16 is controlled by the ACC circuit 34. The LDON signal is constantly output from the ENDEC 42, the switch SW3 is closed, and the first voltage output circuit 14 and the LD driver 12 are connected.
[0044]
In reproducing the data of the first frame, the drive current of the laser diode 10 is controlled in the same manner as in the related art. That is, the processing unit 44 sets the REDA signal to the DA circuit 26. On the other hand, the output power of the laser diode 10 is read out by the FMD circuit 48, and the sampling value is fed back to the APC circuit 22, whereby the output power of the laser diode 10 is maintained at a constant value defined by the REDA signal. At this time, the control voltage output from the first voltage output circuit 14 is the voltage value VRDC_R.
[0045]
For example, in the case of a disk using a phase change, the voltage value VRDC_R of the control voltage is adjusted so that read power P _RD : 1 mW is obtained for data reproduction.
[0046]
Further, while reproducing the data, the ENDEC 42 keeps the PEO signal and the PWO signal at "L level" and outputs them. Thereby, SW4 and SW5 are opened, and the second voltage output circuit 16 and the amplifier 18 are disconnected from the LD driver 12.
[0047]
The optical disk device of the present embodiment is characterized by disconnecting the first voltage output circuit 14 from the LD driver 12 when shifting from a frame for reproducing data to a frame for erasing and recording data.
[0048]
Before the end of the frame in which data is to be reproduced, the processing unit 44 outputs the WDAC3 signal to the DA circuit 38 and boosts the control voltage output from the second voltage output circuit 16 in advance. This allows the control voltage output from the second voltage output circuit 16 to shift from the constant current control by the ACC circuit 34 during data reproduction to the constant power control by the APC circuit 32 during data erasure and recording. This is for smooth following.
[0049]
The DA circuit 38 receives the WDAC3 signal, converts the WDAC3 signal from digital to analog, and outputs it to the ACC circuit 34. The ACC circuit 34 receives the analog-converted WDAC3 signal and controls the second voltage output circuit 16 to output a control voltage value VWDC_W2 defined by the WDAC3 signal. The control voltage value VWDC_W2 is a control voltage value when the power value FMD_W is output from the laser diode 10.
[0050]
A method of calculating the set values of the WDAC3 signal, the output ratio ε, and the attenuation ATT will be described later in detail.
[0051]
At this time, since the PEO signal and the PWO signal are maintained at “L level”, the switches SW4 and SW5 are open, and the control voltage from the second voltage output circuit 16 and the amplifier 18 is applied to the LD driver 12. Not transmitted.
[0052]
When the reproduction of the data from the disk is completed, the process shifts to the second frame in which the data is erased and recorded in synchronization with the rise of ATIPSYNC. The switching timing circuit 46 raises the EFMG signal to “H level” in response to the rise of ATIPSYNC, connects the switch SW1 to the b1 side, and connects the switch SW2 to the a2 side. As a result, the first voltage output circuit 14 is controlled by the ACC circuit 24 at a constant current, and the second voltage output circuit 16 is controlled by the APC circuit 32 at a constant power.
[0053]
Further, the ENDEC 42 sets the LDON signal for the switch SW3 to “L level” to disconnect the first voltage output circuit 14 from the LD driver 12.
[0054]
The processing unit 44 outputs a WRDA signal to the DA circuit 28. The WRDA signal is converted to an analog signal and output to the ACC circuit 24. The ACC circuit 24 receives the WRDA signal and performs constant current control on the first voltage output circuit 14. However, since the LDON signal is at “L level” and the switch SW3 is open, the control voltage from the first voltage output circuit 14 is not transmitted to the LD driver 12, and the laser diode from the first current source 50 No drive current is output to 10.
[0055]
The processing unit 44 outputs a WDAC4 signal to the DA circuit 36. The DA circuit 36 converts the WDAC4 signal from digital to analog and outputs it to the APC circuit 32. The APC circuit 32 receives the analog-converted WDAC4 signal and controls the output of the second voltage output circuit 16 so that the output power from the laser diode 10 becomes the power FMD_W suitable for erasing data on the disk.
[0056]
When erasing data, the PEO signal is set to "H level" in synchronization with the data erasing timing by the ENDEC 42, and the switch SW4 is closed to change the control voltage value from the second voltage output circuit 16 to the LD driver 12 To enter. The LD driver 12 receives a control voltage value from the second voltage output circuit 16 and supplies a drive current from the second current source 52 to the laser diode 10. The laser diode 10 is caused to emit light by the drive current, and data on the disk is erased. At this time, since the first voltage output circuit 14 and the LD driver 12 are separated from each other, the laser diode 10 is caused to emit light only by the drive current from the second current source 52.
[0057]
The output power of the laser diode 10 is read by the FMD circuit 48 and output to the S / H circuit 40 as a feedback signal. The ENDEC 42 outputs a WAPC signal in synchronization with the data erasing timing, and causes the S / H circuit 40 to sample and hold the feedback signal. The APC circuit 32 receives this sampling value and controls the control voltage output from the second voltage output circuit 16 so that the output of the laser diode 10 is maintained at the power value FMD_W. The control voltage at this time is VWDC_W2.
[0058]
When data is recorded on the disk, the PWO signal is set to "H level" in synchronization with the timing at which the data is erased by the ENDEC 42, and the switch SW5 is closed.
[0059]
The ATT circuit 20 receives the control voltage value VWDC_W2 from the second voltage output circuit 16, attenuates the control signal by the attenuation rate ATT, and outputs the control signal to the amplifier 18. The amplifier 18 amplifies the output from the ATT circuit 20 and outputs the amplified output to the LD driver 12. The third current source 54 of the LD driver 12 receives a control voltage from the amplifier 18 and supplies a drive current defined by the control voltage to the laser diode 10. As a result, the laser diode 10 emits light by the driving current from the third current source 54, and data is recorded on the disk by the output of the laser diode 10.
[0060]
At this time, the output of the laser diode 10 is controlled to be ε times the power value FMD_W at the time of data erasure. That is, a drive current having an output ratio ε times that of the data erase operation is supplied to the laser diode 10. The output ratio ε is recorded in the ATIP of the wobble of the disc as a value unique to each disc, and is read from the ATIP and set.
[0061]
For example, in a disk using a phase change, the voltage value VWDC_W2 is adjusted such that an erase power P _{ER of} 5 mW and a write power P _{WR of} 11 mW are obtained. The output ratio ε at this time is calculated to be approximately 2.2, which is substantially equal to the ratio between the erase power _PER and the write power _PWR .
[0062]
By setting the WDAC3 signal to the DA circuit 38 before the end of the data reproduction frame, the control voltage of the second voltage output circuit 16 can be boosted in advance to a value equal to the voltage value when data is erased. it can. In a frame in which data is erased and recorded, the connection between the first voltage output circuit 14 and the LD driver 12 is cut off by opening the switch SW3, and the control voltage of the first voltage output circuit 14 is changed. Fluctuations in the output power of the laser diode 10 can be minimized.
[0063]
In an optical disk device widely used at present, the LD driver 12 is usually of a type with a built-in pickup, and the base power at the time of erasing and recording is often controlled by a control voltage from the first voltage output circuit 14. In some cases, the switch SW3 cannot be opened when erasing or recording data. In such a case, a new switch may be provided between the first voltage output circuit 14 and the LD driver 12, and the switch may be opened at the time of erasing and recording.
[0064]
<Method of calculating set value of WDAC3 signal>
The set value of the WDAC3 signal can be obtained from the relationship between the control voltage of the second voltage output circuit 16 and the output power of the laser diode 10 read by the FMD circuit 48. Hereinafter, the LDON signal is set to “L level”, the switch SW3 is opened, that is, the first voltage output circuit 14 and the LD driver 12 are disconnected, and the drive current is supplied from the first current source 50 to the laser diode 10. Perform processing with no output.
[0065]
First, the EFMG signal is set to “H level”, the first voltage output circuit 14 and the ACC circuit 24 are connected, and the second voltage output circuit 16 and the APC circuit 32 are connected. The processing unit 44 sets the WRDA4 signal in the DA circuit 28. The APC circuit 32, which has received the WRDA4 signal converted by the DA circuit 28, converts the control voltage of the second voltage output circuit 16 to a constant power so that the output power of the laser diode 10 becomes a power value FMD_W suitable for erasing data. Control. At this time, the processing unit 44 acquires the control voltage value VWDC_W2 output from the second voltage output circuit 16 using an AD converter (not shown).
[0066]
Subsequently, the EFMG signal is set to “L level”, and the control of the second voltage output circuit 16 is switched to the constant current control by the ACC circuit 34. While reading the control voltage output from the second voltage output circuit 16 by an AD converter (not shown), the processing unit 44 adjusts the set value of the DA circuit 38 so that the control voltage becomes the voltage value VWDC_W2. The set value of the DA circuit 38 after the adjustment becomes the conventional WDAC3 signal.
[0067]
If the WDAC3 signal obtained as described above is set in the DA circuit 38 before the end of the frame for reproducing data, the control of the second voltage output circuit 16 is performed before the control of the second voltage output circuit 16 is switched from the ACC circuit 34 to the APC circuit 32. The control voltage of the two-voltage output circuit 16 can be preliminarily boosted to a voltage value corresponding to the WDAC3 signal. At this time, the control voltage from the second voltage output circuit 16 has a value equal to the control voltage VWDC_W2 suitable for erasing data. It is possible to reduce fluctuations in the output of the laser diode 10 due to the transition from data reproduction to data erasing and recording, to suppress deterioration of data recording quality, and to prevent servo control of the optical disk device from being broken. it can.
[0068]
<Setting method of write power _PWR >
Described method of setting the attenuation factor ATT defining the write power _{P WR.} Also in the following, the LDON signal is set to “L level”, and the processing is performed with the switch SW3 opened.
[0069]
First, the EFMG signal is set to "H level" to connect the second voltage output circuit 16 to the APC circuit 32, and the PEDEC signal is set to "H level" by the ENDEC 42 to close the switch SW4. At this time, the PWO signal is set to “L level”, and the switch SW5 is opened.
[0070]
In this state, a signal is output from the processing unit 44 to the DA circuit 36, and the output of the laser diode 10 read by the FMD circuit 48 by the APC circuit 32 and the S / H circuit 40 is used for recording data on a disk. Adjustment is performed so that the intermediate power becomes 7 mW. At this time, the signal value set in the DA circuit 36 is stored in the processing unit 44 as WDAC_7.
[0071]
Since the control voltage from the second voltage output circuit 16 for driving the laser diode 10 and the output of the laser diode 10 are in a proportional relationship passing through the origin 0, the setting of the DA circuit 36 when the output of the laser diode 10 becomes 7 mW respectively calculates a set value WDAC_4 and WDAC_10 the DA circuit 36 at the lower limit 4mW and the upper limit 10mW of the erase power _{P ER} based on the value WDAC_7.
[0072]
Next, the unique output ratio ε is read from the ATIP of the disk. Using this output ratio epsilon, and calculates the target output power of the write power P _WR when the lower limit 4 mW, the intermediate value 7mW and the upper limit value 10mW is set as erase power P _ER.
[0073]
Although it depends on the recording strategy, the target output power of the write power P _WR can be calculated by performing, for example, an arithmetic operation based on Expression (3) based on an experiment.
[0074]
[Equation 3]

Here, x is a value obtained by converting the output ratio ε into%, and y is a target output power.
[0075]
Next, the PEO signal is set to "L level" by the ENDEC 42 to open the switch SW4, and the PWO signal is set to "H level" to close the switch SW5. The set values WDAC_4, WDAC_7, and WDAC_10 are sequentially set in the DA circuit 38, and the actual output of the laser diode 10 is acquired as the measured output power using the FMD circuit 48.
[0076]
The processing unit 44 compares the target output power and the measured output power for each set value to the DA circuit 38, and adjusts the attenuation rate ATT of the ATT circuit 20 until they match. When the target output power and the measured output power match for each set value, the attenuation rate ATT at that time is stored in the processing unit 44. For example, when the set value WDAC_4 is set in the DA circuit 38, the attenuation rate at the time when the target output power matches the measured output power is stored as ATT (4). Similarly, the attenuation factors for the set values WDAC_7 and WDAC_10 are stored as ATT (7) and ATT (10).
[0077]
In this manner, an appropriate attenuation rate ATT for the erase power P _{ER of} 4 mW, 7 mW and 10 mW at the predetermined output ratio ε is adjusted. Attenuation factor ATT respect erase power P _ER, as shown by the broken line in FIG. 4, a quadratic curve, as shown by the solid line in FIG. 4, an appropriate attenuation factor ATT for any erase power P _ER It can be calculated by linear approximation using the mathematical formula (4) or (5).
[0078]
(Equation 4)

[0079]
Here, Equation (4) When the erase power _{P ER} is in 4MW～7mW, Equation (5) is used when the erase power _{P ER} is in 7MW～10mW.
[0080]
That is, when the output ratio suitable for the recording of data to individual disk epsilon is defined, it is possible to set the attenuation factor ATT for any erase power P _ER at its output ratio epsilon. Thus, by varying in accordance with the attenuation factor ATT to the set value of the erase power P _ER, it is possible to record data at a constant write power P _WR regardless of the erase power P _ER.
[0081]
Thus, the lower limit of the change range of the erase power P _ER, by keeping once determined the attenuation factor ATT the intermediate value and the upper limit value, then any erase by using the equation (4) and Equation (5) it is possible to find an appropriate attenuation factor ATT for the power P _ER arithmetically, can reduce the amount of data to be used for adjusting the output ratio epsilon, adjustment time can also be shortened.
[0082]
In the present embodiment, the output ratio ε is adjusted using the attenuation factor ATT of the ATT circuit 20, but may be adjusted using the amplification factor of the amplifier 18. Further, the adjustment may be performed using both the attenuation rate ATT and the amplification rate.
[0083]
It should be noted that the optical disk device and the optical disk control method of the present invention are not limited to the above-described embodiment, but may be modified without departing from the scope of the present invention.
[0084]
【The invention's effect】
According to the present invention, it is possible to prevent an abnormal output of the laser diode when the optical disk apparatus shifts from reproducing data to erasing or recording data. As a result, for example, a decrease in data recording quality can be prevented, and servo failure of the optical disk device can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an optical disk device.
FIG. 2 is a diagram illustrating a configuration of an LD driver of the optical disc device.
FIG. 3 is a diagram showing a timing chart of control of the optical disc device in the embodiment of the present invention.
FIG. 4 is a diagram illustrating a method for obtaining a set value of a DA circuit according to the embodiment of the present invention.
FIG. 5 is a diagram showing a timing chart in control of a conventional optical disk device.
FIG. 6 is a diagram illustrating a conventional method of acquiring a set value of a DA circuit.
[Explanation of symbols]
Reference Signs List 10 laser diode, 12 LD driver, 14 first voltage output circuit, 16 second voltage output circuit, 18 amplifier, 20 attenuation circuit (ATT circuit), 26, 28, 36, 38 digital / analog conversion circuit (DA circuit), 22, 32 constant power control circuit (APC circuit), 24, 34 constant current control circuit (ACC circuit), 30, 40 sample / hold circuit (S / H circuit), 42 ENDEC, 44 processing unit, 46 switching timing circuit, 48 FMD circuit, 50 first current source, 52 second current source, 54 third current source, 60 temperature measurement circuit.

Claims (4)

First control signal output means for outputting a first control signal;
Second control signal output means for outputting a second control signal,
An optical disc device for controlling an output of a light emitting element based on the first control signal when reproducing data, and controlling an output of the light emitting element based on the second control signal when erasing or recording data. ,
A first constant power control unit that performs constant power control on the first control signal output unit during data reproduction;
A first constant current control unit that performs constant current control on the first control signal output unit when erasing or recording data;
A second constant current control unit that performs constant current control on the second control signal output unit during data reproduction;
A second constant power control unit that performs constant power control on the second control signal output unit when erasing or recording data;
The control of the first control signal output means is switched from the first constant power control means to the first constant current control means, and the control of the second control signal output means is controlled by the second constant current control means Switching means for switching from the first constant power control means to the second constant power control means;
Including
Before the control of the second control signal output means is switched from the second constant current control means to the second constant power control means by the switching means, the control signal output means outputs the second control signal output means. An optical disk device, wherein the second control signal output means is controlled by a constant current so that the control signal is substantially equal to a value at the time of erasing or recording data. The optical disc device according to claim 1,
A driver for driving the optical element;
A switch for disconnecting an electrical connection between the driver and the first control signal output means when erasing or recording data;
An optical disk device comprising: A first control signal output unit for outputting a first control signal; and a second control signal output unit for outputting a second control signal, and based on the first control signal during data reproduction. A method for controlling an optical disc device, comprising: controlling an output of a light emitting element, and controlling an output of the light emitting element based on the second control signal when erasing or recording data,
At the time of data reproduction, the first control signal output means is controlled at a constant power, and the control signal output from the second control signal output means has a value substantially equal to the value at the time of data erasure or recording. Controlling the constant current so that
A step of performing constant current control on the first control signal output means and a constant power control on the second control signal output means when erasing or recording data;
A method for controlling an optical disk device, comprising: The control method of an optical disk device according to claim 3,
The optical disk device has a driver for driving the optical element, and the driver and the first control signal output unit are connected via a switch,
An optical disc device comprising a step of disconnecting an electrical connection between the driver and the first control signal output means using the switch when a transition is made from data reproduction to data erasure or recording. Control method.

Images