JP2004214643A - Laminated chip varistor and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated chip varistor having small deterioration in varistor characteristics, even when the surface of an external electrode is further plated, and to provide its manufacturing method. <P>SOLUTION: A laminated chip varistor 1 is provided with a varistor element assembly 1, having a plurality of varistor layers 1a, 1b, and 1c and internal electrodes 2a and 2b, arranged so as to sandwich each varistor layer, external electrodes 3a that are formed at the end part of this varistor element assembly 1 and that are connected with the internal electrodes, and glass layers 4 formed between the varistor element assembly 1 and the external electrodes 3a. Moreover, a plating layer 3b and a plating layer 3c are formed on the surface of the external electrode 3a. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a multilayer chip varistor and a method for manufacturing the same.

  As a laminated chip varistor, a varistor element obtained by sintering a laminated body in which a varistor layer and an internal electrode are laminated, and a conductive paste applied to an end face of the varistor element, applied, dried, and baked There is known a structure including a formed external electrode.

  As the conductive paste used for forming the external electrode, a paste obtained by blending a glass frit or an organic vehicle with a metal powder such as silver as a main component is frequently used. The glass frit blended in the conductive paste is blended for the purpose of improving the bondability between the varistor element and the external electrode.

  As a method of mounting such a multilayer chip varistor on a printed board or the like, the varistor is placed on a solder paste previously applied to a conductor on the board, and then the entire board is heated to 200 ° C. or more. Is generally fixed by melting and fixing the so-called reflow.

  At this time, in order to improve the wettability of the external electrode with respect to the solder during reflow, the external electrode is often plated with nickel and then plated with solder or tin.

  However, when plating is performed on the external electrodes in this way, the plating solution penetrates into the varistor element body, and the plating solution that has entered the varistor element body forms a varistor layer in the varistor element body, in particular, a varistor layer. In some cases, the grain boundary portion of the varistor material was eroded. In this case, since the varistor characteristics of the multilayer chip varistor are considered to be developed in the grain boundary portion, the varistor characteristics of the multilayer chip varistor such as the varistor voltage are reduced. Such a decrease in the varistor characteristics may be observed immediately after plating or after being mounted on the substrate by reflow.

  In order to prevent the deterioration of the characteristics due to the intrusion of the plating solution, various measures have been taken in recent multilayer chip varistors. For example, multilayer chip varistors described in Patent Literature 1 and Patent Literature 2 below are known. FIG. 6 is a cross-sectional view showing the multilayer chip varistor described in the above document. The multilayer chip varistor shown in FIG. 6 has a varistor element 10 having an internal electrode 11 and an external electrode 12 provided at an end of the varistor element 10. An insulating protective layer 13 is formed in a portion of the varistor element body 10 where the external electrode 12 is not formed. In this multilayer chip varistor, the insulating protective layer 13 plays a role of preventing the plating solution from entering the varistor element 10.

  Further, as a multilayer chip varistor capable of reducing the entry of a plating solution, a multilayer chip varistor described in Patent Document 3 below is also known. FIG. 7 is a cross-sectional view showing the multilayer chip varistor described in the above-mentioned document. The multilayer chip varistor shown in FIG. 7 includes a varistor element 10 having an internal electrode 11 and a base electrode layer 14 provided at an end of the varistor element 10. A glass coating 15 and an outer electrode layer 16 are formed outside the base electrode layer 14. In addition, a conductive material is diffused in the glass coating 15, so that conduction between the base electrode layer 14 and the outer electrode layer 16 is achieved.

  Further, Patent Literature 4 below describes a multilayer chip varistor in which external electrodes are formed using a conductive paste containing a predetermined amount or more of conductive glass frit. In such a multilayer chip varistor, the content of the glass frit in the external electrode is increased as compared with the conventional case to reduce the gap of the external electrode, thereby suppressing the plating solution from passing through the external electrode. Further, by using a conductive material containing tin oxide or antimony oxide as the glass frit, a decrease in solder wettability, which often occurs with an increase in the amount of glass frit, is suppressed.

Further, Patent Documents 5 and 6 below describe conductive pastes containing glass frit having a specific composition. It has been shown that the external electrodes of the laminated element formed using this conductive paste have excellent resistance to a plating solution, and thereby can suppress the deterioration of the characteristics of the element due to the intrusion of the plating solution.
JP-A-8-31616 JP-A-10-70012 JP 2000-164406 A JP-A-2002-134306 JP-A-6-349313 JP 2001-122639 A

  However, the multilayer chip varistor shown in FIG. 6 can prevent the plating solution from entering from the surface of the varistor element body 10 by the insulating protective layer 13, but the external electrodes 12 are not formed sufficiently densely. Therefore, the plating solution may enter the varistor element 10 through the gap of the external electrode 12. In particular, the plating solution often entered the inside of the element body 10 from the gap between the varistor element body 10 and the internal electrode 11. In this case, the varistor body 10 is significantly eroded by the plating solution, and the varistor characteristics are further reduced.

  In the multilayer chip varistor shown in FIG. 6, the insulating protective layer 13 is formed by putting the varistor element body 10 in silicon oxide powder and firing. For this reason, such a multilayer chip varistor also has a disadvantage that the number of steps is increased at the time of its manufacture.

  On the other hand, in the multilayer chip varistor shown in FIG. 7, not only the surface of the varistor element 10 but also the base electrode 14 is covered with the glass layer 15, so that the plating solution rarely enters the inside of the varistor element 10. However, since the glass layer 15 has low conductivity, conduction between the base electrode layer 14 and the outer electrode layer 16 is insufficient, and the resistance value of the entire external electrode tends to increase. In addition, when manufacturing such a laminated chip varistor, an increase in the number of steps for forming the glass layer 15 has also been a problem.

  Furthermore, in the multilayer chip varistor described in Patent Document 4, the electrical conductivity of the glass frit contained in the conductive paste is about 5 to 6 orders of magnitude lower than that of silver which is a normal electrode material. When the content of is set to an amount that does not cause a decrease in plating solution resistance, sufficient conduction between the underlying electrode layer and the outer electrode layer is often not obtained.

  Furthermore, in the conductive pastes described in Patent Documents 5 and 6, although the glass frit itself has high plating solution resistance, it is difficult to form a dense external electrode. For this reason, in a laminated element having an external electrode formed from such a conductive paste, the plating solution tends to easily enter into the element body.

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a multilayer chip varistor having a reduced varistor characteristic even when the surface of an external electrode is further plated, and a method of manufacturing the same. And

  In order to achieve the above object, the present invention provides a varistor element having a plurality of varistor layers, and an internal electrode arranged so as to sandwich each of the varistor layers. Provided is a multilayer chip varistor comprising an external electrode connected to an electrode, and a glass layer formed between the varistor element and the external electrode.

  The multilayer chip varistor having the above configuration has a glass layer between the varistor element and the external electrode. For this reason, when plating is further performed on the external electrode surface, even if the plating solution passes through the external electrode, the glass layer prevents the plating solution from entering the element body. As a result, the laminated chip varistor after the plating has a very small decrease in the varistor characteristics as compared with the one before the plating.

  In the multilayer chip varistor, the glass layer covers 10% or more of the entire length of the region covered by the external electrode in the varistor body in a cross section passing through the center in the width direction of the external electrode. Preferably, it is formed. This makes it possible to more effectively reduce the penetration of the plating solution into the varistor element. From the same viewpoint, the thickness of the glass layer is more preferably 0.1 μm or more.

  More specifically, the external electrodes in the multilayer chip varistor are formed by firing a conductive paste containing a glass material, and when the glass layer fires the conductive paste, It is preferable that it is formed by a glass substance eluted from the conductive paste.

  In this case, it is not necessary to separately perform a process for forming a glass layer as in the above-described related art, thereby simplifying a manufacturing process for manufacturing a multilayer chip varistor.

  The conductive paste used at this time contains a metal and a glass substance, and the content of the glass substance at this time is preferably 2 to 15% by mass based on the total mass of the metal and the glass substance. When the conductive paste has such a composition, the glass substance is more easily eluted from the conductive paste.

  In the above-mentioned multilayer chip varistor, the external electrode contains silver or an alloy containing silver as a main component and a glass material, and the internal electrode contains palladium or platinum, or an alloy containing these metals as a main component. More preferably, it contains

  Further, the multilayer chip varistor of the present invention has a structure in which the internal electrode protrudes from the varistor element body to the external electrode side, and at least a root portion of the internal electrode protruding to the external electrode side is covered with a glass layer. It is more preferable to have one.

  When the multilayer chip varistor has such a structure, the bonding state between the internal electrode and the external electrode is improved, the contact state between the two is improved, and the base of the internal electrode is covered with a glass layer. This makes it more difficult for the plating solution to enter the varistor element.

  Further, a method for manufacturing a multilayer chip varistor according to the present invention is a method for easily manufacturing a multilayer chip varistor having the above configuration, comprising a plurality of varistor layers, and an internal electrode arranged so as to sandwich the respective varistor layers. Forming a varistor element having a varistor element, applying a conductive paste containing a glass material to an end of the varistor element, and firing the applied conductive paste to form an external electrode, A step of forming a glass layer between the varistor element and the external electrode by eluting a glass substance contained in the paste.

  According to such a manufacturing method, a glass layer can be easily formed between the varistor layer and the external electrode. In the multilayer chip varistor thus obtained, even when the external electrode surface is further plated, the glass layer prevents the plating solution from entering the varistor body. As a result, the reduction in varistor characteristics due to plating is extremely small.

  In this manufacturing method, the glass layer is formed so as to cover at least 10% of the entire length of the region covered by the external electrode in the varistor element in a cross section passing through the center in the width direction of the external electrode. Is preferred. Further, it is more preferable that the glass layer is formed so that its thickness is 0.1 μm or more. By doing so, the intrusion of the plating solution into the varistor element during plating can be more effectively suppressed.

  The firing of the conductive paste is preferably performed at a temperature 70 ° C. or higher than the softening temperature of the glass substance in the paste, and more preferably 700 ° C. or higher. When the conductive paste is fired at such a temperature, the glass substance is more easily eluted from the conductive paste, and a glass layer satisfying the above conditions can be easily formed.

  According to the present invention, since the glass layer 4 is provided between the varistor element 1 and the external electrode 3a, even if the plating solution passes through the external electrode 3a during plating, the plating solution is applied to the varistor element. Thus, it is possible to provide the multilayer chip varistor 100 in which the varistor characteristics are not significantly deteriorated due to entering the inside of the varistor 100.

  Further, since the glass layer 4 is formed by the glass frit eluted from the electrode material at the time of forming the external electrode 3a, it is not necessary to perform a separate step for forming the glass layer 4, thereby eliminating In addition, it is easy to manufacture a multilayer chip varistor having excellent plating solution resistance.

  Furthermore, since the multilayer chip varistor 100 has such characteristics, even if the multilayer chip varistor 100 is mounted on a substrate by reflow, the deterioration of the varistor characteristics due to heat history due to reflow is small, and It will be highly reliable.

  Hereinafter, preferred embodiments of the present invention will be described in detail. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description. In addition, for convenience of illustration, the dimensional ratios in the drawings are not limited to the illustrated values, and do not always match those described. Further, positional relationships such as up, down, left, and right are based on the positional relationships in the drawings unless otherwise specified.

  First, a multilayer chip varistor according to a preferred embodiment will be described with reference to FIGS. FIG. 1 is a sectional view showing a multilayer chip varistor according to a preferred embodiment. FIG. 2 is a side view showing the multilayer chip varistor 100. The multilayer chip varistor 100 has a varistor element 1 and an external terminal 3 provided at an end of the varistor element 1, and a glass layer 4 is provided between the varistor element 1 and the external terminal 3. Is formed.

  In this multilayer chip varistor 100, the varistor element 1 includes varistor layers 1a, 1b, 1c and internal electrodes 2a, 2b arranged so as to sandwich the varistor layer 1b. The external terminal 3 has an external electrode 3a, plating layers 3b and 3c in this order from the varistor element 1 side. Further, the internal electrode 2a and the internal electrode 2b are formed (extracted) such that their one end portions are exposed on different sides of the opposing end surfaces of the varistor element body 1, respectively, and are connected to the external electrode 3a. Have been.

  The varistor layers 1a, 1b, 1c can be applied without any particular limitation as long as they are made of a varistor material that can exhibit varistor characteristics. More specifically, a preferable example includes ZnO as a main component, and a rare earth element such as Pr, an auxiliary component such as Bi, and a trace additive such as Al mixed in the ZnO.

  Examples of the internal electrodes 2a and 2b include a single metal such as Pt, Pd, and Ag or an alloy or a compound thereof, which is usually used as an internal electrode of a multilayer chip varistor. Ag-Pd alloy and Ag-Pt alloy are preferable.

  As the external electrode 3a, an electrode composed of the same electrode material as the internal electrodes 2a and 2b can be exemplified. Above all, those composed of Ag alone or Ag-Pd alloy are preferable. It is more preferable that the external electrode 3a further include a glass substance such as a glass frit in addition to the above-mentioned metal. When the external electrode 3a contains the glass frit in this manner, the bonding property to the varistor element 1 is improved.

  The thickness of the external electrode 3a is preferably 5 to 100 μm, more preferably 20 to 70 μm. This makes it difficult for the plating solution during plating to pass through the external electrode 3a itself, and the synergistic effect with the glass layer 4 makes it possible to further reduce the penetration of the plating solution into the varistor element 1.

  The internal electrodes 2a, 2b and the external electrodes 3a are preferably made of different metals each having a face-centered cubic crystal structure in order to promote the effect of improving the bondability between the two by the Kirkendall effect described later. preferable. From such a viewpoint, it is preferable that the external electrode 3a contains silver or an alloy containing silver as a main component, and the internal electrodes 2a and 2b contain palladium or platinum, or an alloy containing these metals as a main component. Is more preferable.

  The plating layer 3b has a function of preventing solder erosion when mounting the multilayer chip varistor 100 on a substrate or the like by reflow. As the plating layer 3b, a layer made of Ni formed by electrolytic plating is preferable. Further, the plating layer 3c has a property of improving the solder wettability at the time of reflow, and is preferably made of a material having a good affinity for the solder, such as solder or Sn.

  The glass layer 4 is made of a glass material, and suppresses a plating solution from entering the varistor element during plating. As described above, when the external electrode 3a includes the glass frit, the glass layer 4 is formed by elution of the glass frit contained in the conductive paste for forming the external electrode 3a when the external electrode 3a is formed. It is more preferable that it is. In this case, it is not necessary to separately perform a process for forming the glass layer 4, and the manufacturing process of the multilayer chip varistor 100 can be simplified.

As the glass layer 4, B ₂ O ₃ —ZnO—Al ₂ O ₃ —SrO based glass, B ₂ O ₃ —SiO ₂ —ZnO based glass, B ₂ O ₃ —SiO ₂ —ZnO—Al ₂ O ₃ based glass _glass, SiO ₂ -BaO-Li 2 O-based _glass, B ₂ O ₃ -SiO ₂ -ZnO based _{glass, B 2 O 3 -SiO 2 -Na} 2 O -based _{glass, B 2 O 3 -SiO 2 -ZnO} -Al is composed of ₂ O ₃ -SrO based glass materials can be exemplified.

In the multilayer chip varistor 100, it is preferable that the glass layer 4 is formed so as to cover the end of the varistor element body 1 in the following ratio. In the present specification, the rate at which the glass layer 4 covers the ends of the varistor element body 1 is referred to as “coverage”, and this coverage is defined as follows. That is, the coverage ratio r (%) is such that the varistor element body 1 has a cross section passing through the center of the external terminal 3 (external electrode 3 a) in the width direction of the multilayer chip varistor 100 (cross section along the straight line L in FIG. 2). When the total length of the region (end surface) covered by the external electrode 3a is L1 and the length of the region (end surface) where the glass layer 4 is formed is L2, a value calculated by the following equation (1). And
r (%) = (L2 / L1) × 100 (1)

  In this specification, the “width direction of the external terminal 3 (external electrode 3a)” refers to a direction orthogonal to the laminating direction of the varistor element body 1 in the external terminal 3 (external electrode 3).

  In the multilayer chip varistor 100, the coverage by the glass layer 4 is preferably 10% or more, and more preferably 40% or more. When the coverage is 40% or more, the deterioration of the characteristics of the laminated chip varistor after plating is reduced to a level that hardly affects practical use.

  On the other hand, when the glass layer 4 is formed by elution from the conductive paste at the time of forming the external electrode 3a as described above, when the coverage by the glass layer 4 exceeds 80%, the varistor in the external electrode 3a is formed. The glass frit may elute undesirably on the surface opposite to the body 1. Therefore, from such a viewpoint, the coverage is particularly preferably 40 to 80%.

  Furthermore, the thickness of the glass layer 4 is preferably 0.1 μm or more, more preferably 0.4 to 1.5 μm, and even more preferably 0.4 to 0.8 μm. In addition, in this specification, the thickness of the glass layer 4 is a value obtained by observing a cross section cut along L in FIG. 2 with a scanning microscope and measuring the thickness of the glass layer 4 at five points. Means the average value of

  When the thickness of the glass layer 4 is 0.1 μm or more, it is possible to more effectively prevent the plating solution from entering the varistor element body 1. On the other hand, if the thickness of the glass layer 4 exceeds 1.5 μm, it may be difficult to form the plating layer 3b or the plating layer 3c on the surface of the external electrode 3a.

  The dimensions of the multilayer chip varistor 100 configured as described above can be appropriately changed depending on the application, but in general, the vertical length (the left-right direction in FIG. 2) is 0.4 to 5.6 mm, The width (horizontal direction in FIG. 1) is 0.2 to 0.6 mm, and the thickness (vertical direction in FIG. 1) is 0.2 to 1.9 mm. Further, the multilayer chip varistor array may have a configuration in which a plurality of external terminals 3 are vertically arranged on the same surface of a substrate or the like.

  Next, with reference to FIGS. 3 and 4, an example of a structure around a joint between the varistor element 1 and the external electrode 3a in the multilayer chip varistor having the above configuration will be described. FIG. 3 is a schematic cross-sectional view showing, in an enlarged manner, the periphery of the joint between the varistor element 1 and the external electrode 3a in the multilayer chip varistor having a coverage of 5%. FIG. 4 is a schematic cross-sectional view showing, in an enlarged scale, the vicinity of the joint between the varistor element body 1 and the external electrode 3a in the multilayer chip varistor having a coverage of 100%. The multilayer chip varistor shown in FIGS. 3 and 4 differs from the above-described multilayer chip varistor 100 in that it has a structure including a plurality of internal electrodes 2a or 2b.

  First, in the multilayer chip varistor shown in FIG. 3, a glass layer 4 formed by elution of a glass frit 4a is formed between the varistor element 1 and an external electrode 3a. Further, one end of the internal electrode 2 a is in a state of being exposed at an end of the varistor element body 1. At this time, the coverage by the glass layer 4 is 5%. Since the glass layer 4 is formed at the end of the varistor element 1 in this manner, even if the plating solution enters through the external electrode 3a during plating, the glass layer 4 allows the inside of the varistor element 1 to be formed. The plating solution can be prevented from entering the plating solution.

  In the laminated chip varistor shown in FIG. 4, a glass layer 4 formed by elution of a glass frit 4a is formed between a varistor element body 1 and a glass electrode 3a so as to have a coverage of 100%. I have. The internal electrode 2a protrudes toward the external electrode 3a, and the root of the protruding internal electrode 2a is covered with a glass layer 4b.

  As described above, in the multilayer chip varistor in which the coverage by the glass layer 4 is 100%, since the internal electrodes 2a protrude toward the external electrodes 3a, the bondability between the two is extremely good. Further, since the peripheral region of the base portion of the protruding internal electrode 2a is covered with the glass layer 4b, the intrusion of the plating solution from the joint portion between the internal electrode 3a and each varistor element body 1 is effectively suppressed. obtain. As a result, such a multilayer chip varistor is much more effective in suppressing the entry of the plating solution than the multilayer chip varistor shown in FIG.

  Next, an example of the region shown in FIGS. 3 and 4 will be specifically described with reference to the scanning electron micrographs shown in FIGS. 5A and 5B. FIG. 5A is a scanning electron micrograph showing the periphery of the joint between the varistor element 1 and the external electrode 3a in a laminated chip varistor having a glass layer coverage of 5%. FIG. 5B is a scanning electron micrograph showing the periphery of the joint between the varistor element 1 and the external electrode 3a in the laminated chip varistor having a glass layer coverage of 80%.

  As shown in FIG. 5A, in the multilayer chip varistor having a coverage of 5%, the glass layer 4 formed by elution of the glass frit 4a is formed at the boundary between the varistor element 1 and the external electrode 3a. The varistor element 4 is formed so as to cover a part thereof. Also, from FIG. 5A, it is confirmed that the internal electrode 2a is exposed on the end face of the varistor element 1.

  On the other hand, in the laminated chip varistor shown in FIG. 5B, the glass layer 4 formed by elution of the glass frit 4a is formed so as to cover most of the varistor element body 1. The glass layer 4 in this case is formed thicker than the glass layer 4 shown in FIG. 5A. In addition, it is confirmed that the internal electrode 2a protrudes largely toward the external electrode 3a, and that the protruding peripheral portion of the external electrode 2a is covered with the glass layer 4b.

  Next, a preferred embodiment of a method for manufacturing the multilayer chip varistor 100 having the above configuration will be described. First, a green chip in a state before the varistor element body 1 is sintered is formed by a printing method, a sheet method, or the like.

  When forming a green chip by the former printing method, first, a varistor paste and a conductive paste for internal electrodes are prepared. Examples of the varistor paste include an organic paste obtained by mixing a varistor material and an organic vehicle, and an aqueous paste obtained by mixing a varistor material and an aqueous mixed solution.

  As the varistor material, a material exhibiting varistor characteristics after firing can be selected and used, and a Zn oxide such as ZnO or a Zn compound which forms a Zn oxide by firing is preferable. Examples of the Zn compound that forms a Zn oxide by firing include a carbonate, a nitrate, an oxalate, and an organometallic compound of Zn. These Zn oxides or Zn compounds may be used in appropriate combination.

  Further, in addition to the Zn oxide or the Zn compound, a rare earth element such as Pr (praseodymium), a subcomponent such as Bi, and a trace additive such as Al may be added to the varistor material. It is preferable to use a varistor material having such a composition having an average particle size of about 0.3 to 2 μm.

  Examples of the organic vehicle to be incorporated into the organic paste include those in which a binder is dissolved in an organic solvent. As the binder, those generally used in the production of organic vehicles can be appropriately selected and used, and examples thereof include ethyl cellulose and polyvinyl butyral. Examples of the organic solvent include terpionaire, butyl carbitol, acetone, and toluene.

  Examples of the aqueous mixed solution used for the aqueous paste include those in which a water-soluble binder, a dispersant, and the like are dispersed in water. The water-soluble binder can be appropriately selected from polyvinyl alcohol, cellulose, water-soluble acrylic resin, emulsion and the like.

  The conductive paste for the internal electrode is prepared by kneading a conductive material constituting the internal electrode, or an oxide that becomes a conductive material after firing, an organometallic compound or a resinate, and the organic vehicle as described above. Things. As the conductive material constituting the internal electrode at this time, a simple metal of Pd or Pt, an Ag-Pd alloy or an Ag-Pt alloy is preferable.

  When an organic vehicle is used for preparing these pastes, the content of the binder is preferably 1 to 5% by weight based on the total weight of the organic vehicle. The content of the organic solvent is preferably set to 10 to 50% by weight based on the total weight of the organic vehicle. In addition, various dispersants, plasticizers, dielectrics, insulators, and the like can be added to such a paste as needed. In the present invention, “parts by mass” is substantially equivalent to the weight reference value (“parts by weight”) (the same applies hereinafter).

  In the production of a green chip by a printing method, after preparing the paste for the varistor and the conductive paste for the internal electrode as described above, the above-mentioned paste for the varistor is applied a plurality of times onto a substrate such as polyethylene terephthalate to obtain a predetermined paste. The varistor layer 1c in a green state is formed to have a thickness. Next, on the varistor layer 1c in the green state, a conductive paste for an internal electrode is applied in a predetermined pattern to form the internal electrode 2b in the green state.

  Thereafter, a varistor paste, a conductive paste for the internal electrodes, and a varistor paste are sequentially applied on the green internal electrodes 2b to form a green varistor layer 1b, an internal electrode 2a, and a varistor layer 1a. Obtain a laminate. Then, the obtained laminate is pressed and pressurized while being heated, and then cut into a predetermined shape to obtain a green chip. It is preferable that the conductive paste for the internal electrode is applied in such a pattern that the internal electrodes 2a and 2b have their one ends exposed to different sides of the opposite end faces of the green chip.

  On the other hand, when manufacturing a green chip by the latter sheet method, first, the above-mentioned varistor paste is formed into a sheet shape, a predetermined number of the varistor pastes are stacked to a desired thickness, and a green sheet for forming a varistor layer is formed. To form Next, on the green sheet, the above-mentioned conductive paste for an internal electrode is printed in a predetermined pattern to form a sheet including a varistor layer and an internal electrode in a green state.

  After preparing two sheets, these sheets are arranged so that the internal electrodes are opposed to each other, and are stacked so as to sandwich the above-mentioned green sheet for forming a varistor layer therebetween, thereby obtaining a laminate. Then, the laminate is pressed and pressurized while being heated, and then cut into a predetermined shape to obtain a green chip.

  In manufacturing the multilayer chip varistor 100, after forming a green chip by the above-described printing method or sheet method, the green chip is subjected to a binder removal treatment. The binder removal treatment can be performed, for example, by raising the temperature in an air atmosphere at about 5 to 300 ° C./hour, and then keeping the temperature at about 180 to 400 ° C. for 0.5 to 24 hours.

  Thereafter, the green chip after the binder removal treatment is fired to obtain the varistor element body 1. The firing of the green chip is performed, for example, by raising the temperature under the condition of about 50 to 500 ° C./hour in an air atmosphere, maintaining the temperature at 1000 to 1400 ° C. for about 0.5 to 8 hours, and further about 50 to 500 ° C./hour. It can be carried out by cooling at a speed of

  If the holding temperature during this firing is lower than 1000 ° C., the densification of the internal electrodes 2a, 2b and the varistor layers 1a, 1b, 1c tends to be insufficient. On the other hand, when the holding temperature exceeds 1400 ° C., the internal electrodes 2 a and 2 b are excessively sintered and partially spherical, whereby the contact area with the varistor layers 1 a, 1 b and 1 c is reduced, and the varistor characteristics are reduced. Tends to decrease.

  After the end face (end) of the varistor element body 1 thus obtained is subjected to barrel polishing or sand blasting, a conductive paste for an external electrode is printed or transferred to the end face, and further heated. By firing, the external electrodes 3a are formed. In the case where the conductive paste for an external electrode contains glass frit, the firing (heating) temperature of the conductive paste is preferably 70 ° C. or more higher than the softening temperature of the glass frit. The temperature is preferably set to 700 ° C. or higher for the conductive paste used.

  As the conductive paste for the external electrode, a paste prepared in the same manner as the conductive paste for the internal electrode can be used except that a conductive material for the external electrode is blended. The conductive material for the external electrode used at this time is preferably a metal such as Ag alone or an Ag-Pd alloy. In addition, from the viewpoint of improving the adhesion of the external electrode 3a to the varistor element 1 and easily forming the glass layer 4, the conductive paste for the external electrode contains a glass material such as a glass frit. Is preferred. When glass frit is contained in the conductive paste for an external electrode, the content of glass frit is preferably 2 to 15% by mass based on the total mass of the conductive material (metal) and glass frit.

  As described above, when the conductive paste for an external electrode contains glass frit, the glass frit in the conductive paste is eluted from the electrode material due to a high temperature condition during firing. The glass layer 4 is formed between the varistor element 1 and the external electrode 3 by attaching the glass frit eluted from the electrode material to the end face of the varistor element 1.

  In the manufacture of the laminated chip varistor 100, the glass layer 4 does not necessarily need to be formed of glass frit eluted from the conductive paste. For example, a glass material is adhered to the end surface of the varistor element 1. After that, a process such as baking may be separately performed.

  After forming the glass layer 4 and the external electrode 3a in this manner, a plating layer 3b made of Ni is formed on the external electrode 3a, and a plating layer 3c made of solder, Sn, or the like is further formed on the plating layer 3b. Then, a multilayer chip varistor 100 is obtained. Electroplating is suitable as a plating method in this case.

  As described above, the laminated chip varistor 100 manufactured as described above has a state in which one end of the internal electrodes 2a and 2b protrudes toward the external electrode 3a, and at least a root portion of the protruding internal electrodes 2a and 2b. Is covered by the glass layer. Such a shape in the multilayer chip varistor 100 is considered to be formed as follows.

  That is, in a suitable case, each of the internal electrodes 2a and 2b and the external electrode 3a in the multilayer chip varistor 100 contains a different kind of metal having a face-centered cubic crystal structure such as Ag, Pd, or Pt. When the internal electrodes 2a, 2b and the external electrode 3a contain such metals, the high temperature during firing causes the so-called Kirkendall effect, in which these metals diffuse through their contact interfaces.

  When the Kirkendall effect occurs, the metal contained in the internal electrodes 2a and 2b diffuses to the external electrode 3a side, and the metal contained in the external electrode 3a diffuses to the internal electrodes 2a and 2b. , 2b project toward the external electrode 3a.

  In this case, due to the diffusion of the metal, the joint between the internal electrodes 2a and 2b and the external electrode 3a and the vicinity thereof are densified, and the area around the protruding portions of the internal electrodes 2a and 2b is covered with a glass layer. It becomes. As a result, the bondability between the internal electrodes 2a and 2b and the external electrode 3a is improved, and the penetration of the plating solution into the varistor element 1 during plating is further reduced.

  When the Kirkendall effect occurs, the cavities formed between the internal electrodes 2a, 2b and the varistor layers 1a, 1b, 1c due to the diffusion of atoms elute during the firing of the external electrode 3a. Becomes filled by glass. In this case, the intrusion of the plating solution into the varistor element body 1 tends to be more difficult to occur.

<Manufacture of multilayer chip varistor>
First, B ₂ O ₃ —ZnO—Al ₂ O ₃ —SrO-based glass is used as a glass frit, Ag is used as a conductive powder (metal), and ethyl cellulose and terpionaire are used as an organic vehicle. A conductive paste for forming external electrodes was obtained. At this time, the compounding amount of the glass frit was 1 to 16% by weight based on the total weight with the Ag powder. Further, the addition amounts of ethyl cellulose and terpionaire were such that when the total weight of the Ag powder and the glass frit was 100 parts by weight, ethyl cellulose was 15 parts by weight, and terpioneer was 10 parts by weight. The amount of the glass frit is set to 1% by weight or more because if the amount of the glass frit is less than this, the bonding strength between the external electrode and the element after baking may be insufficient. .

  Next, a varistor element including a varistor layer containing ZnO as a main component and an internal electrode made of Pd was formed. The above-mentioned conductive paste was applied to the end of the obtained varistor element body, dried, and then baked in air at 700 ° C. for 10 minutes. External electrodes having a thickness of 3 μm, 5 μm or 50 μm were formed. The firing temperature (700 ° C.) at this time is usually about 20 ° C. higher than the temperature at which the external electrode containing the glass frit is fired. In addition, the thickness of the external electrode was a value obtained by averaging the maximum value of the thickness of each external electrode formed on both end surfaces of the varistor element.

  Next, a Ni plating layer and a Sn plating layer were sequentially formed on the external electrodes by plating to obtain a multilayer chip varistor having the structure shown in FIG. At this time, the average thickness of the Ni plating layer was 2 μm, and the average thickness of the Sn plating layer was 5 μm. In addition, these thickness values were calculated by measuring five places in a scanning electron microscope photograph magnified 2000 times and calculating the average value of the obtained thickness.

<Characteristic evaluation>
Using each laminated chip varistor obtained by changing the compounding amount of the glass frit in the conductive paste and the thickness of the external electrode, the thickness of the glass layer in each laminated chip varistor and the glass layer according to the method described below. , The rate of change in varistor voltage after plating, and the rate of characteristic degradation after reflow. Table 1 summarizes the amount of glass frit, the thickness of the external electrode, and the results obtained by the above measurements in each laminated chip varistor.

(Measurement of thickness and coverage of glass layer)
First, as for the thickness of the glass layer, a cross section (cross section along the straight line L in FIG. 2) passing through the center in the width direction of the external terminal (external electrode) in the multilayer chip varistor is observed with a scanning microscope, and is enlarged 2000 times. The thickness of the glass layer formed on one end surface of the varistor element was measured at five points from the scanning electron micrograph thus obtained, and the thickness was obtained by calculating the average of the obtained values.

Also, the coverage r (%) of the glass layer was determined from the scanning electron micrograph of the same cross section as in the above, from the total length L1 of the region (end face) where the varistor element was covered with the external electrode and the formation of the glass layer. The length L2 of each of the regions (end faces) was measured, and calculated from the obtained values of L1 and L2 by the following equation (1).
r (%) = (L2 / L1) × 100 (1)

(Measurement of varistor voltage change rate)
The varistor voltage (voltage between external terminals when a current of 1 mA flows between external terminals in the multilayer chip varistor) before and after forming the Ni plating layer and the Sn plating layer in each multilayer chip varistor was measured and obtained. The rate of change of the varistor voltage due to the plating process was calculated from the value. Specifically, first, 20 samples were manufactured for each multilayer chip varistor. Next, after measuring the varistor voltage of the sample in each multilayer chip varistor before plating, each sample was subjected to plating treatment, and the varistor voltage was measured for each sample after plating. The varistor voltage change rate ΔVm (%) is expressed by the following equation (2), where V1 is the average value of the varistor voltage obtained in each sample before plating, and V2 is the average value of the varistor voltage obtained after plating. As shown, it was calculated by dividing the difference between V2 and V1 by V1.
ΔVm (%) = {(V2−V1) / V1} × 100 (2)

(Measurement of characteristic deterioration rate after reflow)
The varistor voltage before and after the reflow was performed on each laminated chip varistor on which the Ni plating layer and the Sn plating layer were formed was measured, and the characteristic deterioration rate after the reflow was calculated from the obtained values. Specifically, first, 20 samples of the multilayer chip varistor having both plating layers were produced. Next, after measuring the varistor voltage V3 obtained in each sample before reflow, each sample was mounted on a substrate by reflow, and the varistor voltage V4 obtained in each sample after reflow was measured. Using the obtained values of V3 and V4, the change rate ΔVr (%) of the varistor voltage obtained for each sample was calculated according to the following equation (3). Samples having a varistor voltage change rate of 10% or more are determined to be defective, and the number of samples determined to be defective out of the 20 samples prepared for each multilayer chip varistor is counted to determine the number of samples after reflow. The characteristic deterioration rate was measured.
ΔVr (%) = {(V4−V3) / V3} × 100 (3)

  As shown in Table 1, first, the content of the glass frit in the conductive paste was set to 1% by weight, and the thickness of the external electrode was set to 50 μm. The laminated chip varistor No. 1 had a glass layer coverage of 5%. According to this multilayer chip varistor, the rate of change of the varistor voltage was -12%, and the number of defects in 20 samples was two. Further, in such a sample, it was difficult to measure the thickness of the glass layer.

  Furthermore, the content of the glass frit was 1.5% by weight, and the thickness of the external electrode was 50 μm. In the multilayer chip varistor No. 2, the thickness of the glass layer was 0.1 μm and the coverage was 8%. As a result, the rate of change of the varistor voltage was -8%, and the number of defects in 20 samples was one.

  In addition, the content of the glass frit was 2% by weight, and the thickness of the external electrode was 50 μm. In the multilayer chip varistor No. 3, the thickness of the glass layer was 0.1 μm and the coverage was 10%. According to the multilayer chip varistor, the rate of change of the varistor voltage was -5%, and the number of defects in 20 samples was 0.

  Further, the content of the glass frit was increased to 5 to 15% by weight, and the thickness of the external electrode was set to 50 μm. In the multilayer chip varistors Nos. 4 to 6, the thicknesses of the glass layers were all 0.4 μm or more, and the coverage of the glass layers was 40% or more. As a result, the average value of the change rate of the varistor voltage was -2 to -0.5%, and the number of defects in 20 samples was 0. Note that the glass frit content was 16% by weight. With the multilayer chip varistor No. 7, it was difficult to form a plating layer on the external electrodes.

  From the above, the multilayer chip varistor in which the glass layer is formed between the varistor element and the external electrode has a small decrease in the varistor voltage even when the plating layer is formed on the external electrode by plating. There was found. Further, it has been found that even when these laminated chip varistors are mounted on a substrate by reflow, the varistor characteristics are sufficiently maintained.

  From the above results, relatively favorable results can be obtained when the content of the glass frit is 2 to 15% by weight, the thickness of the glass layer is 0.1 μm to 1.5 μm, and the coverage is 10 to 100%. It has been found. Furthermore, when the content of the glass frit is 5 to 10%, the thickness of the glass layer is 0.4 to 0.9 μm, and the coverage is 40 to 80%, the deterioration of the varistor characteristics due to plating is suppressed most remarkably. It turned out to get.

It is sectional drawing which shows the laminated chip varistor which concerns on suitable embodiment. FIG. 2 is a side view showing the multilayer chip varistor 100. It is a schematic sectional view which expands and shows the periphery of the junction part of the varistor element body 1 and the external electrode 3a in the multilayer chip varistor with a coverage of 5%. FIG. 4 is a schematic cross-sectional view showing, in an enlarged manner, the periphery of a joint between a varistor element body 1 and an external electrode 3a in a multilayer chip varistor having a coverage of 100%. A is a scanning electron micrograph showing the periphery of the joint between the varistor element 1 and the external electrode 3a in the multilayer chip varistor having a coverage of 5% by the glass layer 4, and B is the coverage by the glass layer 4. Is a scanning electron micrograph showing the vicinity of a joint between a varistor element body 1 and an external electrode 3a in a multilayer chip varistor having a ratio of 80%. It is sectional drawing which shows the conventional laminated chip varistor. It is sectional drawing which shows the conventional laminated chip varistor.

Explanation of reference numerals

  DESCRIPTION OF SYMBOLS 1 ... Varistor body, 1a, 1b, 1c ... Varistor layer, 2a, 2b ... Internal electrode, 3 ... External terminal, 3a ... External electrode, 3b, 3c ... Plating layer, 4 ... Glass layer, 4a ... Glass frit, 4b ... glass layer, 100 ... laminated chip varistor,

Claims (12)

A plurality of varistor layers, and a varistor element having internal electrodes arranged to sandwich each varistor layer,
An external electrode formed at an end of the varistor element body and connected to the internal electrode;
A glass layer formed between the varistor element and the external electrode,
A multilayer chip varistor comprising:   The glass layer is formed so as to cover an area of 10% or more of the entire length of the area of the varistor element covered with the external electrode in a cross section passing through the center in the width direction of the external electrode. The multilayer chip varistor according to claim 1.   The multilayer chip varistor according to claim 1, wherein the glass layer has a thickness of 0.1 μm or more. The external electrode is formed by firing a conductive paste containing a glass material, and
4. The multilayer chip varistor according to claim 1, wherein the glass layer is formed of the glass substance eluted from the conductive paste when firing the conductive paste. 5.   The multilayer chip varistor according to claim 4, wherein the conductive paste includes a metal and the glass material, and a content of the glass material is 2 to 15% by mass based on a total mass of the metal and the glass material. . The external electrode contains silver or an alloy containing silver as a main component, and
The multilayer chip varistor according to any one of claims 1 to 5, wherein the internal electrode includes palladium, platinum, or an alloy mainly containing these metals. The internal electrode projects from the varistor element body toward the external electrode, and
The multilayer chip varistor according to claim 1, wherein at least a root portion of the internal electrode protruding toward the external electrode is covered with the glass layer. A plurality of varistor layers, and a step of forming a varistor element body having internal electrodes arranged to sandwich the respective varistor layers,
A step of applying a conductive paste containing a glass material to an end of the varistor element body,
Baking the applied conductive paste to form an external electrode, and forming a glass layer between the varistor element and the external electrode by eluting the glass substance contained in the conductive paste. When,
A method for manufacturing a multilayer chip varistor having: The glass layer is formed so as to cover an area of 10% or more of the entire length of the area covered by the external electrode in the varistor element in a cross section passing through the center in the width direction of the external electrode. Item 9. The method for manufacturing a multilayer chip varistor according to Item 8. The method for manufacturing a multilayer chip varistor according to claim 8, wherein the glass layer is formed to have a thickness of 0.1 μm or more. The method of manufacturing a multilayer chip varistor according to any one of claims 8 to 10, wherein the firing of the conductive paste is performed at a temperature higher than the softening temperature of the glass material by 70C or more. The method for manufacturing a multilayer chip varistor according to claim 8, wherein the firing of the conductive paste is performed at 700 ° C. or higher.

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