JP2004200967A - Video multiplexer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video multiplexer reduced in cost by decreasing a required capacity of a buffer to be mounted thereon even in the case of data different in a material speed and whose capacity depends on a data rate of a source and a packet size. <P>SOLUTION: The video multiplexer is provided with: a video signal packetizing circuit 11a for packetizing a video signal; an effective data count circuit 12a for counting the number of passing packets within a prescribed time to measure a data rate; a priority decision circuit 13 for prioritizing the packet data in orders of faster data rates on the basis of the measured data; and a multiplexer circuit 14 for selecting the packet data of the video signal on the basis of the priority from the priority decision circuit 13 to generate multiplexed data. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【００２８】
この式より入力ビットレート、パケットサイズ、 出力ビットレートは決まっているため、 待たせるパケットの数をできるだけ小さくする必要がある。従来の方式でCH1,CH2,CH3,CH4から同時に送出要求が出たとき、CH2からサービスが始まったとするとサービスの順番は、
CH2→CH3→CH4→CH1
となりHDTVのCH1が送出されるまでHDTVレートで3パケット待たされることになる。一方優先順位をレートの高い方に設定した場合には、
CH2→CH1→CH1→CH1→CH3→CH1→CH1→CH4→CH1→CH1
の順番となりSDTVのCH4が送出されるまでSDTVレートで3パケット待たされることになる。したがって、待たせるパケットの数は、従来の方が多いものの速度に関しては、HDTV：SDTV=5.5：1であるため、優先順位を速度の速い順に並べた方がバッファメモリの容量が少なくてすむ。
【００２９】
図３は以上説明した考察事例２について、優先順位を速度の速い順に並べた場合のバッファメモリの遷移図を示したものである。同図の一点鎖線を挟んで上側が送出要求側、下側が実際の多重送出側である。各CHの対応関係を説明すると、送出要求側においてHD_WRITE(A)〜(G)がCH1に相当し、SD1_WRITE(A)とSD1_WRITE(B)がCH2に相当し、SD2_WRITE(A)とSD2_WRITE(B)がCH3に相当し、SD3_WRITE(A)とSD3_WRITE(B)がCH4に相当する。一方、多重送出側において、HD_READ(A)〜(G)がCH1に相当し、SD1_READ(A)がCH2に相当し、SD2_READ(A)がCH3に相当し、SD3_READ(A)がCH4に相当する。
【００３０】
【発明の効果】
本発明により、多重化のとき使用するバッファメモリの容量を増大させることなく多重化することができる。
【００３１】
また、速度レートの高い順に優先順位をつけることにより、バッファメモリのサイズが小さくても、オーバーフローすることなしに多重する事ができる。
【００３２】
【図面の簡単な説明】
【図１】本発明の実施形態を示したブロック図である。
【図２】本発明の実施形態における有効データカウンタ回路のブロック図である。
【図３】考察事例２におけるバッファメモリの遷移図である。
【符号の説明】
１１ａ 映像信号パケット化回路
１２ａ 有効データカウント回路
１３ 優先順位決定回路
１４ 多重化回路
２１ 加算部
２２ データセレクタＡ
２３ データセレクタＢ
２４ クロック発生部
２５ フリップフロップＡ
２６ データセレクタＣ
２７ フリップフロップＢ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an apparatus for multiplexing a plurality of video signals and sending the multiplexed signals to one line. More specifically, the video signal is transmitted in a group called a packet for multiplexing, and the multiplexing is performed without increasing the capacity of a FIFO (First-in First-out) memory for holding the packet at that time. The present invention relates to a video multiplexing device and a video multiplexing method that can be multiplexed.
[0002]
[Prior art]
When multiplexing multiple video signals and data and sending them out to one line, they can be sent out immediately if the line is free, but cannot be sent out immediately if another channel is using the line. So you need to keep waiting. At this time, when a large number of transmission requests are made, there is a round robin method for determining which one to output. This system is a system in which the priority order is changed in a ring shape each time a signal is transmitted, and a fair output opportunity can be given to an output request from each input. In the case of video signals, there are high definition television (HDTV) and standard television (SDTV).
[0003]
Even if HDTV and SDTV coexist, even if services are provided uniformly, the amount of memory to be stored will differ depending on the speed of the material. In other words, the capacity of the memory required for the waiting is obtained by multiplying the speed of the material by the time for the waiting. Therefore, the faster the speed of the material, the larger the memory. When the speed of the material is known in advance, the memory may be allocated depending on the material. However, in the case of the fixed assignment, the port is replaced every time the transmission material changes, which is not a preferable operation.
[0004]
Patent Document 1 discloses that code multiplexing is performed on video and audio information using an information compression and multiplexing technique based on MPEG (Moving Picture Expert Group) or the like, and a high quality program of a plurality of programs is performed under a limited transmission band. A method of converting video and audio data into a single bit stream is disclosed.
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. H11-340936 (full text of the specification, all drawings)
[0006]
[Problems to be solved by the invention]
In the case of the same buffer memory, when input is performed at high speed, the time required for storing in the buffer is short, and when input is performed at low speed, the time required for storing is long. When multiplexing a material input at a high speed and a material input at a low speed, a high-speed input material requires more output requests than a low-speed input. If the request is issued at the same time and the low-speed data is output, more buffer memory is required than when the high-speed data is processed with priority. It is sufficient to increase the capacity of the buffer memory so that it does not overflow at any time. However, the increase in the buffer memory increases the scale of hardware. When directly multiplexing HDTV or SDTV instead of a fixed format such as MPEG, it is necessary to change the packet size depending on the number of scanning lines and the number of pixels.
[0007]
Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to solve the above-mentioned problems, to reduce the necessary capacity of a buffer to be mounted even for data having different material speeds and packet sizes, thereby reducing costs. The purpose of the present invention is to provide a video multiplexing device.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a video multiplexing device according to the first aspect of the present invention includes a means for packetizing a video signal, a means for measuring the speed of data by counting the number of packets passing within a predetermined time, A multiplexing unit that switches the packet data of the video signal to generate multiplexed data based on the priority from the priority determining unit. It is characterized by having.
[0009]
In the video multiplexing apparatus according to the second aspect of the present invention, in the first aspect, the priority determining means assigns a video number to a plurality of input video signals and rearranges the video numbers in ascending order of the data rate. Output.
[0010]
Further, the video multiplexing apparatus according to the invention of claim 3 is characterized in that in claim 1 or 2, the updating of the priority is performed every time one packet is output.
[0011]
Further, in the video multiplexing method according to the invention of claim 4, the video signal is packetized, the number of packets passing within a predetermined time of the packet is counted, and the data speed is measured. It is characterized in that multiplexed data is generated by switching video signal packet data in a priority order from the fastest.
[0012]
In the video multiplexing method according to a fifth aspect of the present invention, in the fourth aspect, the priority order is determined by assigning video numbers to a plurality of input video signals and rearranging the video numbers in order of the data rate. Output.
[0013]
The video multiplexing method according to the invention of claim 6 is characterized in that in claim 4 or 5, the priority order is updated every time one packet is output.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a block diagram according to the embodiment of the present invention. Each of the video signals 1, 2, and 3 is a video input and has three channels in this example, but is not limited to three channels, and may have more channels. The multiplexed output is obtained by multiplexing the video signals 1, 2, and 3, and the data speed needs to be higher than the data rate obtained by adding the video signals 1, 2, and 3. If it is too small, all of the multiplexed data cannot be sent, causing an overflow of the memory and preventing normal transmission.
[0015]
Since the video signals are multiplexed, they are packetized by the video signal packetizing circuit 11a. The packetization is performed in units of a good division of the video signal, for example, for each line or 1/2 line of the video signal. The packetized data is input to the valid data count circuit 12a, and the number of valid data is measured at a common time interval for a certain period. The value is input to the priority determination circuit 13 as the speed value of the video signal. Similarly, the video signals 2 and 3 are packetized by the video signal packetizing circuit 11b and the video signal packetizing circuit 11c, and the effective data count circuit 12b and the valid data count circuit 12c measure the speed value applied to the video signal. And input to the priority determination circuit 13.
[0016]
The priority determination circuit 13 determines which video signal is to be output with priority based on the speed values of the three video signals. In the method of determining the priority here, rearrangement is performed based on the code amount (data rate) per unit time obtained by the valid data count circuits 12a, 12b, and 12c, and the priority is determined. Since the important thing in the rearrangement is not the code amount (data rate) itself but the data order from each video signal, the video input is given a video number indicating the material number. The numbers are 01 for the video signal 1, 02 for the video signal 2, 03 for the video signal 3, and so on. After rearranging in the order of the code amount (in order of higher data rate), the data indicating the video number is sent to the multiplexing circuit 14. The update of the priority is performed every time one packet is output. That is, after outputting the packet, the video material having the highest priority is selected from those requested to be output. By deciding the priority order in the order of the code amount (the order of the higher data rate) in this manner, the buffer memory in the multiplexing circuit 14 is prevented from being broken down and its capacity is minimized, and The circuit scale can be made compact. It should be noted that the method of determining such priorities is considered by the inventor, and will be described later in detail.
[0017]
The multiplexing circuit 14 multiplexes and outputs the multiplexed data according to the priority determined by the priority determining circuit 13 based on the code amount (data rate) obtained from the valid data counting circuits 12a, 12b and 12c. In this, a FIFO memory is built in, and even if there is an output request at the same time, the data is output from the one with the highest priority.
[0018]
FIG. 2 is a block diagram showing the inside of the valid data count circuits 12a, 12b and 12c described above. The counting is performed by selecting the previous count value input from the flip-flop A 25 and the count value incremented by the adder 21 by the data selector A 22. The count value selected here is latched by the flip-flop B 27 via the data selector B 23, the flip-flop A 25, and the data selector C 26, and this is used as the valid data count number. Send to The reset of the data selector B 23 and the update of the count number of the data selector C 26 are performed at predetermined intervals using a clock (1 second) from the clock generator 24 as a basic timing.
[0019]
Next, a description will be given of considerations made by the inventor regarding a method of determining a priority order in the order of a larger code amount (an order of a higher data rate) as described above.
[0020]
(Discussion example 1)
First, 8 channels of SDTV are multiplexed and multiplexed to a line of 2.488 Gbps SDH (Synchronous Digital Hierarchy). Find the memory capacity for 8 channels of SDTV in multiplexing.
One packet = 270 Word (32 Bit width) = 1080 Byte.
The data rate of one channel of SDTV is a transmission rate of 38.88 MHz, and the data width is 8 bits. Since the memory size is preferably 2 ^ n, 2 ^ 9 = 512 words. (Data width = 32Bit, Address width = 9Bit) The worst case is when 8CHs issue requests at the same time.
[0021]
First, the time from the arrival of the first packet to the arrival of the next packet is determined.
Since the transmission clock is 38.88 MHz, the time required to transmit one packet is 1080 × (1 / 38.88 MHz) = 27.78 μS.
Since 1H of SDTV is 63.5 μS and one packet is 1 / 2H,
63.5 μS / 2 = 31.75 μS.
Therefore, the percentage of data validity is
27.78 μS / 31.75 μS = 87%
And the time until the next packet arrives is
31.75 μS−27.78 μS = 3.97 μS.
[0022]
Next, the time until the data is accumulated in the remaining capacity of the FIFO memory is obtained.
512 Word-270 Word = 242 Word, with a transmission rate of 38.88 MHz, divided into 4 phases,
242 × (1 / 38.88 MHz) × 4 = 24.89 μS.
Therefore, if the reading of the FIFO memory is completed within 3.97 + 24.89 μS = 28.86 μS, no failure occurs.
[0023]
Next, the time required to read 7 packets of 7CH is obtained.
Since the reading speed of the FIFO memory is 77.76 MHz and one packet is 270 words,
270 × (1 / 77.76 MHz) × 7 CH = 24.30 μS.
Therefore, the size of the FIFO memory may be 32 bits in data width and 9 bits in address width.
[0024]
(Discussion example 2)
As another example, the memory capacity for HDTV 1CH and SDTV 3CH is obtained. In this case, HDTV and SDTV are mixed.
HDTV has one packet = 174 Word (32-bit width) = 696 Byte.
SDTV is one packet = 270 Word (32 Bit width) = 1080 Byte.
The data from the terminal unit has a transmission rate of 77.76 MHz and a data width of 32 Bit. Since the memory size is preferably 2 ^ n, consider 2 ^ 9 = 512 words (data width = 32Bit, address width = 9Bit). The same memory size is used for HDTV and SDTV so that the same buffer memory can be used even if the material to be transmitted changes. The worst case is when HDTV1CH and SDTV3CH make requests at the same time. Since the HDTV packet size is 174 Words, 2 packets + 164 Words are included in the 512 Word FIFO. Since the packet size of the SDTV is 270 words, one packet + 242 words can be stored in the 512 word FIFO.
[0025]
First, the time from the arrival of the first packet to the arrival of the next packet is determined. Since the transmission clock of HDTV is 77.76MHz, the time required to transmit one packet is
174 × (1 / 77.76 MHz) = 2.237 μS.
Since 1H of HDTV is 29.62 μS and one packet is 8H,
29.62 μS / 8 = 3.703 μS.
Therefore, the data validity period is
2.237μS / 3.703μS = 60%
And the time until the next packet arrives is
3.703μS −2.237μS = 1.466μS
It is.
[0026]
Next, the time until the data is accumulated in the remaining capacity of the FIFO memory is obtained.
The remaining capacity of the memory is 338 Word (512 Word-174 Word), and it is transferred at the transmission rate of 77.76 MHz.
338 × (1 / 77.76 MHz) = 4.34 μS.
Therefore, if the reading of the FIFO memory is completed within 5.812 μS (1.466 + 4.346 μS), no failure occurs. When HDTV and SDTV coexist, the transfer rate of HDTV is higher, so starting with SDTV packets that have become readable first will cause the HDTV buffer to fail. This problem can be avoided if HDTV packets are processed with priority.
[0027]
(General calculation of Discussion Case 2)
The example of the memory capacity in the case of HDTV 1CH and SDTV 3CH is shown. The bit rate of HDTV is 1485 Mbps (74.25 MHz × 20 Bit). The bit rate of SDTV shall be 270Mbps (13.5MHz x 20Bit). It is assumed that the input is four channels, HDTV is assigned to CH1, and SDTV is assigned to CH2, CH3, and CH4, respectively. The output bit rate is a total of 1485 Mbps + 270 Mbps × 3 = 2295 Mbps for one HDTV channel and three SDTV channels. If the bit rate is lower than this, no matter how much the capacity of the buffer memory is increased, it will break down. If the bit rate is higher than this, the line will be wastefully used and uneconomical. As another condition, a packet transmission request is issued after one packet of data is completed. The capacity of the buffer memory is the same size so that ports can be switched during operation while being shared by HDTV and SDTV. The capacity of the buffer memory is determined by the number of bits stored in other channels during output. This relationship is given by the following equation.
(Equation 1)

[0028]
Since the input bit rate, packet size, and output bit rate are determined from this equation, it is necessary to minimize the number of packets to be waited for. In the conventional method, when a transmission request is issued simultaneously from CH1, CH2, CH3, and CH4, if the service starts from CH2, the order of the services is as follows.
CH2 → CH3 → CH4 → CH1
Thus, three packets are waited at the HDTV rate until the HDTV CH1 is transmitted. On the other hand, if you set the priority to the higher rate,
CH2 → CH1 → CH1 → CH1 → CH3 → CH1 → CH1 → CH4 → CH1 → CH1
In this order, three packets are waited at the SDTV rate until CH4 of the SDTV is transmitted. Therefore, although the number of packets to be waited is larger in the conventional case, but the speed is HDTV: SDTV = 5.5: 1, the buffer memory capacity can be reduced by arranging the priorities in descending order of speed.
[0029]
FIG. 3 shows a transition diagram of the buffer memory in the case where the priorities are arranged in descending order of speed in the consideration example 2 described above. The upper side of the dashed line is the transmission request side, and the lower side is the actual multiplex transmission side. Explaining the correspondence of each CH, HD_WRITE (A) to (G) correspond to CH1, SD1_WRITE (A) and SD1_WRITE (B) correspond to CH2, and SD2_WRITE (A) and SD2_WRITE (B) on the transmission request side. ) Corresponds to CH3, and SD3_WRITE (A) and SD3_WRITE (B) correspond to CH4. On the multiplex transmission side, HD_READ (A) to (G) correspond to CH1, SD1_READ (A) corresponds to CH2, SD2_READ (A) corresponds to CH3, and SD3_READ (A) corresponds to CH4. .
[0030]
【The invention's effect】
According to the present invention, multiplexing can be performed without increasing the capacity of a buffer memory used for multiplexing.
[0031]
In addition, by assigning priorities in descending order of speed rate, multiplexing can be performed without overflow even if the size of the buffer memory is small.
[0032]
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram of a valid data counter circuit according to the embodiment of the present invention.
FIG. 3 is a transition diagram of a buffer memory in a consideration example 2;
[Explanation of symbols]
11a Video signal packetizing circuit 12a Effective data counting circuit 13 Priority determining circuit 14 Multiplexing circuit 21 Adder 22 Data selector A
23 Data Selector B
24 clock generator 25 flip-flop A
26 Data selector C
27 Flip-flop B

Claims (6)

Means for packetizing the video signal, means for measuring the speed of the data by counting the number of packets passing within a certain time, and priority determining means for prioritizing the measured data in order of decreasing speed, A video multiplexing apparatus comprising: multiplexing means for switching packet data of a video signal to generate multiplexed data based on the priority from the priority determining means. 2. The video multiplexing apparatus according to claim 1, wherein said priority order determination means assigns video numbers to a plurality of input video signals, and rearranges and outputs the video numbers in order of the data rate. . 3. The video multiplexing apparatus according to claim 1, wherein the updating of the priority is performed every time one packet is output. After packetizing the video signal and counting the number of packets passing within a certain time period of the packet and measuring the data speed, the video data packet data is switched by assigning a priority from the measured data in order of increasing speed. A video multiplexing method characterized by generating multiplexed data. 5. The video multiplexing method according to claim 4, wherein in the determination of the priority, a video number is assigned to a plurality of input video signals, and the video numbers are rearranged and output in ascending order of the data rate. . 6. The method according to claim 4, wherein the updating of the priority is performed every time one packet is output.

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