JP2004199293A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing the increase of a chip size while providing a clock signal generating circuit having a CR oscillator. <P>SOLUTION: This semiconductor integrated circuit 1 is provided with a clock signal generating circuit 2, an analog digital converter 3, a microprocessor 4 and a bus 5. The clock signal generating circuit 2 is applied with a reset signal 101 and a stop signal 102, and the reset signal 101 is outputted from an internal circuit which is not shown in a figure in order to start the clock signal generating circuit 2 in power supply or standby mode recovery, and a stop signal 102 is outputted from the internal circuit which is not shown in the figure in order to stop the clock signal generating circuit 2 in power supply disconnection or standby mode transition. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device configured as a semiconductor integrated circuit, and more particularly to a semiconductor device including a clock signal generation circuit.
[0002]
[Prior art]
Conventionally, for example, a clock signal generation circuit shown in FIG. 7 is used to generate a clock signal in a microcomputer system. FIG. 7 is a configuration diagram of a conventional clock signal generation circuit. As shown in FIG. 7, the conventional clock signal generation circuit includes an oscillator 206 which is a crystal oscillator which is high in accuracy but has a long oscillation stabilization time, and an oscillator 207 which is a low accuracy but has a CR oscillation in which the oscillation stabilization time is short. , A selector 208, a flip-flop 209, a counter 210, a flip-flop 211, a flip-flop 212, and an OR gate 213. When the flip-flop 209, the counter 210, the flip-flop 211 and the flip-flop 212 are reset by the reset signal 301 when the power is turned on or when returning from the standby mode, the oscillators 206 and 207 start oscillating, and the output signal of the oscillator 207 is output. Is sent from the selector 208 as a clock signal, and when a predetermined time sufficient for stabilizing the oscillation of the oscillator 206 elapses, the flip-flop 211 and the flip-flop 212 are set by the overflow signal of the counter 210 counting the output signal of the oscillator 206. The output signal of the oscillator 206 is sent out as a clock signal from the selector 208, and the oscillation of the oscillator 207 is stopped. Flip-flop 209 and the flip-flop 212 is set, the oscillation of the oscillator 206 and the oscillator 207 is adapted to be stopped (for example, see Patent Document 1.).
[0003]
[Patent Document 1]
JP-A-4-177516 (FIG. 1)
[0004]
[Problems to be solved by the invention]
However, the oscillator 207, which is a CR oscillator, requires a delay circuit including a resistor R and a capacitor C in an oscillation feedback loop of, for example, an odd-stage cascade-connected inverter array, so that the conventional clock signal generation circuit shown in FIG. If a single-chip semiconductor integrated circuit is to be configured together with a peripheral function block such as a processor, an analog-to-digital converter, or a digital-to-analog converter, a delay resistor R and a capacitor C must be provided only for the oscillator 207. However, there arises a problem that the layout area, that is, the chip size of the semiconductor integrated circuit is increased accordingly.
[0005]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor device capable of suppressing an increase in chip size while having a clock signal generation circuit having a CR oscillator.
[0006]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a first oscillator, and a second oscillator including a resistor and a capacitor in an oscillation feedback loop, and includes a first oscillator until the oscillation is stabilized when the first oscillator starts to oscillate. Clock signal generating means for outputting the output signal of the first oscillator as the clock signal during a second period after the output signal of the second oscillator is transmitted as a clock signal during the period of the oscillation and stabilizing the oscillation; , Analog-to-digital conversion means including the resistor.
[0007]
Further, a switch is provided for switching the resistance to the second oscillator during the first period and for switching the resistance to the analog-to-digital converter during the second period.
[0008]
Further, the analog-to-digital conversion means includes voltage dividing means for generating a successive approximation voltage, and the resistor is included in the voltage dividing means.
[0009]
Further, the resistor is a resistor in which n (n is a natural number) resistors constituting the voltage dividing means are connected in series, and n is varied by a control signal.
[0010]
The analog-to-digital converter includes the capacitor for holding an analog signal, and switches the capacitor to the second oscillator during the first period, and switches the capacitor to the analog-to-digital converter during the second period. And a switch means for switching to.
[0011]
A first oscillator including a second oscillator including a resistance and a capacitance in an oscillation feedback loop, the first oscillator having a first period until the oscillation is stabilized at the start of oscillation of the first oscillator; Clock signal generating means for outputting the output signal of the first oscillator as the clock signal during a second period after the output signal of the second oscillator is transmitted as the clock signal and the oscillation is stabilized, and the resistor. Digital-to-analog conversion means.
[0012]
Further, a switch is provided for switching the resistance to the second oscillator during the first period and for switching the resistance to the digital-to-analog converter during the second period.
[0013]
Further, the digital-to-analog conversion means includes a ladder-type resistance circuit, and the resistance is included in the ladder-type resistance circuit.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention.
[0015]
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention is configured as a semiconductor integrated circuit 1. The semiconductor integrated circuit 1 includes a clock signal generation circuit 2, an analog / digital converter 3, a microprocessor 4, and a bus 5. The reset signal 101 and the stop signal 102 are supplied to the clock signal generation circuit 2. The reset signal 101 is output from an internal circuit (not shown) for activating the clock signal generation circuit 2 when power is turned on or when returning from the standby mode. The stop signal 102 is output from an internal circuit (not shown) in order to stop the clock signal generation circuit 2 when the power is turned off or when transition to the standby mode. The clock signal generation circuit 2 supplies a clock signal 109 to the microprocessor 4. The analog-to-digital converter 3 is connected to the microprocessor 4 via the bus 5.
[0016]
The clock signal generation circuit 2 includes an oscillator 6 having high accuracy but a long oscillation stabilization time, an oscillator 7 having a low accuracy but a short oscillation stabilization time, a selector 8, a flip-flop 9, a counter 10, and a flip-flop. 11, a flip-flop 12 and an OR gate 13. An oscillator 6 is externally attached to the oscillator 6 which is a crystal oscillator. The oscillator 6 starts oscillating by the output signal 103 of the flip-flop 9 when the flip-flop 9 is reset by the reset signal 101, and stops oscillation by the output signal 103 when the flip-flop 9 is set by the stop signal 102. The counter 10 counts the output signal 104 of the oscillator 6, outputs an overflow signal 107 when a predetermined count value is exceeded, and is reset by a reset signal 101. When the flip-flop 12 is reset by the reset signal 101, the output signal 105 of the flip-flop 12 becomes a logic H level and starts oscillating, and the flip-flop 12 performs a logical sum of the stop signal 102 and the overflow signal 107. When the output signal 105 is set by the output signal of the OR gate 13, the output signal 105 becomes logic L and stops oscillation. When the flip-flop 11 is reset by the reset signal 101, the selector 8 sends out the output signal 106 of the oscillator 7 as the clock signal 109 by the output signal 108 of the flip-flop 11, and when the flip-flop 11 is set by the overflow signal 107. The output signal 104 of the oscillator 6 is sent out as the clock signal 109 by the output signal 108.
[0017]
The oscillator 7 is a CR oscillator, and has a configuration in which an oscillation feedback loop of an odd-stage cascaded inverter row includes a delay circuit including a resistor R and a capacitor C. For example, a resistance R of about 40K ohm and a capacitance C of about 1.5PF are required. The resistor R2 and the capacitor C included in the analog-to-digital converter 3 are used as the resistor R and the capacitor C.
[0018]
Next, the configurations of the analog-to-digital converter 3 and the oscillator 7 will be further described with reference to FIG. FIG. 2 is a partial configuration diagram of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 2, the successive approximation type analog-to-digital converter 3 includes an analog signal input terminal 15, a sample-and-hold circuit 16, a comparator 21, a control circuit 22, a tap selector 23, and a voltage dividing circuit 24. And.
[0019]
The sample and hold circuit 16 includes a voltage buffer 17, a sampling switch 18, an N-channel MOS transistor 19, an N-channel MOS transistor 20, and a capacitor C. The voltage of the analog signal input terminal 15 is sampled by the sampling switch 18 via the voltage buffer 17 and the other of the capacitor C whose one end is connected to the low potential power supply VSS via the source / drain path of the N-channel MOS transistor 19. Given and held at the edge.
[0020]
The holding voltage of the capacitor C is input to the comparator 21 via the source / drain path of the N-channel MOS transistor 19, and is compared with the successive comparison voltage output from the tap selector 23. The control circuit 22 sets an internal successive approximation register based on the comparison result, and switches the tap selector 23 according to the control signal 110. The tap selector 23 selects a divided voltage from each tap of the voltage dividing circuit 24 and outputs it as a successive comparison voltage. When the successive approximation conversion is completed, the control circuit 22 outputs the digital data 111.
[0021]
The voltage dividing circuit 24 includes N resistors from a resistor R1 to a resistor RN (for example, N = 256 in the case of 8-bit conversion), an N-channel MOS transistor 25, an N-channel MOS transistor 26, and an N-channel MOS transistor. A MOS transistor 27 and an N-channel MOS transistor 28 are provided. One end of the resistor R1 is connected to the reference voltage source VREF, the other end of the resistor R1 is connected to one end of the resistor R2 via the source / drain path of the N-channel MOS transistor 25, and a divided voltage is applied from the other end of the resistor R1. Tap is pulled out. The other end of the resistor R2 is connected to one end of the resistor R3 via the source / drain path of the N-channel MOS transistor 26, and a divided voltage tap is pulled out from one end of the resistor R3. Hereinafter, similarly, the resistors R4 to RN are connected in series, a tap for the divided voltage is drawn out, and one end of the resistor RN is connected to the low potential power supply VSS.
[0022]
The oscillator 7 includes a NAND gate 30, an inverter 31, an inverter 32, a resistor R2 included in the voltage dividing circuit 24, and a capacitor C included in the sample and hold circuit 16. The NAND gate 30, the inverter 31, and the inverter 32 form an inverter train that is cascaded in three stages, and a delay circuit including a resistor R2 and a capacitor C is provided in an oscillation feedback loop of the inverter train. The output terminal of the NAND gate 30 is connected to the input terminal of the inverter 31, the output terminal of the inverter 31 is connected to the input terminal of the inverter 32, and the signal 106 is output from the output terminal of the inverter 31. The output terminal of the inverter 32 is connected to the connection point between the resistor R2 and the source / drain path of the N-channel MOS transistor 26 via the source / drain path of the N-channel MOS transistor 28. A first input terminal of the NAND gate 30 is connected to a connection point between the resistor R2 and the source / drain path of the N-channel MOS transistor 25 via the source-drain path of the N-channel MOS transistor 27. Further, the first input terminal of the NAND gate 30 is connected to the other end of the capacitor C whose one end is connected to the lower potential power supply VSS via the source / drain path of the N-channel MOS transistor 20. An output signal 105 is provided to a second input terminal of the NAND gate 30.
[0023]
The N-channel MOS transistor 25 and the N-channel MOS transistor 26 are switch means for separating the resistor R2 from the voltage dividing circuit 24, that is, the analog-to-digital conversion circuit 3, and include an N-channel MOS transistor 27 and an N-channel MOS transistor. The transistor 28 is a switch for connecting the resistor R2 to the oscillator 7 side. Output signal 105 of flip-flop 12 is inverted by inverter 29 to become signal 112. Signal 112 is applied to the gates of N-channel MOS transistor 25 and N-channel MOS transistor 26. Output signal 105 is applied to the gates of N-channel MOS transistor 27 and N-channel MOS transistor 28. When the output signal 105 is at the logic H level, the signal 112 goes to the logic L level, the N-channel MOS transistor 25 and the N-channel MOS transistor 26 are turned off, and the N-channel MOS transistor 27 and the N-channel MOS transistor 28 are turned on. When the output signal 105 is at the logic L level, the signal 112 goes to the logic H level, the N-channel MOS transistor 25 and the N-channel MOS transistor 26 are turned on, and the N-channel MOS transistor 27 and the N-channel MOS transistor 28 are turned off. Therefore, the N-channel MOS transistor 25, the N-channel MOS transistor 26, the N-channel MOS transistor 27, and the N-channel MOS transistor 28 switch the resistance R2 to the oscillator 7 when the output signal 105 is at the logic H level, and When the signal 105 is at the logical L level, it functions as a switch for switching the resistor R2 to the analog-to-digital conversion circuit 3 side.
[0024]
The N-channel MOS transistor 19 is a switch for separating the capacitor C from the sample-hold circuit 16 side, that is, the analog-to-digital conversion circuit 3 side. The N-channel MOS transistor 20 connects the capacitor C to the oscillator 7 side. Switch means. Signal 112 is applied to the gate of N-channel MOS transistor 19. Output signal 105 is applied to the gate of N-channel MOS transistor 20. When the output signal 105 is at the logic H level, the signal 112 goes to the logic L level, and the N-channel MOS transistor 19 turns off and the N-channel MOS transistor 20 turns on. When the output signal 105 is at the logic L level, the signal 112 is at the logic H level, and the N-channel MOS transistor 19 is turned on and the N-channel MOS transistor 20 is turned off. Therefore, the N-channel MOS transistor 19 and the N-channel MOS transistor 20 switch the capacitance C to the oscillator 7 when the output signal 105 is at the logic H level, and convert the capacitance C to analog-to-digital when the output signal 105 is at the logic L level. It functions as switch means for switching to the circuit 3 side.
[0025]
Next, the operation will be described with reference to FIG. FIG. 3 is an operation explanatory diagram of the semiconductor device according to the first embodiment of the present invention. FIG. 3 shows the start-up operation of the clock signal generation circuit 2 when the power is turned on, but the same applies when returning from the standby mode. First, when the power is turned on, a reset signal 101 is output in synchronization with the rise of the power supply voltage. At time t1, the output signal 105 becomes a logic H level, and the oscillator 6 starts oscillating gradually. Is switched to the oscillator 7 side and the oscillator 7 immediately starts oscillating, so that the output signal 106 is sent out as the clock signal 109. Even if the resistor R2 and the capacitor C are switched to the oscillator 7, the analog-to-digital conversion circuit 3 does not operate when the clock signal generation circuit 2 is started, so that no inconvenience occurs. Next, after the oscillation stabilization time (for example, about 30 ms) in which the oscillation of the oscillator 6 is stabilized from the time t1 at the start of the oscillation and reaching the time t2, the overflow signal 107 is output, the output signal 105 becomes the logical L level, and the resistance R2 And the capacitance C is switched to the analog-to-digital conversion circuit 3 side, the output signal 104 is sent out as the clock signal 109, and the oscillator 7 stops oscillating. During the period after time t2, the resistance R2 and the capacitance C are switched to the analog-to-digital conversion circuit 3, so that the analog-to-digital conversion circuit 3 is in an operable state. Thus, the resistor R2 and the capacitor C are switched to the oscillator 7 only during the period from the time t1 to the time t2 when the output signal 105 is at the logical H level, and the oscillator 7 oscillates. Although not shown, when the stop signal 102 is input at any time, the oscillators 6 and 7 stop oscillating, and the resistance R2 and the capacitance C are switched to the analog-digital conversion circuit 3 side.
[0026]
As described above, according to the semiconductor device of the first embodiment of the present invention, the time between the oscillator 7 of the clock signal generation circuit 2 provided in the one-chip semiconductor integrated circuit 1 and the analog-to-digital conversion circuit 3 is increased. Since the resistor R2 and the capacitor C are shared by the division switching, it is not necessary to provide a dedicated delay resistor and capacitor only for the oscillator 7, and the clock signal generating circuit 2 having the oscillator 7 which is a CR oscillator is used. Although it is provided, an increase in the layout area, that is, the chip size can be suppressed.
[0027]
In this embodiment, the sampling capacitor of the analog-to-digital converter 3 is used as the capacitor C. However, although the effect of reducing the chip size is slightly reduced, the oscillator 7 can be changed to have a dedicated capacitor. The parasitic capacitance of the wiring pattern of the feedback loop 7 may be used.
[0028]
Next, a configuration of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a partial configuration diagram of a semiconductor device according to a second embodiment of the present invention.
[0029]
The difference between the configuration of the semiconductor device of the second embodiment of the present invention shown in FIG. 4 and the configuration of the semiconductor device of the first embodiment of the present invention shown in FIG. In the semiconductor device according to the first embodiment, only the resistor R2 is used as a delay resistor, whereas in the semiconductor device according to the second embodiment of the present invention shown in FIG. 4, four resistors R2 connected in series are used. The voltage dividing circuit 24 shown in FIG. 2 is changed to a voltage dividing circuit 33 shown in FIG. 4 so that an arbitrary number of stages can be selected from the resistors R3, R4, and R5 so that the delay resistance value can be step-variable. Accordingly, only the oscillator 7 shown in FIG. 2 is changed to the oscillator 7a shown in FIG. 4, and the other components are the same. Therefore, the same components as those shown in FIG. 4 and FIG. Are denoted by the same reference numerals and description thereof is omitted.
[0030]
As shown in FIG. 4, the voltage dividing circuit 33 includes N resistors from a resistor R1 to a resistor RN (for example, N = 256 in the case of 8-bit conversion), an N-channel type MOS transistor 34, and an N-channel type. A MOS transistor 35, an N-channel MOS transistor 36, an N-channel MOS transistor 37, an N-channel MOS transistor 38, an N-channel MOS transistor 39, an N-channel MOS transistor 40, and a selector 41 Prepare. The selector 41 is constituted by a transfer gate, and conduction between one of the four input terminals and the output terminal is made by the selection signal 113. One end of the resistor R1 is connected to the reference voltage source VREF, the other end of the resistor R1 is connected to one end of the resistor R2 via the source / drain path of the N-channel MOS transistor 34, and a divided voltage is applied from the other end of the resistor R1. Tap is pulled out. One end of the resistor R2 is input to the selector 41 via the source / drain path of the N-channel MOS transistor 36. The other end of the resistor R2 is connected to one end of the resistor R3, and a tap for a divided voltage is drawn from one end of the resistor R3. One end of the resistor R3 is input to the selector 41 via the source / drain path of the N-channel MOS transistor 37. The other end of the resistor R3 is connected to one end of the resistor R4, and a tap for a divided voltage is drawn from one end of the resistor R4. One end of the resistor R4 is input to the selector 41 via the source / drain path of the N-channel MOS transistor 38. The other end of the resistor R4 is connected to one end of the resistor R5, and a tap for a divided voltage is drawn from one end of the resistor R5. One end of the resistor R5 is input to the selector 41 via the source / drain path of the N-channel MOS transistor 39. The other end of the resistor R5 is connected to one end of the resistor R6 via the source / drain path of the N-channel MOS transistor 35, and a tap for a divided voltage is drawn from one end of the resistor R6. Hereinafter, similarly, the resistors R7 to RN are connected in series, the tap for the divided voltage is drawn out, and one end of the resistor RN is connected to the low-potential-side power supply VSS. The other end of the resistor R5 is connected to the output terminal of the inverter 32 via the source / drain path of the N-channel MOS transistor 40. The output terminal of the selector 41 is connected to the first input terminal of the NAND gate 30.
[0031]
The N-channel MOS transistor 34 and the N-channel MOS transistor 35 are switch means for separating the resistors R2, R3, R4, and R5 from the voltage dividing circuit 33 side. The MOS transistor 37, the N-channel MOS transistor 38, the N-channel MOS transistor 39 and the N-channel MOS transistor 40 are switching means for connecting the resistors R2, R3, R4 and R5 to the oscillator 7a side. is there. Signal 112 is applied to the gates of N-channel MOS transistor 34 and N-channel MOS transistor 35. Output signal 105 is applied to the gates of N-channel MOS transistor 36, N-channel MOS transistor 37, N-channel MOS transistor 38, N-channel MOS transistor 39 and N-channel MOS transistor 40. From the N-channel MOS transistor 34 to the N-channel MOS transistor 40, when the output signal 105 is at the logical H level, the resistors R2, R3, R4, and R5 are switched to the oscillator 7a side, and the output signal 105 is at the logical L level. In this case, it functions as a switch for switching the resistors R2, R3, R4, and R5 to the voltage dividing circuit 33 side. When the output signal 105 is at the logical H level, the switches 23a, 23b and 23c of the tap selector 23 are also turned off.
[0032]
As described above, according to the semiconductor device of the second embodiment of the present invention, n (n is a natural number, where n is a natural number) out of N resistors R1 to RN constituting the voltage dividing circuit 33. Then, 4.) The resistors R2, R3, R4, and R5 as resistors connected in series are used for delaying the oscillator 7a, and the selector 41 can change the delay resistance value by n steps. The oscillation frequency of the oscillator 7a can be adjusted.
[0033]
Next, a configuration of a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a semiconductor device according to the third embodiment of the present invention.
[0034]
The difference between the configuration of the semiconductor device of the third embodiment of the present invention shown in FIG. 5 and the configuration of the semiconductor device of the first embodiment of the present invention shown in FIG. The converter 3 is changed to the digital-to-analog converter 3a shown in FIG. 5 so that the resistor 2R0 included in the digital-to-analog converter 3a is shared with the oscillator 7b, and accordingly, the semiconductor integrated circuit 1 and the clock signal generation circuit 2 shown in FIG. 1 is only a portion including the semiconductor integrated circuit 1a and the clock signal generation circuit 2a shown in FIG. 5, and the other components are the same. Therefore, the same components as those in the configuration shown in FIG. 5 and the configuration shown in FIG. The description is omitted by attaching the reference numerals.
[0035]
Next, the configurations of the digital-to-analog converter 3a and the oscillator 7b will be further described with reference to FIG. FIG. 6 is a partial configuration diagram of a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 6, the constant voltage digital-to-analog converter 3a includes a ladder-type resistor circuit 42, a switch block 43, and an analog signal output terminal 15a. The ladder-type resistor circuit 42 includes N-1 resistors ranging from a resistor R1 having a resistance value of R to a resistor R (N-1) (for example, N = 8 in the case of 8-bit conversion), and each resistance value. N + 2 resistors from the resistors 2R0 to 2R (N + 1), which are 2R, an N-channel MOS transistor 44, an N-channel MOS transistor 45, an N-channel MOS transistor 46, and an N-channel MOS transistor 47. And. Based on the digital data signal 114, the reference voltage source VREF or the low-potential-side power supply VSS is supplied to one end of each of the resistors 2R1 to 2RN by a switch from the MSB to the LSB in the switch block 43. Output from the output terminal 15a. One end of the resistor 2R0 is connected to one end of the resistor R1 via the source / drain path of the N-channel MOS transistor 44. The other end of the resistor 2R0 is connected to the lower potential power supply VSS via the source / drain path of the N-channel MOS transistor 45.
[0036]
The oscillator 7b includes a NAND gate 30, an inverter 31, an inverter 32, a resistor 2R0 included in a ladder resistor circuit 42, and a capacitor C. The NAND gate 30, the inverter 31, and the inverter 32 form an inverter train that is cascaded in three stages, and a delay circuit including a resistor 2R0 and a capacitor C is provided in an oscillation feedback loop of the inverter train. The output terminal of the NAND gate 30 is connected to the input terminal of the inverter 31, the output terminal of the inverter 31 is connected to the input terminal of the inverter 32, and the signal 106 is output from the output terminal of the inverter 31. The output terminal of the inverter 32 is connected to the connection point between the resistor 2R0 and the source / drain path of the N-channel MOS transistor 44 via the source-drain path of the N-channel MOS transistor 46. A first input terminal of the NAND gate 30 is connected to a connection point between the resistor 2R0 and the source / drain path of the N-channel MOS transistor 45 via the source-drain path of the N-channel MOS transistor 47. Further, a first input terminal of the NAND gate 30 is connected to the other end of the capacitor C whose one end is connected to the lower potential power supply VSS. An output signal 105 is provided to a second input terminal of the NAND gate 30.
[0037]
The N-channel MOS transistor 44 and the N-channel MOS transistor 45 are switch means for disconnecting the resistor 2R0 from the ladder resistor circuit 42, and the N-channel MOS transistor 46 and the N-channel MOS transistor 47 are connected to the resistor 2R0. Is a switch means for connecting to the oscillator 7b side. Output signal 105 of flip-flop 12 is inverted by inverter 29 to become signal 112. Signal 112 is applied to the gates of N-channel MOS transistor 44 and N-channel MOS transistor 45. Output signal 105 is applied to the gates of N-channel MOS transistor 46 and N-channel MOS transistor 47. The N-channel MOS transistor 44, the N-channel MOS transistor 45, the N-channel MOS transistor 46, and the N-channel MOS transistor 47 switch the resistance 2R0 to the oscillator 7b side when the output signal 105 is at the logic H level, and Functions as switch means for switching the resistor 2R0 to the digital-to-analog converter 3a side when is at the logical L level.
[0038]
As described above, according to the semiconductor device of the third embodiment of the present invention, the time between the oscillator 7b of the clock signal generation circuit 2a and the digital-to-analog converter 3a provided in the one-chip semiconductor integrated circuit 1a. Since the resistor 2R0 is shared by the division switching, it is not necessary to provide a dedicated delay resistor only for the oscillator 7b, and the layout area is provided while the clock signal generating circuit 2a having the oscillator 7b as the CR oscillator is provided. That is, an increase in chip size can be suppressed.
[0039]
【The invention's effect】
An advantage of the present invention is that a semiconductor device which can suppress an increase in chip size while having a clock signal generation circuit having a CR oscillator can be realized.
[0040]
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a partial configuration diagram of the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is an operation explanatory diagram of the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a partial configuration diagram of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a block diagram of a semiconductor device according to a third embodiment of the present invention.
FIG. 6 is a partial configuration diagram of a semiconductor device according to a third embodiment of the present invention.
FIG. 7 is a configuration diagram of a conventional clock signal generation circuit.
[Explanation of symbols]
1 Semiconductor integrated circuit
1a Semiconductor integrated circuit
2 Clock signal generation circuit
2a Clock signal generation circuit
3 Analog-digital converter
3a Digital-to-analog converter
4 Microprocessor
5 bus
6 oscillator
7 Oscillator
7a Oscillator
7b oscillator
8 Selector
9 flip-flops
10 counter
11 flip-flops
12 flip-flops
13 OR gate
14 Crystal oscillator
15 Analog signal input terminal
15a Analog signal output terminal
16 Sample hold circuit
17 Voltage buffer
18 Sampling switch
19 N-channel MOS transistor
20 N-channel MOS transistor
21 Comparator
22 Control circuit
23 tap selector
23a switch
23b switch
23c switch
24 voltage divider circuit
25 N-channel MOS transistor
26 N-channel MOS transistor
27 N-channel MOS transistor
28 N-channel MOS transistor
29 Inverter
30 NAND gate
31 Inverter
32 inverter
33 voltage divider
34 N-channel MOS transistor
35 N-channel MOS transistor
36 N-channel MOS transistor
37 N-channel MOS transistor
38 N-channel MOS transistor
39 N-channel MOS transistor
40 N-channel MOS transistor
41 Selector
42 Ladder type resistance circuit
43 Switch block
44 N-channel MOS transistor
45 N-channel MOS transistor
46 N-channel MOS transistor
47 N-channel MOS transistor
206 oscillator
207 oscillator
208 Selector
209 flip-flop
210 counter
211 flip-flop
212 flip-flop
213 OR gate

Claims (8)

A first oscillator and a second oscillator including a resistance and a capacitance in an oscillation feedback loop, wherein the second oscillator is provided for a first period until the oscillation is stabilized at the start of oscillation of the first oscillator. Clock signal generating means for outputting the output signal of the first oscillator as the clock signal during a second period after the output signal of the oscillator is transmitted as the clock signal and the oscillation is stabilized, and an analog digital signal including the resistor. And a conversion means. 2. The semiconductor device according to claim 1, further comprising switch means for switching said resistance to said second oscillator during said first period and switching said resistance to said analog-to-digital conversion means during said second period. . 3. The semiconductor device according to claim 1, wherein the analog-to-digital converter includes a voltage divider for generating a successive approximation voltage, and the resistor is included in the voltage divider. 4. The semiconductor device according to claim 3, wherein said resistor is a resistor in which n (n is a natural number) resistors constituting said voltage dividing means are connected in series, and said n is varied by a control signal. The analog-to-digital converter includes the capacitor for holding an analog signal, and switches the capacitor to the second oscillator during the first period and switches the capacitor to the analog-digital converter during the second period. 5. The semiconductor device according to claim 2, further comprising switch means. A first oscillator and a second oscillator including a resistance and a capacitance in an oscillation feedback loop, wherein the second oscillator is provided for a first period until the oscillation is stabilized at the start of oscillation of the first oscillator. Clock signal generating means for outputting the output signal of the first oscillator as the clock signal during a second period after the output signal of the oscillator is transmitted as the clock signal and the oscillation is stabilized; And a conversion means. 7. The semiconductor device according to claim 6, further comprising: switch means for switching the resistance to the second oscillator during the first period and switching the resistance to the digital-to-analog conversion means during the second period. . 8. The semiconductor device according to claim 6, wherein said digital-to-analog conversion means includes a ladder-type resistance circuit, and said resistance is included in said ladder-type resistance circuit.

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