JP2004193422A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a contact via in which a contact resistance does not increase even by making it microscopic, and its manufacturing method. <P>SOLUTION: The semiconductor device has a first conductive layer and a wiring connection part in which a metal material constituting the first conductive layer is diffused in an insulator to indicate the conductivity, and the semiconductor device is constituted so that the first conductive layer is electrically connected to the insulator. The manufacturing method comprises the step in which the diffusion is caused by a function of heat or an electric field. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a contact via for electrically connecting metal wirings and a method for forming the same.
[0002]
[Prior art]
The multi-layer wiring structure of a semiconductor device includes a plurality of metal wiring layers covered with an insulating film, a contact hole is formed in order to conduct between the wirings, and a sidewall is surrounded by a barrier film for preventing metal diffusion. And a contact via made of metal.
[0003]
2. Description of the Related Art In recent years, a damascene method is frequently used in a process of forming a multilayer wiring layer of a semiconductor device. In this method, in order to electrically join two metal wirings sandwiching the insulating film, a lower wiring is formed, and then a contact hole forming layer and an insulating film for insulating the upper wiring are deposited, followed by a patterning step and etching. By repeating the process, a contact hole and an upper wiring groove are formed, a metal is buried in the contact hole and the upper wiring groove by a plating method, and chemical mechanical polishing (CMP method) is performed until the metal is left in the wiring groove. In this method, an upper wiring and a contact via are formed. Further, as one of methods for forming a wiring structure, there is a method utilizing a phenomenon in which a metal wiring material causes disconnection of a wiring due to stress migration or electromigration. (For example, Patent Document 1)
[0004]
[Patent Document 1] JP-A-5-7506 (pages 3-7, FIG. 1)
[0005]
[Problems to be solved by the invention]
In the damascene method, it is difficult to etch copper represented by a low-resistance wiring material. Therefore, in order to form a contact via connecting a lower wiring and an upper wiring by a plating method, a contact hole in which an insulating film is patterned is formed. It is required to fill a plating solution and deposit copper so as to be in close contact with the lower wiring. However, when the hole diameter of the contact hole is reduced, the surface tension of the plating solution hinders the penetration of the plating solution, and it becomes difficult to uniformly deposit copper.
[0006]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a contact via formed without applying a plating solution to a contact hole to be miniaturized and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
FIG. 1 is a diagram illustrating the principle of the present invention. The figure schematically shows a part of a cross-sectional view in a semiconductor device manufacturing process. More specifically, a silicon oxide film 8 is formed on a silicon substrate 1, and a copper buried wiring layer 17 is formed in a groove via a tantalum nitride film 14 via a silicon nitride film 9. Further, a high-density insulating film 18 made of any one of SiN, SiC, and SiC: H is sandwiched between the silicon film nitride 13 and the silicon nitride 19, and furthermore, SiO2, SiOC, SiOF, SiON, SiCON, SiCN, and organic. A wiring connection portion 27 made of any one of the system insulating materials is formed so as to be in contact with the copper embedded wiring layers 17 and 25. The copper embedded wiring layers 25 and 26 are also formed inside the groove with the tantalum nitride film 22 therebetween. The buried wiring layers 17, 25, 26 are flattened by chemical mechanical polishing, and the side surfaces are insulated by the low dielectric constant insulating films 12, 20.
[0008]
When the substrate is heated at about 400 ° C. for several minutes in this state, stress migration occurs in the copper embedded wiring, and copper is diffused into the wiring connection portion 27, so that the upper and lower wirings are electrically connected. This phenomenon can be reproduced with good reproducibility when the wiring width is 1 μm or less, because the wiring is easily affected by a change in stress. Alternatively, when a voltage of several hundred mV is applied to the front and back surfaces of the substrate for several minutes before the upper layer wiring is subjected to chemical mechanical polishing, electromigration occurs, and copper diffuses into the wiring connection portion 27 made of a low-density insulator. , The upper and lower wirings are electrically connected.
[0009]
Since the wiring connection portion is made of one of SiO2, SiOC, SiOF, SiON, SiCON, SiCN, and an organic insulating material, it is possible to provide a wiring connection portion suitable for diffusing the metal material forming the conductive layer. When the organic insulating material is a polysiloxane-based porous silica, the wiring metal can be easily diffused into the porous structure. Further, when the metal material is any one of Al, Al alloy, Cu, Cu alloy, W, W alloy, Fe, and Fe alloy, the wiring material can be selectively diffused into the diffusion plug. Since the diffusion direction of the wiring material is perpendicular to the main surface, metal atoms diffuse in the same direction as the crystal direction when the metal material of the conductive layer is formed, and the wiring connection portion and the wiring layer Adhesion is improved.
[0010]
Since the insulating film formed around the wiring connection portion is any one of SiN, SiC, and SiC: H, the wiring connection portion in which the metal material is diffused is insulated, and the wiring is suitable for preventing the diffusion of the wiring material. Can provide structure. Furthermore, since the wiring connection part has similar chemical or mechanical properties to general interlayer insulating film materials, it does not react with each other and forms devices while maintaining the flatness of the substrate without causing local stress. it can. Further, since a contact via can be formed without using a barrier metal, the contact area of the contact via diameter can be increased, and the contact resistance can be reduced. As a result, when the contact vias are miniaturized, the insulation resistance between the contact vias increases, and a semiconductor device with reduced wiring delay can be provided.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
[Example 1]
Hereinafter, the present invention will be described with reference to FIGS. 2 to 9 which are cross-sectional views in the course of a semiconductor device manufacturing process according to an embodiment of the present invention.
Referring to FIG. 2A, first, after forming an element isolation oxide film 2 on a p-type silicon substrate 1 by using a selective oxidation method, a gate structure including a gate insulating film 3, a gate electrode 4, and a protective film 6 is formed. After the silicon nitride film is formed so as to cover the entire surface of the gate electrode laminated structure, As ions are implanted by dry etching using the sidewalls 5 remaining after the etch-back process as a mask. Forming the source / drain regions 7 to form the structure shown in FIG.
Next, as shown in FIG. 2B, a silicon oxide film 8 (thickness: 1 μm) as an interlayer insulating film is formed on the entire surface by a CVD method, and a silicon nitride film 9 (which becomes a polishing stopper in a subsequent CMP (chemical mechanical polishing) process by a sputtering method). (Thickness: 100 nm) are sequentially deposited to form the structure of FIG.
Referring to FIG. 3C, the silicon nitride film 9 is patterned by using a resist (not shown) formed by photolithography as an etching mask to form a via hole reaching the n-type source / drain region 7. The silicon oxide film 8 is subjected to reactive ion etching with a mixed gas plasma such as CF4 and CHF3 using the silicon nitride film 9 opened by removing the silicon nitride film 9 as an etching mask, to obtain a structure shown in FIG.
Then, as shown in FIG. 3D, in order to form a diffusion prevention film (tantalum nitride film) 10 and a tungsten via 11, a tungsten film (thickness: 50 nm) and tungsten (hereinafter, referred to as W (Not shown), and then polished by a CMP method until the silicon nitride film 9 is exposed, and the structure shown in FIG. 3D is obtained.
Referring to FIG. 4E, in order to form a low dielectric constant insulating film 12 as an interlayer insulating film, for example, an organic SOG film is spin-coated (450 nm thick) and then baked, and then a silicon nitride film 13 (100 nm thick) Is deposited as shown in FIG.
Next, referring to FIG. 4F, the silicon nitride film 13 is patterned by performing reactive ion etching with a mixed gas plasma of CF4 and CHF3 using a resist (not shown) formed by photolithography as an etching mask. Then, by using the silicon nitride film 13 opened by removing the resist as a mask, reactive ion etching is performed by using a mixed gas plasma of Ar and O2 to which a carbon source such as C4F8 is added as necessary. The dielectric insulating film 12 is etched to form a wiring layer groove that reaches the tungsten via 11, as shown in FIG.
Next, as shown in FIG. 5G, a tantalum nitride film 14 and a copper seed layer 15 are sequentially deposited on the entire surface as a diffusion prevention film and plating deposition nuclei (thicknesses 50 nm and 50 nm, respectively) by sputtering. Next, a copper plating layer 16 (thickness: 600 nm) is formed by plating and the trench for forming the wiring layer is buried to obtain a structure shown in FIG.
[0012]
Next, the copper plating layer 16, the copper seed layer 15, and the tantalum nitride film 14 are polished by CMP until the silicon nitride film 13 is exposed.
Referring to FIG. 5H, a copper buried wiring layer 17 in which the copper plating layer 16 and the copper seed layer 15 are integrated is formed, as shown in FIG.
Next, as shown in FIG. 6I, a porous silica film 29, which is an SOG material, is applied (thickness: 400 nm) as a material of the wiring connection portion and then fired (360 to 380 ° C.) to obtain FIG.
Referring to FIG. 6 (j), a resist (not shown) formed by photolithography is used as an etching mask to perform reactive ion etching with a mixed gas plasma such as CF4 and CHF3 to connect the wiring on the copper embedded wiring layer 17. The portion 27 is patterned, as shown in FIG.
7 (k), a plasma CVD silicon nitride film 30 (600 nm thick) is formed on the entire surface by a plasma CVD method (film formation temperature: 360 to 380 ° C.).
Referring to FIG. 7 (l), the plasma CVD silicon nitride film 30 is flattened by an etch-back method or the like until the surface of the wiring connection portion 27 is exposed.
Next, as shown in FIG. 8M, porous silica is spin-coated (400 nm thick) as the low dielectric constant insulating film 20 and then fired (360 to 380 ° C.) to obtain the structure shown in FIG.
Next, referring to FIG. 8 (n), using a resist (not shown) formed by photolithography as an etching mask, reactive ion etching is performed with a mixed gas plasma of CF4 and CHF3 to form wiring layer grooves. The structure shown in FIG.
Referring to FIG. 9 (o), a tantalum nitride film 22 and a copper seed layer 23 are sequentially deposited (50 nm and 50 nm, respectively) on the entire surface by sputtering. Using the copper seed layer 23 as a growth nucleus, a copper plating layer 24 (600 nm in thickness) is formed and the trench for forming the wiring layer is buried to obtain the structure shown in FIG.
[0013]
Next, the copper plating layer 24, the copper seed layer 23, and the tantalum nitride film 22 are polished by a CMP method until the silicon nitride film 21 is exposed.
As shown in FIG. 9 (p), the copper buried wiring layers 25 and 26 in which the copper plating layer and the copper seed layer are integrated are formed, and the structure shown in FIG. 9 (p) is obtained.
[0014]
Then, the substrate is heated at 400 ° C. for 5 minutes to cause stress migration in the wiring structure, to diffuse copper atoms from the copper buried wiring layer 17 to the wiring connection part 27, and to form the copper buried wiring layer 17 and the copper buried wiring layer 25. Are electrically connected.
[0015]
As described above, the steps of forming the insulating film including the wiring connection portion, forming the wiring layer groove, forming the copper buried wiring layer, and diffusing copper to the wiring connection portion by the required number of times are repeated. A wiring structure is formed.
[0016]
Note that electromigration can be used as a method for diffusing copper atoms from the copper wiring layer 17 into the wiring connection portion 27.
[0017]
In order to diffuse copper atoms from the copper wiring layer into the wiring connection portion 27 in the same process as in the embodiment, for example, a bias voltage of several hundred mV is applied from both sides of the substrate for 3 minutes in the structure of FIG. Causes electromigration. As a result, the copper atoms diffuse into the wiring connection portion 27, and the copper buried wiring layer 17 and the copper plating layer 24 are electrically joined.
[0018]
In the above embodiment, in addition to the plasma CVD silicon nitride film 30 around the wiring connection portion 27, a material having a high density from SiC or SiC: H is used to form a wiring metal diffusion preventing film in any case. Contact vias can be formed without the need. At this time, since the contact area between the contact via and the wiring increases, the contact resistance can be reduced by 12% or more. Note that as a method for forming these materials, a low-temperature plasma CVD method that can be formed in a temperature range (for example, 360 ° C. to 380 ° C.) where the wiring material does not cause stress migration can be used.
[0019]
Examples of the wiring connection portion 27 (insulator having a low density) include SiO2, SiOC, SiOF, SiON, SiCON, and SiCN that can be formed by a plasma CVD method, and an organic insulating film that can be formed by a coating method. However, the invention of the present application is not limited to the above-mentioned materials, and by using two or more kinds of insulating films having a difference in the diffusibility of the wiring metal, the insulating material having a high diffusivity, that is, a low-density insulator (wiring connecting portion) can be formed. Wiring metal can be selectively diffused to form contact vias.
[0020]
This eliminates the need for cleaning, which was conventionally required to adhere the diffusion prevention film to the inside of the wiring via, and prevents the cleaning solution from eroding the inner wall of the contact hole.
[0021]
Since the lower wiring surface of the contact via portion is not subjected to the contact hole etching and the associated cleaning process, the surface is not oxidized and the wiring resistance does not increase.
[0022]
In addition, by arranging a low-density insulator that is not intended for bonding between wirings to a required part of a metal wiring, abnormal temperature rise caused by wiring deterioration (high resistance) and excessive current generation due to wiring short-circuiting can be prevented. On the other hand, a semiconductor device capable of avoiding temporary stress migration can be provided because metal is diffused into the insulator having a low density.
[0023]
Other than copper, copper alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, iron, and iron alloy can be used as the wiring material. Stress migration occurs at a temperature higher than the formation temperature of the material selected for the wiring connection, or an electric field is applied. A wiring material that causes electromigration due to is selected.
[Example 2]
Hereinafter, the present invention will be described with reference to FIGS. 10 to 13 which are cross-sectional views in the middle of a manufacturing process of a semiconductor device according to another embodiment of the present invention.
Steps up to FIG. 10A are obtained after sequentially performing the steps of FIG. 2A to FIG. 5H in the first embodiment, and thus description thereof is omitted.
As shown in FIG. 10A, a porous silica (not shown), which is an SOG material, is applied (film thickness: 400 nm) as a material of the reference wiring connection portion, and is baked (360 to 380 ° C.), and is formed by photolithography (not shown). By performing reactive ion etching with a mixed gas plasma such as CF4 and CHF3 using) as an etching mask, the wiring connection portion 27 is patterned on the copper buried wiring layer 17, and the result is shown in FIG.
Referring to FIG. 10B, a tantalum nitride film 28 (thickness: 50 nm) serving as a diffusion prevention film is formed using a sputtering method so as to cover the wiring connection portion 27.
Next, as shown in FIG. 11C, a porous silica film 29, which is a SOG material having a low dielectric constant, is spin-coated (600 nm in thickness) and baked (360-380 ° C.) on the entire surface.
Referring to FIG. 11D, flattening is performed by an etch-back method or the like until the surface of the wiring connection portion 27 is exposed, and FIG. 11D is obtained.
Next, as shown in FIG. 12E, porous silica is spin-coated (400 nm) as the low-dielectric-constant insulating film 20 and then baked (360 to 380 ° C.), and then a silicon nitride film 21 is formed by sputtering (100 nm). 12 (e).
Referring to FIG. 12F, the silicon nitride film 21 is patterned by performing reactive ion etching with a mixed gas plasma such as CF4 and CHF3 using a resist (not shown) formed by photolithography as an etching mask. The resist mask is removed, and the silicon nitride film 21 is used as a mask to perform reactive ion etching using a mixed gas plasma of Ar and O2 to which a carbon source such as C4F8 is added as necessary, thereby achieving low dielectric constant insulation. The film 20 is etched to form the structure of FIG. 12F in which the wiring layer groove is formed.
Referring to FIG. 13 (g), a tantalum nitride film 22 and a copper seed layer 23 are sequentially deposited (50 nm and 50 nm, respectively) on the entire surface by sputtering, and then a copper plating layer is formed so as to fill the grooves by plating. 24 (600 nm) is formed, and the structure shown in FIG.
Next, the copper plating layer 24, the copper seed layer 23, and the tantalum nitride film 22 are polished by the CMP method.
As shown in FIG. 13H, the silicon nitride film 21 is polished by CMP until the silicon nitride film 21 is exposed to form copper embedded wiring layers 25 and 26, and the structure shown in FIG. 13H is obtained.
[0024]
Then, the substrate is heated at 400 ° C. for 5 minutes to cause stress migration in the wiring structure, copper atoms diffuse from the copper buried wiring layer 17 to the wiring connection part 27, and the copper buried wiring layer 17 and the copper buried wiring layer 25 Are electrically connected.
[0025]
In the above-described embodiment, the tantalum nitride film 28 is formed so as to cover the side wall of the connection portion 27. With this, a low dielectric such as a porous silica film is used as the low-density insulator 29 around the wiring connection portion 27. Since it can be used, the delay time of the wiring can be reduced. Further, even if the action of heat or an electric field for diffusing the wiring material varies, the tantalum nitride film 28 serves as a diffusion stopper, so that no extra diffusion occurs.
[0026]
Hereinafter, various aspects of the present invention are collectively described as supplementary notes.
[0027]
(Supplementary Note 1) A first conductive layer,
A metal material constituting the first conductive layer diffuses into the insulator and has a conductive wiring connection portion,
A semiconductor device configured to electrically conduct between the first conductive layer and the insulator. (1)
(Supplementary Note 2) The semiconductor device according to supplementary note 1, wherein the wiring connection portion is configured to be in contact with a second conductive layer.
[0028]
(Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein an insulator forming the wiring connection part has a lower density than an insulating film disposed around the wiring connection part.
(Supplementary Note 4) The wiring connection part is a silicon oxide film (SiO2), a silicon carbide oxide film (SiOC), a silicon fluoride oxide film (SiOF), a silicon nitride oxide film (SiON), a silicon carbonitride oxide film (SiCON), 4. The semiconductor device according to any one of supplementary notes 1 to 3, wherein the semiconductor device is made of any one of a silicon carbide nitride film (SiCN) and an organic insulating material. (2)
(Supplementary note 5) The semiconductor device according to supplementary note 4, wherein the organic insulating material is polysiloxane-based porous silica.
(Supplementary Note 6) The insulator formed around the wiring connection portion is made of any one of a silicon nitride film (SiN), silicon carbide (SiC), and silicon hydride (SiC: H). 4. The semiconductor device according to any one of supplementary notes 1 to 3. (3)
(Supplementary Note 7) The semiconductor device according to Supplementary Note 1 or 2, wherein the metal material is any one of Al, an Al alloy, Cu, a Cu alloy, W, a W alloy, Fe, and an Fe alloy.
[0029]
(Supplementary Note 8) The semiconductor device according to Supplementary Note 1 or 2, wherein the conductive layers have a wiring structure extending in parallel with each other, and have a line width of 1 μm or less.
[0030]
(Supplementary note 9) The semiconductor device according to any one of Supplementary notes 1 to 5, wherein the wiring junction has a diffusion prevention film on a side wall.
[0031]
(Supplementary Note 10) a step of forming a first conductive layer;
Forming an insulator;
A step of applying heat or an electric field, such that the metal material constituting the first conductive layer is diffused into the insulator, and the insulator forms a wiring connection portion.
A method for manufacturing a semiconductor device configured to electrically conduct between the first conductive layer and the insulator. (4)
(Supplementary Note 11) a step of forming the wiring connection portion so as to be in contact with a second conductive layer;
A step of applying heat or an electric field, such that the metal material constituting the second conductive layer is diffused into the insulator, and the insulator forms a wiring connection portion.
The method for manufacturing a semiconductor device according to claim 11, wherein the first conductive layer and the second conductive layer are electrically connected to each other.
[0032]
(Supplementary note 12) The method of manufacturing a semiconductor device according to Supplementary note 11 or 12, wherein a direction in which the metal material diffuses into the wiring connection part is a direction perpendicular to a main surface.
[The invention's effect]
As described above, according to the present invention, a contact via can be formed by selectively diffusing a metal wiring material into an insulator. Therefore, there is no erosion of the insulating film or the wiring metal in the cleaning step, and there is no increase in the wiring resistance due to the oxidation of the wiring surface, and the wiring delay of the LSI can be significantly reduced by miniaturizing the contact via.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention (cross-sectional view of a wiring structure).
FIG. 2 is a sectional view (steps a and b) of a semiconductor device during a manufacturing process according to an embodiment of the present invention;
FIG. 3 is a sectional view (steps c and d) of the semiconductor device according to the embodiment of the present invention during the manufacturing process;
FIG. 4 is a sectional view (steps e and f) of the semiconductor device according to the embodiment of the present invention during the manufacturing process thereof;
FIG. 5 is a cross-sectional view of the semiconductor device in the course of the manufacturing process according to the embodiment of the present invention (processes g and h).
FIG. 6 is a cross-sectional view (steps i and j) of the semiconductor device during the manufacturing process according to the embodiment of the present invention;
FIG. 7 is a cross-sectional view of a semiconductor device in the course of a manufacturing process according to an embodiment of the present invention (processes k and l).
FIG. 8 is a cross-sectional view (steps m and n) of the semiconductor device in the course of the manufacturing process according to the embodiment of the present invention;
FIG. 9 is a sectional view (steps o and p) of a semiconductor device according to an embodiment of the present invention in the course of manufacturing the semiconductor device;
FIG. 10 is a sectional view (a, b) of a semiconductor device during a manufacturing process according to another embodiment of the present invention;
FIG. 11 is a sectional view (c, d) of a semiconductor device according to another embodiment of the present invention during the manufacturing process thereof;
FIG. 12 is a sectional view (e, f) of a semiconductor device according to another embodiment of the present invention during the manufacturing process thereof;
FIG. 13 is a sectional view (g, h) of the semiconductor device according to another embodiment of the present invention during the manufacturing process thereof;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation oxide film 3 Gate insulating film 4 Gate electrode 5 Side wall 6 Protective film 7 Source / drain region 8 Silicon oxide film 9 Silicon nitride film 10 Tantalum nitride film 11 Tungsten plug 12, 20 Low dielectric constant insulating film 13 Silicon nitride films 14, 28 Tantalum nitride film 15 Copper seed layer 16 Copper plating layer 17 Copper buried wiring layer 18 High density insulating films 19, 21 Silicon nitride film 22 Tantalum nitride film 23 Copper seed layer 24 Copper plating layers 25, 26 Copper Embedded wiring layer 27 Wiring connection part 29 Low density insulator (porous silica film)
30 Plasma CVD silicon nitride film

Claims (5)

A first conductive layer,
A metal material constituting the first conductive layer diffuses into the insulator and has a conductive wiring connection portion,
A semiconductor device configured to electrically conduct between the first conductive layer and the insulator. The wiring connection portion is a silicon oxide film (SiO2), a silicon carbide oxide film (SiOC), a silicon fluoride oxide film (SiOF), a silicon nitride oxide film (SiON), a silicon carbonitride oxide film (SiCON), a silicon carbide nitride film. 2. The semiconductor device according to claim 1, wherein the semiconductor device is made of any one of (SiCN) and an organic insulating material. The insulator formed around the wiring connection portion is made of any one of a silicon nitride film (SiN), silicon carbide (SiC), and silicon hydride (SiC: H). 3. The semiconductor device according to 2. Forming a first conductive layer;
Forming an insulator;
A step of applying heat or an electric field, such that the metal material constituting the first conductive layer is diffused into the insulator, and the insulator forms a wiring connection portion.
A method for manufacturing a semiconductor device configured to electrically conduct between the first conductive layer and the insulator. Forming the wiring connection portion so as to be in contact with the second conductive layer,
A step of applying heat or an electric field, such that the metal material constituting the second conductive layer is diffused into the insulator, and the insulator forms a wiring connection portion.
The method according to claim 4, wherein the first conductive layer and the second conductive layer are electrically connected.

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