JP2004193269A - Manufacturing method of mask, and manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily inspect the defects in the multilayer film of a reflecting mask. <P>SOLUTION: The defect is inspected for the multilayer film mask blanks which are used for substrates for manufacturing a reflecting multilayer film mask for pattern transfer in the exposure process using extreme ultraviolet ray. Here, firstly, a multilayer film formation surface of the multilayer film mask blanks is inspected for a relatively wide range at a relatively low magnification (steps 100a-100d). Then, the position of a defective candidate found in that inspection step is inspected in detail at a relatively high magnification(steps 102a-102f). Thus, defects of the multilayer film of the multilayer film mask blanks are quickly and easily inspected at high sensitivity. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a mask manufacturing technique, and particularly, to inspect a reflection type master such as a mask (including a reticle) used for pattern exposure transfer using exposure light having a short wavelength such as extreme ultraviolet light or X-ray. It relates to technology that is effective when applied to
[0002]
[Prior art]
In the manufacture of a semiconductor integrated circuit device (LSI: Large Scale Integrated circuit), a lithography technique for forming a fine pattern on a wafer is important. In this lithography technique, a so-called optical reduction projection exposure method in which a pattern formed on a mask is repeatedly transferred onto a wafer via a reduction projection optical system is mainly used. In this exposure method, generally, exposure light in the ultraviolet region, for example, i-line (wavelength λ = 365 nm) of a mercury lamp, KrF excimer laser (λ = 248 nm), and further, ArF excimer laser (λ = 193 nm) are used. As a mask for pattern projection, a so-called transmissive mask that forms a desired pattern using a transparent glass substrate transmitting portion of exposure light and a light blocking portion made of a chrome film or the like is used.
[0003]
However, in the reduction projection exposure method using the above-mentioned ultraviolet light, the resolution reaches near the diffraction limit of light, and in order to achieve higher resolution, light having a shorter wavelength needs to be used as exposure light. Is coming. Therefore, a lithography technique using extreme ultraviolet (EUV) light as the exposure light is promising. This is described in, for example, Japanese Journal of Applied Physics, 1991, 30, No. 11B, page 3051. Since EUV light has extremely low transmittance in all glass materials, all projection optical systems and masks have to be multilayer reflective surfaces. The mask forms a multilayer film on the surface of the substrate and is used as a reflection surface of EUV light. By forming an absorber that does not reflect EUV light on the multilayer film, or by removing a part of the multilayer film so that EUV light is not reflected, a reflecting portion of the multilayer film and the absorber or the multilayer can be used. A desired pattern is formed by the non-reflection part by the film removal part.
[0004]
By the way, when various defects such as chipping of a pattern and adhesion to a transmissive portion occur in a mask, the defects are reflected in a projection image obtained by exposure. Therefore, it is necessary to inspect the presence or absence of a defect after manufacturing the mask, and to correct the defect if any. If the defect cannot be corrected, it will be a defective product. In the transmission type mask having the chrome light-shielding film or the like, the defect inspection can be performed relatively easily because the transparent and opaque portions with respect to the exposure light, ultraviolet light, and the like may be examined. However, in a reflective multilayer mask using EUV light as exposure light, in addition to miniaturization of the defect size to be inspected and a decrease in contrast of reflected light from the mask pattern, etc., currently used inspection by ultraviolet rays or the like is not possible. It is not always easy to implement. Further, in the multilayer film of the reflection type mask, as the number of multilayer films to be stacked increases, the possibility that a defect occurs in the film increases. In a reflective mask manufactured from a mask blank having a defect in the multilayer film, the reflectance is lowered or a phase change occurs at the defective portion, and a desired pattern cannot be transferred.
[0005]
With respect to defect inspection of a multilayer film of a reflection type mask, an inspection apparatus using a so-called X-ray microscope is disclosed, for example, in JP-A-6-349715. In addition, as described in, for example, Japanese Patent Application Laid-Open No. 9-318330, an inspection apparatus that scans an object to be inspected with a laser beam of visible light or ultraviolet light, causes light scattering, and checks a light scattering state to find a defect. It has been disclosed. Further, as disclosed in, for example, JP-A-11-354404, a method of inspecting a multilayer defect by forming a peelable pattern on a multilayer mask and actually performing pattern transfer and inspecting the pattern is disclosed. Have been.
[0006]
[Problems to be solved by the invention]
However, for example, the defect inspection apparatus using an X-ray microscope described in the above-mentioned Japanese Patent Application Laid-Open No. Hei 6-349715 examines only the reflectance of the multilayer film, so that it is not possible to detect all defects that cause a phase change. Can not. In addition, for example, an inspection apparatus that scans a laser beam described in Japanese Patent Application Laid-Open No. 9-318330 to cause light scattering and examines a light scattering state also detects EUV light because it detects only a change in the external shape of the reflective mask surface. There is a problem that it is not possible to detect all of the defects that cause a phase change in. Further, for example, the inspection method described in Japanese Patent Application Laid-Open No. 11-354404 can detect a phase defect, but requires a step of actually performing pattern transfer, and is complicated as an inspection. In addition, in any of the inspection methods, when a defect that is difficult to correct is detected, the defect is treated as a defective product even if it is a minute-sized defect.
[0007]
An object of the present invention is to provide a technique capable of easily inspecting a defect in a multilayer film of a reflective mask.
[0008]
Another object of the present invention is to provide a technique capable of manufacturing a reflective mask having a multilayer structure at a high yield.
[0009]
Still another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor integrated circuit device manufactured using a reflective mask having a multilayer structure.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
That is, in the present invention, in the defect inspection of the multilayer mask blanks, first, after inspecting a relatively wide range at a relatively low magnification, the position of the defect existence candidate found in the inspection step is relatively determined this time. It has a step of inspecting at an extremely high magnification.
[0013]
Further, the present invention, when forming an absorber pattern on the multilayer mask blanks, a step of shifting and arranging the absorber pattern so that defects found in the multilayer mask blanks are not transferred as defects during exposure processing. Have
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
In the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other and one is the other. In some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), a case where it is particularly specified, and a case where it is clearly limited to a specific number in principle, etc. However, the number is not limited to the specific number, and may be more than or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified, and when it is deemed essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, the shapes are substantially the same unless otherwise specified and in cases where it is considered that it is not clearly apparent in principle. And the like. This is the same for the above numerical values and ranges. In all the drawings for describing the present embodiment, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted. In the present embodiment, a MIS • FET (Metal Insulator Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel MIS • FET is abbreviated as pMIS, and an n-channel MIS • FET is referred to. Is abbreviated as nMIS. Further, in some drawings used in the present embodiment, hatching is used even in a plan view so as to make the drawings easy to see.
[0015]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
(Embodiment 1)
First, a mask inspection technique according to the present embodiment will be described with reference to FIGS. FIG. 1 is a diagram showing the multilayer mask blanks MB. FIG. 1A is a plan view of a main part of the multilayer mask blank MB, and FIG. 1B is a cross-sectional view taken along line A1-A1 in FIG. The ultra-smooth substrate (mask substrate) 1 is made of, for example, quartz, silicon (Si), BK7, or the like, and its surface is in a mirror-like state with almost no roughness in order to obtain a high reflectance. On the surface of the ultra-smooth substrate 1, a multilayer film 2 that reflects EUV light is formed. The multilayer film 2 is configured by alternately stacking, for example, silicon (Si) and molybdenum (Mo) (all layers, for example, about 40 layers). This step is a step before forming the absorber pattern. FIG. 1 illustrates a case where fine irregularities are present on the surface of the ultra-smooth substrate 1, so that the irregularities on the surface remain even after the formation of the multilayer film 2, and these are present as phase defects 3. In the case of a mask blank of a normal mask using chrome as a light-shielding member, it is not necessary to form a multilayer film and no projection is formed, so that it is unnecessary to inspect the mirror surface of the mask blank. However, in the multi-layer mask, since the light having a wavelength of about 1/10 of the exposure light used in the normal mask is used, the size of the problematic defect becomes ten times as severe. From these viewpoints and the like, the multilayer mask blanks used in the production of the multilayer mask require the inspection of the surface state which was not required by the above-mentioned ordinary mask.
[0017]
FIG. 2 is a diagram showing a configuration example of the mask inspection apparatus 4 of the present embodiment for detecting a defect in the multilayer mask blank MB. The mask inspection apparatus 4 includes a light source 4a that emits EUV light, a mask stage 4b, a projection optical system L, a two-dimensional array type sensor 4c, a defect position storage unit 4d, a main control system 4e, and the like. The multilayer mask blank MB to be inspected for defects is placed on the mask stage 4b, and EUV light BM having a wavelength of 13.5 nm emitted from the light source 4a is bent by the mirror 4f to a predetermined area of the multilayer mask blank MB. Irradiate. In the inspection, the same light as the exposure light is used. The reflected light from the multilayer mask blank MB is collected on the sensor 4c via the projection optical system L. The position of the multilayer mask blank MB to be inspected is determined by detecting the position of the mirror 4g fixed to the mask stage 4b by the laser length measuring device 4h. The position information obtained therefrom is transmitted to the main control system 4e. The main control system 4e drives the drive system 4i while monitoring the information, and moves the mask stage 4b. Further, the alignment of the surface of the multilayer mask blank MB in the focal direction is performed by irradiating the surface of the multilayer mask blank MB with laser light in an oblique direction from the light source 4j, and the reflected light always reaches a predetermined position of the sensor 4k. The mask stage 4b was controlled as described above. Further, a plurality of laser light sources and a plurality of sensors are used to simultaneously focus a plurality of points near the inspection region, thereby correcting a tilt error of the surface of the multilayer mask blank MB. The detected image focused on the two-dimensional array type sensor 4c and its processing will be described later. The main control system 4e determines whether the signal detected by the sensor 4c indicates a defect. Reference numeral 4m indicates an aperture, and reference numeral 4n indicates an optical system control unit that drives the aperture 4m. Reference numeral 4p indicates an alignment scope for adjusting the irradiation position of the EUV light BM. Further, reference numeral BMa indicates a convergent beam obtained by blocking specular reflection light out of the reflected light from the multilayer mask blank MB and transmitting only the spread reflected light through the projection optical system L.
[0018]
FIG. 3 shows an explanatory diagram of the EUV light source of FIG. As shown in FIG. 3, a pulse laser beam 4a2 emitted from a laser light source 4a1 is applied to a target 4a4 via a lens 4a3 to generate a plasma light source 4a5. EUV light generated from the plasma light source 4a5 is collected by a collection mirror 4a6 having a multilayer film formed on the surface thereof, and EUV light BM for irradiation is generated. FIG. 4 is an explanatory diagram of the projection optical system of FIG. As the projection optical system L, a Schwarzschild imaging optical system which is a combination of a concave mirror La and a convex mirror Lb was used. In this optical system, a central portion does not contribute to image formation. Therefore, of the reflected light from the multilayer mask blank MB, the specularly reflected light is blocked, and only the spread reflected light passes through the projection optical system L to become a convergent beam BMa and is condensed on the light receiving surface of the sensor 4c. I do. If there is no defect on the surface of the multilayer mask blank MB, the specularly reflected light does not reach the sensor 4c. That is, it is a dark-field imaging optical system. Here, the optical system control unit 4n drives the aperture 4m to change the numerical aperture (NA) of the projection optical system L, or performs magnification conversion by replacing the optical system (not shown in detail). Has a function. That is, it is possible to select an imaging optical system having a different magnification by the optical system control unit 4n. For example, assuming that the size of the defect is about 30 nm, the scattered light caused by the defect has a spread of about 0.4 rad. Therefore, the numerical aperture (NA) of the Schwarzschild imaging optical system is set to 0.2 as a standard. However, the aperture range of the EUV light can be changed by the aperture 4m, which is a numerical aperture variable means, and the numerical aperture is substantially variable within a range of, for example, about 0.15 to 0.3.
[0019]
Such a Schwarzschild imaging optical system cannot make the area in which an image can be formed so large. Therefore, when an image formation area is particularly widened at a low magnification, a projection optical system L including four reflection mirrors, for example, as shown in FIG. The image forming area of the projection optical system L basically has a shape that draws an arc as shown by reference numeral D in FIG. 5B, but may be used as a surface of the sensor 4c as appropriate. FIG. 4 illustrates a case where the aperture 4m is interposed between the concave surface of the concave mirror La and the convex mirror Lb. In this case, high image forming properties can be obtained, but the present invention is not limited to this. As shown in FIG. 6, a structure may be employed in which the concave mirror La is interposed between the concave mirror La and the sensor 4c, as shown in FIG. In this case, the assembly of the mask inspection device 4 can be facilitated.
[0020]
Next, details of the flow of the mask inspection method of the present embodiment will be described with reference to FIG. In the present embodiment, a detection process using a low-magnification projection optical system (up to steps 100a, 100b, 100c, 100d, and 101) and a local detection process using a high-magnification projection optical system (from step 102) are mainly described. Separated.
[0021]
First, a multilayer mask blank MB having a multilayer film 2 formed on an ultra-smooth substrate 1 made of, for example, quartz or BK7 is placed on a mask stage 4b (step 100a). FIG. 8 shows an overall plan view of the multilayer mask blank MB. Prior to the inspection, the multi-layer mask blank MB is provided with, for example, fiducial marks 5 in the vicinity of two corners around the multi-layer mask blank MB, for example. FIG. 9 illustrates a specific structure of the reference mark 5. 9A is a plan view of a main part of the reference mark 5 in FIG. 8, and FIG. 9B is a cross-sectional view taken along line A2-A2 in FIG. 9A. On a part of the surface of the ultra-smooth substrate 1 constituting the multilayer mask blank MB, a fine width concave portion 6 is formed in advance by FIB (Focused Ion Beam) or the like, and an ordinary multilayer film is formed so as to cover the concave portion 6. By depositing 2, the reference mark 5 is formed in the recess 6 portion. FIG. 9 illustrates a case where two concave portions 6 are formed at one position. This concave portion 6 is recognized as a pattern portion having a large phase change when observed with EUV light. Therefore, hereinafter, the reference mark 5 is used as a reference for coordinates on the multilayer mask blank MB to define the coordinates of the defect to be detected. The reference mark 5 is designed to be capable of detecting a pattern from reflected light even when irradiated with an electron beam or visible light. Thereby, for example, when the absorber pattern is formed, the reference mark 5 and the defect can be detected by the electron beam. Further, the reference marks 5 are preferably arranged at two or more positions. By arranging the reference mark 5 at two or more positions, the rotational deviation of the multilayer mask blank MB can be measured, and its correction and correction can be performed. However, it is difficult to set the reference coordinates even if the number of the reference marks 5 is too large. Therefore, in the present embodiment, the reference marks 5 are arranged at two places, one near each of two corners. . Although not particularly limited, the plane size of the reference mark 5 is, for example, about 200 to 2000 nm.
[0022]
Subsequently, after the alignment between the multilayer mask blank MB and the mask inspection apparatus 4 is performed using the reference mark 5 (step 100b), first, an enlarged inspection optical system with a low magnification (for example, 30 times) is set ( In step 100c), the entire surface of the multilayer mask blanks MB on which the multilayer film 2 is formed is inspected (step 100d). At this time, the mask stage 4b is continuously moved, one image is captured by the sensor with one pulse of the inspection light source, the inspection target surface of the multilayer mask blank MB is sequentially scanned, and the semiconductor integrated circuit pattern of the multilayer mask blank MB is scanned. The formation area was inspected. The size of the semiconductor integrated circuit pattern formation region is, for example, about 100 mm × 130 mm. The sensor 4c has, for example, 1000 × 1000 pixels, and the pixel size is 300 nm on a side as converted on a mask. Therefore, the area captured by one image of one pulse of the inspection light source is, for example, 0.3 mm × 0.3 mm. This low magnification inspection is completed in about one hour. At this time, a defect candidate position is stored from the pixel position determined as a defect.
[0023]
Next, when it is determined in step 101 that there is a defect candidate position (first area), the inspection is performed again according to the following flow. That is, the magnification inspection optical system is set to a high magnification (step 102a), the mask stage 4b is moved to a defect candidate position (step 102b), and only the candidate position and its peripheral portion are inspected (step 102c). Here, if the defect is determined again (step 102d), the defect position is stored in a high-resolution coordinate system (step 102e). Inspection is performed again at all the defect candidate positions (step 102f), and a table of the coordinates of the defect position is created (step 103), and the inspection ends. Here, as a setting method of the high-magnification magnifying inspection optical system, the optical system was switched to a 150-magnification optical system. However, the present invention is not limited to this. For example, a zooming tube is arranged on the sensor surface to increase the apparent magnification. You can also. Although it is difficult to set a magnification of 150 times with one lens system, a zooming tube electronically enlarges an optical image, so that it is possible to set a magnification of an optical image without setting an unreasonable magnification in an inspection optical system.
[0024]
Here, an image captured on the detection surface of the sensor 4c will be described. FIGS. 10A and 10B show intensity distributions of inspection images obtained for phase defects having different sizes (reference signs PI1 and PI2). In FIGS. 10A and 10B, the horizontal axis represents the mask-converted coordinates detected by the sensor, and the vertical axis represents the light intensity distribution. However, the actual detection signal is captured by the pixel size of the sensor 4c. Therefore, as shown in FIGS. 11A and 11B, when an image of the phase defect 3 of, for example, about 60 nm is captured using a high-magnification inspection optical system with a pixel size (PS1) of, for example, 50 nm, a detection signal is generated. Are obtained as indicated by reference signs PI3 and PI4, as shown in FIG. As shown in FIGS. 12A and 12B, when an image of a phase defect 3 of, for example, about 60 nm is captured using a low-magnification inspection optical system with a pixel size (PS2) of, for example, 200 nm, a detection signal is generated. Are obtained as shown by symbols PI5 and PI6a as shown in FIG.
[0025]
As described above, in the present embodiment, the defect inspection of the multilayer mask blanks is performed by the inspection systems having different magnifications. That is, first, after inspecting a relatively wide range at a relatively low magnification (first inspection step), the position of the defect presence candidate found in the first inspection step is now determined at a relatively high magnification. Inspection (that is, in detail) (second inspection step). Thereby, the defect of the multilayer film 2 of the multilayer mask blank MB can be easily inspected. In particular, various defects of the multilayer mask blank MB can be inspected with high sensitivity and high speed, and the coordinate information of the defect can be obtained accurately.
[0026]
(Embodiment 2)
In this embodiment, a method for manufacturing a multilayer mask will be described with reference to FIGS. FIG. 13 is a diagram showing an example of the flow of the method of manufacturing a multilayer mask.
[0027]
First, the absorber pattern data of the multilayer mask pattern to be manufactured is read (step 200a). Next, the position information of the defect of the multilayer mask blank inspected by the inspection method described in the first embodiment is read (step 200b). The actual number of defects in the multilayer mask blanks is about several tens at most, and is reduced to several or less due to improvement in manufacturing technology. Next, in step 200c, the position where the absorber pattern is formed is compared with all the stored defect positions. Here, if all of the multilayer defects are covered with the absorber pattern, the multilayer defects are practically not defects. Further, if a fine phase defect is present in isolation on a wide multilayer film reflecting surface where no absorber is present, this is not a defect. The above-described comparison is performed for all the defect positions, and for example, a shift amount is obtained such that, if the entire absorber pattern is shifted, the defect is practically eliminated. When the shift amount is obtained, in step 200d, an absorber pattern is formed to manufacture a multilayer mask. The formation of the absorber pattern includes an electron beam lithography step. In determining the lithography position in consideration of the shift amount, the reference mark 5 (see FIGS. 8 and 9) of the multilayer mask blank MB described above is used. Good. On the other hand, if it is determined in step 200c that all the defects cannot be located at the position of the light-shielding pattern, the multilayer mask blank is corrected or discarded if correction is impossible (step 201).
[0028]
FIG. 14 shows the reference mark 5 on the multilayer mask blank MB, the detected phase defect 3, the pattern area CA and the alignment pattern 7 of the semiconductor integrated circuit device. The alignment pattern 7 is a pattern used for aligning the multilayer mask and the EUV exposure apparatus when placing the multilayer mask on the EUV exposure apparatus. FIG. 15 is a diagram showing the positional relationship between the absorber pattern 8a formed on the multilayer mask and the multilayer defect 3, and FIG. 15 (a) shows the effect of the defect when the mask pattern of the multilayer mask is transferred. Is the case that comes out. In this case, a short circuit may occur between adjacent patterns on the wafer. FIG. 15A illustrates a case where the phase defect 3 is located between relatively narrow adjacent absorber patterns 8a. However, if the position where the absorber pattern 8a is formed is shifted as shown in FIGS. 15B and 15C, the phase defect 3 on the multilayer mask can be prevented from being transferred. It can be a good quality mask. In FIG. 15B, the phase defect 3 is included in the region of the absorber pattern 8a, and in FIG. 15C, the phase defect 3 is arranged only one away from the absorber pattern 8a. Are respectively illustrated. In particular, when manufacturing a mask for transferring a hole pattern such as a contact hole or a through hole, the ratio of the absorber pattern region is large, and the defect is included in the absorber pattern 8a and hidden. Therefore, the effect of improving the yield of mask blanks by this method is extremely large.
[0029]
When the formation position of the absorber pattern 8a is shifted in this way (for example, when the position of the entire pattern area CA of the semiconductor integrated circuit device of the multilayer mask is shifted from the original position), the shift amount is stored. deep. Then, when a desired pattern is transferred to the wafer by exposure processing using the multilayer mask, the pattern is exposed on the wafer in consideration of the shift amount of the absorber pattern 8a. That is, exposure is performed in a state where the position of the wafer is shifted by the shift amount of the absorber pattern 8a from the relative position considered to be correct in design between the wafer and the multilayer mask that are aligned using the alignment pattern of the multilayer mask. Perform processing. Thus, the pattern on the multilayer mask can be transferred onto the wafer with good alignment.
[0030]
Next, an example of a method for manufacturing the reflective multilayer mask of the present embodiment will be described. FIGS. 16A to 16E are main-portion cross-sectional views of the multilayer mask of the present embodiment during the manufacturing process thereof. First, as shown in FIG. 16A, an ultra-smooth substrate 1 having almost no roughness is prepared to obtain a high reflectance, and a multilayer film 2 is formed thereon as shown in FIG. 16B. . What formed the multilayer film 2 on the ultra-smooth substrate 1 is generally called a multilayer blank mask or multilayer blanks. In general, the multilayer film 2 is formed by a physical vapor deposition method such as an ion beam sputtering vapor deposition method or a magnetron sputtering vapor deposition method, a chemical vapor deposition (CVD) method, or an atomic layer epitaxy (ALE). ) Is used. It is preferable that the entire surface of the multilayer mask blank is a mirror surface, and is formed so as to reflect 60 to 70% or more of the incident EUV light by forming the multilayer film 2. Next, as shown in FIG. 16C, an absorber 8 that is to be a non-reflective portion of the reflective mask is formed on the multilayer film 2 with the buffer layer 9 interposed therebetween. In the formation of the absorber 8, a physical vapor deposition method such as an ion beam sputtering vapor deposition method or a magnetron sputtering vapor deposition method or a chemical vapor deposition vapor deposition (CVD) method is used in the same manner as in the formation of the multilayer film 2. Examples of the material of the absorber 8 include tungsten (W), tantalum (Ta), gold (Au), chromium (Cr), titanium (Ti), germanium (Ge), nickel (Ni), and cobalt (Co). A simple substance or a compound of such a metal, semimetal, or semiconductor material is used. Thereafter, in order to pattern the absorber 8 and form a desired absorber pattern, a resist film R is formed on the absorber 8, and i-line exposure (λ = 365 nm) and KrF excimer laser exposure (λ = 248 nm) 16), a pattern of the resist film R is formed as shown in FIG. 16D by a lithography technique such as electron beam drawing, 1: 1 exposure X-ray, ion beam exposure, EUV exposure, or the like. Finally, the absorber 8 is processed by reactive ion etching or the like using the pattern of the resist film R as a mask, the resist film R is removed, and an absorber pattern 8a is formed as shown in FIG. The film mask M is manufactured.
[0031]
As described above, by employing the mask manufacturing method of the present embodiment, it is possible to improve the yield of the multilayer mask by manipulating the positional relationship between the absorber pattern 8a and the phase defect 3, and as a result, As a result, a low-cost mask can be supplied. In the exposure process using the multilayer mask, the pattern of the multilayer mask is formed on the wafer with good alignment by taking into account the shift amount of the absorber pattern 8a in the relative plane position between the multilayer mask and the wafer. it can. Therefore, the performance, reliability, and yield of the semiconductor integrated circuit device can be improved. Further, cost reduction of the multilayer film mask can promote cost reduction of a semiconductor integrated circuit device requiring high performance.
[0032]
(Embodiment 3)
In this embodiment, a method for manufacturing a semiconductor integrated circuit device using the above-described multilayer mask will be described. Prior to this description, an EUV exposure apparatus used for transferring a pattern onto a semiconductor substrate using a multilayer mask will be described in detail.
[0033]
The exposure apparatus used here is, for example, a reduction projection exposure apparatus that uses extreme ultraviolet light (EUV light) having a wavelength of 13.5 nm as exposure light. One example is shown in FIG. The exposure apparatus 10 includes a light source 10a that emits EUV light, a mask stage 10b, a projection optical system 10c, a wafer stage 10d, and the like. The multilayer mask M is placed on the mask stage 10b, and the wafer 11W is placed on the wafer stage 10d, and the mask pattern on the multilayer mask M is transferred to the wafer 11W. The multilayer mask M is placed so that the multilayer film 2 on its main surface and the absorber pattern face the projection optical system 10c. The wafer 11W is arranged so that the resist film deposited on the main surface thereof faces the projection optical system 10c. The EUV light emitted from the light source 10a is applied to the surface of the multilayer mask M on which the multilayer film 2 and the absorber pattern 8a are formed, and the light reflected therefrom passes through the projection optical system 10c to the main surface of the wafer 11W (resist deposition). Surface). As the exposure method, for example, a step-and-scan exposure method was adopted. The multilayer mask M on the mask stage 10b is appropriately replaced according to the type of pattern desired to be transferred. The position control of the mask stage 10b is performed by a drive system 10e. The position control of the wafer stage 10d is performed by a drive system 10f. The drive systems 10e and 10f are driven according to a control command from the main control system 10g. The position of the multilayer mask M is obtained by detecting the position of the mirror 10h1 fixed to the mask stage 10b by the laser length measuring device 10h2. Similarly, the position of the wafer 11W is obtained by detecting the position of the mirror 10i1 fixed to the wafer stage 10d by the laser length measuring device 10i2. The position information obtained therefrom is transmitted to the main control system 10g. The main control system 10g drives the drive systems 10e and 10f based on the information to scan the multilayer mask M and the wafer 11W synchronously. A pattern in a limited area on the multilayer mask M can be transferred. In particular, a multilayer film in which the center position of the absorber pattern 8a is shifted with respect to the center of the mask substrate (ultra-smooth substrate 1). The transfer position of the mask M can be appropriately shifted using the shift amount as an input value.
[0034]
Next, an example of a method for manufacturing the semiconductor integrated circuit device according to the present embodiment will be described. 18 shows a two-input NAND gate circuit ND. FIG. 18A shows a symbol diagram, FIG. 18B shows a circuit diagram thereof, and FIG. 18C shows a layout plane. In FIGS. 18A and 18B, reference numerals I1 and I2 indicate input terminals, Qp indicates pMIS, and Qn indicates nMIS. In FIG. 18C, a portion surrounded by a dashed line is a unit cell UC, and two nMIS portions Qn formed in the n-type semiconductor region 15n on the surface of the p well PW and a p cell on the surface of the n well NW. And two pMIS portions Qp formed on the semiconductor region 15p of the mold type. Reference numeral 16G is a common gate electrode of pMISQp and nMISQn, reference numeral 17L1 is a first layer wiring, reference numeral 17L2 is a second layer wiring, and reference numeral CNT is a connection between the first layer wiring 17L1 and the semiconductor regions 15p, 15n and the gate electrode 16G. A contact hole and a symbol TH indicate through holes for connecting the first layer wiring 17L1 and the second layer wiring 17L2, respectively.
[0035]
In order to fabricate this structure, masks NM1 to NM3 and multilayer masks M1 to M3 as shown in FIG. 19 were repeatedly used. Among them, the masks NM1 to NM3 are ordinary masks for photolithography, and a light shielding portion such as a chromium film is disposed on a main surface of a mask substrate made of transparent synthetic quartz glass or the like. In FIG. 19, reference numerals 20a, 20b, and 20c denote light transmitting portions, and reference numerals 21a, 21b, and 21c denote light shielding portions formed of a chrome film or the like. On the other hand, the multilayer film masks M1 to M3 are the masks for EUV lithography described in the first and second embodiments. Reference numerals 22a, 22b, and 22c denote EUV light reflecting portions of the multilayer film 2, and reference numerals 23a, 23b, and 23. Reference numeral 23c denotes an EUV light absorbing section in which the absorber 8 exists.
[0036]
Next, an example of a method of manufacturing the semiconductor integrated circuit device of FIG. 18 using the masks NM1 to NM3 and the multilayer masks M1 to M3 of FIG. 19 will be described. First, the steps up to the step of forming the pMISQp and nMISQn of the semiconductor integrated circuit device of FIG. 18 will be described with reference to FIGS. 20 and 21 assuming a cross-sectional view taken along a broken line A3-A3 in FIG. As shown in FIG. 20A, an insulating layer made of, for example, a silicon oxide film is formed on a main surface (device forming surface) of a semiconductor substrate (hereinafter, referred to as a substrate) 11S made of a p-type silicon single crystal constituting the wafer 11W. After the film 25a is formed by an oxidation method, an insulating film 26a made of, for example, a silicon nitride film is deposited thereon by a CVD (Chemical Vapor Deposition) method, and a resist film R1 is further deposited thereon. Subsequently, as shown in FIG. 20B, an exposure and development process is performed using the normal light transmission type mask NM1 to form a pattern of the resist film R1. Here, i-line (λ = 365 nm), krypton fluoride (KrF) excimer laser light (λ = 248 nm), argon fluoride (ArF) excimer laser light (λ = 193 nm), or fluorine (F ₂ ) A laser beam (λ = 157 nm) or the like is used. Thereafter, as shown in FIG. 20C, the insulating film 26a, 25a and the substrate 11S exposed from the resist film R1 are sequentially removed using the pattern of the resist film R1 as an etching mask. A shallow groove 27 is formed. Next, as shown in FIG. 20D, an insulating film 25b made of, for example, silicon oxide is deposited on the main surface of the wafer 11W by a CVD method or the like, and then, for example, a chemical mechanical polishing (CMP: By performing a planarization process by Chemical Mechanical Polishing or the like, an element isolation structure SG is finally formed on the main surface of the wafer 11W as shown in FIG. In the present embodiment, the element isolation structure SG is a groove-type isolation structure. However, the present invention is not limited to this. For example, the element isolation structure SG may be formed of a field insulating film by a LOCOS (Local Oxidation of Silicon) method.
[0037]
Next, as shown in FIG. 21A, exposure and development are performed using the normal light transmission type mask NM2 to form a pattern of the resist film R2 on the main surface of the wafer 11W. Since the region where the n-well NW is to be formed is exposed, for example, phosphorus (P) or arsenic (As) is ion-implanted into the substrate 11S to form the n-well NW. Similarly, as shown in FIG. 21B, after the pattern of the resist film R3 is formed by using the normal light transmission type mask NM3, for example, boron or the like is ion-implanted to form the p-well PW. Thereafter, as shown in FIG. 21C, a gate insulating film 28 made of a silicon oxide film is formed to a thickness of about 3 nm by a thermal oxidation method, and a conductive film 16 made of polycrystalline silicon or the like is further formed thereon by a CVD method or the like. Deposited by Subsequently, after a resist film is applied to the main surface of the wafer 11W, as shown in FIG. 21D, a pattern of the resist film R4 is formed on the main surface of the wafer 11W using a multilayer film mask M1, and Using the pattern of the resist film R4 as an etching mask, the conductor film 16 exposed therefrom is etched. After that, the pattern of the resist film R4 was removed to form the gate insulating film 28 and the gate electrode 16G. In the exposure processing using the multilayer mask M1, the above-mentioned EUV light (for example, λ = 13.5 nm) was used as exposure light. Further, the mask M1 used was one in which the center of the pattern group was drawn with an electron beam shifted by about 200 μm in the X direction (predetermined direction) from the center of the main surface of the ultra-smooth substrate 1 avoiding phase defects. . Therefore, the shift amount of about 200 μm was input to an exposure control unit of an exposure apparatus using EUV light as exposure light, and exposure was performed by correcting the relative position between the mask M1 and the wafer 11W. Thereafter, as shown in FIG. 21E, a high impurity concentration n-type semiconductor region 15n for nMISQn which also functions as a source and drain region and a wiring layer, and a high impurity concentration p-type semiconductor region for pMISQp 15p were formed in a self-aligned manner with respect to the gate electrode 16G by ion implantation or diffusion using different resist patterns as masks.
[0038]
Next, an example of manufacturing a two-input NAND gate using the multilayer masks M2 and M3 shown in FIGS. FIGS. 22A to 22E are cross-sectional views taken along the broken line A3-A3 shown in FIG. 18C in the manufacturing process of the semiconductor integrated circuit device following FIG. I have. First, as shown in FIG. 22A, an interlayer insulating film made of, for example, a phosphorus-doped silicon oxide film is formed on the main surface of the wafer 11W so as to cover the two nMISQn and the two pMISQp. An insulating film 25c is deposited by a CVD method. Subsequently, as shown in FIG. 22B, a resist film R3 is applied on the main surface of the wafer 11W, and a pattern of the resist film R3 is formed using the multilayer film mask M2. As shown, a contact hole CNT is formed by an etching process. After removing the pattern of the resist film R3, a metal film 17 of, for example, aluminum, an aluminum alloy, or copper is deposited on the main surface of the wafer 11W, and the metal is buried in the contact holes CNT. Subsequently, as shown in FIG. 22D, a resist film R4 was applied on the main surface of the wafer 11W, and a pattern of the resist film R4 was formed using the multilayer film mask M3 shown in FIG. 19F. Thereafter, the first layer wiring 17L1 was formed by an etching process. Thereafter, an interlayer insulating film 25d is deposited on the wafer 11W, a through hole TH is formed in the insulating film 25d using another mask (not shown), and further, in the same manner as the first layer wiring 17L1. The upper second-layer wiring 17L2 was formed. Thus, a 2-input NAND gate group was manufactured by appropriately selecting the wiring. Here, needless to say, if the shape of the wiring is changed, another circuit such as a NOR gate circuit can be formed. Wiring between elements was performed by pattern formation in which similar steps were repeated as necessary, and a semiconductor integrated circuit device was manufactured. Since the pattern of the multilayer mask M2 has a large ratio of the absorber region, a phase defect can be avoided even when the center of the pattern group and the center of the main surface of the ultra-smooth substrate 1 are matched. However, in the multilayer mask M3, in order to avoid a phase defect, the center of the pattern group was drawn and formed shifted from the center of the main surface of the ultra-smooth substrate 1 by 100 μm in the Y direction (upward or downward in FIG. 19). . Then, when exposing with an exposure apparatus for EUV light, exposure was performed after correcting the position in the Y direction. Wiring between elements was performed by pattern formation in which similar steps were repeated as necessary, and a semiconductor integrated circuit device was manufactured.
[0039]
As described above, by applying the method of the present embodiment, when utilizing EUV lithography, a method for manufacturing a semiconductor integrated circuit device can be manufactured using a highly reliable and low-cost multilayer mask. . In addition, a normal light transmission type mask is used for forming a relatively fine pattern, and a reflective type multilayer mask is used for forming a relatively fine pattern. The cost in manufacturing the semiconductor integrated circuit device can be reduced as compared with the case of forming. Further, the manufacturing time of all the masks required for manufacturing the semiconductor integrated circuit device can be reduced as compared with the case where all the masks are multi-layer masks, so that the manufacturing time of the semiconductor integrated circuit device can be reduced.
[0040]
(Embodiment 4)
Another example of the mask manufacturing method of the present embodiment will be described with reference to FIGS. FIG. 23 shows a step of preparing a multilayer mask manufactured by the mask manufacturing method shown in the second embodiment (step 300a), and inspecting and correcting the mask. In the following step 300b, contour defects and the like of the absorber pattern of the multilayer mask are inspected by a normal mask pattern inspection method using, for example, deep ultraviolet light (λ = 248 to 266 nm) as inspection light, and are determined to be defective. Store the coordinates of the part that has been set. In the following step 300c, the defect of the absorber pattern at the stored coordinates is corrected by FIB (Focused Ion Beam) or the like.
[0041]
The repaired multilayer mask was confirmed again by the inspection flow shown in FIG. That is, the coordinates at which the defect was corrected were sequentially read out, the mask stage was moved to the coordinate position, and an enlarged projection image was captured by the bright-field detection optical system (step 400a). FIG. 25 shows an example of a bright-field detection optical system. Here, the EUV light BMb forming a bright-field image was focused on the sensor 4c using the multilayer film reflecting mirrors Lc and Ld in the Schwarzschild optical system, and the image was captured. As this image, an image similar to the transferred image obtained when the mask pattern is transferred using the exposure apparatus for EUV light is obtained. The defect correction is confirmed from this inspection image (step 400b in FIG. 24). When all the correction positions are confirmed (step 400d), the inspection is terminated. If the correction is insufficient, the coordinates are recorded again (step 400c) and the correction process is performed again.
[0042]
According to the above-described method, it is possible to surely confirm the defect repair and to manufacture a highly reliable multilayer mask M.
[0043]
The following is a brief description of an effect obtained by a representative one of the above embodiments. That is, in the inspection and manufacture of the multilayer mask blanks MB, by applying the inspection method, the inspection apparatus, and the mask manufacturing method of the multilayer mask blanks of the present embodiment, the reflective multilayer mask M for EUV light can be obtained. Defects that cause existing phase changes can be inspected in a short time. Further, by reflecting the defect position information on the formation of the absorber pattern 8a on the multilayer mask M, the yield of the multilayer mask blanks MB and the reflective multilayer mask M can be improved and the cost can be reduced. In addition, by using the method of manufacturing a semiconductor integrated circuit device, a highly reliable highly integrated semiconductor device can be manufactured with a high yield using a reflective multilayer mask M for defect-free low-cost EUV light. .
[0044]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0045]
For example, in this embodiment, EUV light as exposure light has a wavelength of 13.5 nm. However, the present invention is not limited to this, and various changes can be made. For example, the wavelength is 5 to 20 nm, and preferably the wavelength is 11 The present invention can also be applied to the case where light having a wavelength of １４14 nm, particularly light having a wavelength of 11 nm or 13.4 nm is used. Of course, the present invention can be applied to any exposure treatment using a reflection-type multilayer mask, and the principle of the present invention can be similarly applied to the case of using light in a short wavelength end region of ultraviolet light having a wavelength of less than 100 nm. is there.
[0046]
In the above description, the case where the invention made by the present inventor is mainly applied to a method of manufacturing a semiconductor integrated circuit device having a NAND circuit, which is a utilization field as a background, has been described, but the invention is not limited thereto. For example, a semiconductor integrated circuit device having a memory circuit such as an SRAM (Static Random Access Memory) or a flash memory (EEPROM: Electric Erasable Programmable Read Only Memory), or a semiconductor integrated circuit device having a logic circuit such as a microprocessor or the like. The present invention can also be applied to a method of manufacturing another semiconductor integrated circuit device such as a hybrid semiconductor integrated circuit device in which a memory circuit and a logic circuit are provided on the same semiconductor substrate. INDUSTRIAL APPLICABILITY The present invention is also applicable to a pattern transfer technique by an exposure process using a mask in a manufacturing process of a liquid crystal device, an electronic device, a micromachine, or the like.
[0047]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0048]
That is, in the defect inspection of the multilayer mask blanks, first, after inspecting a relatively wide range at a relatively low magnification, the position of the defect existence candidate found in the inspection step is now changed to a relatively high magnification. Inspection by means of the above makes it possible to easily inspect for defects in the multilayer film of the reflective mask.
[0049]
In addition, when forming an absorber pattern on the multilayer mask blanks, the arrangement of the absorber pattern is shifted so that a defect found in the multilayer mask blank is not transferred as a defect during the exposure process, thereby forming a multilayer film structure. Can be manufactured at a high yield.
[0050]
Further, since the reliability of the reflective mask having the multilayer structure can be improved, the reliability of the semiconductor integrated circuit device manufactured using the same can be improved.
[Brief description of the drawings]
FIG. 1A is a plan view of a main part of a multilayer mask blank, and FIG. 1B is a cross-sectional view taken along line A1-A1 of FIG.
FIG. 2 is an explanatory diagram of a configuration example of a mask inspection apparatus used in a mask manufacturing method according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram of the extreme ultraviolet light source of FIG. 2;
FIG. 4 is an explanatory diagram of the projection optical system of FIG. 2;
5A and 5B are explanatory diagrams of a modification of the projection optical system of FIG. 2, in which FIG. 5A is an explanatory diagram of an optical system, and FIG. 5B is an explanatory diagram of an imaging region.
FIG. 6 is an explanatory diagram of a modification of the projection optical system of FIG. 2;
FIG. 7 is an explanatory diagram of a flow of a mask inspection method in a mask manufacturing method according to an embodiment of the present invention;
FIG. 8 is an overall plan view of an example of a multilayer mask blank to be inspected.
9A is a plan view of a principal part of a reference mark portion in FIG. 8, and FIG. 9B is a cross-sectional view taken along line A2-A2 in FIG. 9A.
FIGS. 10A and 10B are graphs showing intensity distributions of inspection images obtained for phase defects having different sizes.
11A and 11B are explanatory diagrams showing a state of a defect caught by a high-magnification sensor, and FIG. 11C is a graph of an intensity distribution of a detected image of the defect caught by the high-magnification sensor. .
FIGS. 12A and 12B are explanatory diagrams showing a state of a defect caught by a low magnification sensor, and FIG. 12C is a graph of an intensity distribution of a detection image of the defect caught by the low magnification sensor; .
FIG. 13 is an explanatory diagram illustrating an example of the flow of a method for manufacturing a mask according to an embodiment of the present invention.
FIG. 14 is an overall plan view of a mask blank according to an embodiment of the present invention.
FIGS. 15A to 15C are explanatory diagrams showing a positional relationship between an absorber pattern formed on a multilayer mask and multilayer defects.
FIGS. 16A to 16E are cross-sectional views of main parts during a manufacturing process of the multilayer mask according to the embodiment of the present invention;
FIG. 17 is a diagram illustrating an example of an exposure apparatus used in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
18A is a symbol diagram of a NAND circuit which is a part of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 18B is a circuit diagram of the NAND circuit of FIG. 3A is a plan view of a layout plane of the NAND circuit in FIG.
FIGS. 19A to 19F are plan views of masks used for manufacturing the semiconductor integrated circuit device of FIG.
FIGS. 20A to 20E are cross-sectional views of main parts during a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;
21A to 21E are cross-sectional views of main parts of the semiconductor integrated circuit device in a manufacturing step following that of FIG. 20;
22A to 22E are cross-sectional views of main parts of the semiconductor integrated circuit device in a manufacturing step following that of FIG. 21;
FIG. 23 is a flowchart showing a flow of defect inspection and inspection correction in a mask manufacturing method according to another embodiment of the present invention.
FIG. 24 is a flowchart showing a flow of confirmation after defect correction in a mask manufacturing method according to another embodiment of the present invention.
FIG. 25 is an explanatory diagram showing an example of a bright-field detection optical system for mask inspection in a mask manufacturing method according to another embodiment of the present invention.
[Explanation of symbols]
1 Super smooth substrate
2 Multilayer film
3 phase defects
4 Mask inspection equipment
4a Light source
4a1 Laser light source
4a2 Pulse laser beam
4a3 lens
4a4 target
4a5 Plasma light source
4a6 Collection mirror
4b Mask stage
4c sensor
4d defect position storage unit
4e Main control system
4f mirror
4g mirror
4h laser length measuring instrument
4i drive system
4j light source
4k sensor
4m aperture
4n optical system control means
4p alignment scope
5 Reference mark
6 recess
7 Positioning pattern
8 Absorber
8a Absorber pattern
9 Buffer layer
10 Exposure equipment
10a light source
10b mask stage
10c Projection optical system
10d wafer stage
10e drive system
10f drive system
10g main control system
10h1 mirror
10h2 laser measuring device
10i1 mirror
10i2 laser length measuring instrument
11W wafer
11S semiconductor substrate
15n, 15p semiconductor region
16 Conductive film
16G gate electrode
17 Metal film
17L1 First layer wiring
17L2 Second layer wiring
20a, 20b, 20c Light transmitting part
21a, 21b, 21c Light shielding unit
22a, 22b, 22c EUV light reflector
23a, 23b, 23c EUV light absorber
25a-25d insulating film
26a insulating film
27 grooves
28 Gate insulating film
MB multilayer mask blanks
L Projection optical system
La concave mirror
Lb convex mirror
Lc, Ld Multilayer reflector
BM, BMa, BMb Extreme ultraviolet light
PS1, PS2 pixel size
CA pattern area
R resist film
R1 to R4 resist film
M, M1, M2, M3 Multilayer mask
NM1 to NM3 mask
I1, I2 input terminal
UC unit cell
PW p-well
NW n-well
ND NAND gate circuit
SG element isolation structure
Qp p-channel type MIS • FET
Qn n-channel type MIS • FET

Claims (5)

In the method for manufacturing a mask,
(A) depositing a multilayer film on a mask substrate;
(B) inspecting a surface of the mask substrate on which a multilayer film is formed;
(C) forming an absorber pattern on the surface of the mask substrate on which the multilayer film is formed to manufacture a mask;
The step (b) comprises:
(B1) irradiating extreme ultraviolet light having the same wavelength as the exposure light used in the exposure processing using the mask to the surface of the mask substrate on which the multilayer film is formed;
(B2) a step of detecting the reflected light reflected from the multilayer film by the sensor through the imaging optical system in the step (b1);
(B3) storing the position information of the first area detected in the steps (b1) and (b2), and inspecting the image by changing the magnification of the imaging optical system. Manufacturing method for a mask. In the method for manufacturing a mask,
(A) depositing a multilayer film on a mask substrate;
(B) inspecting a surface of the mask substrate on which a multilayer film is formed;
(C) forming an absorber pattern on the surface of the mask substrate on which the multilayer film is formed to manufacture a mask;
In the inspection method of the step (b), the ultraviolet light having the same wavelength as the exposure light used in the exposure processing using the mask is irradiated on the surface of the mask substrate on which the multilayer film is formed, and the reflection reflected from the multilayer film is performed. This is a method of detecting light with a sensor via an imaging optical system,
The step (b) comprises:
(B1) inspecting the entire surface of the mask substrate on which the multilayer film is formed, with the magnification of the imaging optical system being relatively low;
(B2) storing the position information of the first area detected in the inspection step (b1);
(B3) inspecting the first region of the mask substrate on which the multilayer film is formed, which is detected in the step (b1), in a state where the magnification of the imaging optical system is relatively high. Manufacturing method of mask. In the method for manufacturing a mask,
(A) depositing a multilayer film on a mask substrate;
(B) inspecting a surface of the mask substrate on which a multilayer film is formed;
(C) forming an absorber pattern on the surface of the mask substrate on which the multilayer film is formed to manufacture a mask;
The step (b) comprises:
(B1) irradiating extreme ultraviolet light having the same wavelength as the exposure light used in the exposure processing using the mask on the surface of the mask substrate on which the multilayer film is formed, and reflecting the light reflected from the multilayer film on an imaging optical system. Detecting with a sensor via
(B2) storing the position information of the defect detected in (b1);
The step (c) comprises:
(C1) comparing the position information of the defect stored in (b2) with the position information of the absorber pattern;
(C2) moving and forming the absorber pattern based on the comparison result of (c1) so that the defect is not transferred by exposure processing;
(C3) storing the amount of movement of the absorber pattern. In the method for manufacturing a mask,
(A) depositing a multilayer film on a mask substrate;
(B) inspecting a surface of the mask substrate on which a multilayer film is formed;
(C) forming an absorber pattern on the surface of the mask substrate on which the multilayer film is formed to manufacture a mask;
In the inspection method of the step (b), the ultraviolet light having the same wavelength as the exposure light used in the exposure processing using the mask is irradiated on the surface of the mask substrate on which the multilayer film is formed, and the reflection reflected from the multilayer film is performed. This is a method of detecting light with a sensor via an imaging optical system,
The step (b) comprises:
(B1) inspecting the entire surface of the mask substrate on which the multilayer film is formed, with the magnification of the imaging optical system being relatively low;
(B2) storing the position information of the first area detected in the inspection step (b1);
(B3) inspecting the first area of the mask substrate on which the multilayer film is formed, the first area being detected in the step (b1), with the magnification of the imaging optical system being relatively high;
(B4) storing position information of the defect detected in (b3),
The step (c) comprises:
(C1) comparing the position information of the defect stored in (b4) with the position information of the absorber pattern;
(C2) moving and forming the absorber pattern based on the comparison result of (c1) so that the defect is not transferred by exposure processing;
(C3) storing the amount of movement of the absorber pattern. In a method of manufacturing a semiconductor integrated circuit device,
(A) depositing a multilayer film on a mask substrate;
(B) inspecting a surface of the mask substrate on which a multilayer film is formed;
(C) forming an absorber pattern on the surface of the mask substrate on which the multilayer film is formed to manufacture a mask;
(D) transferring a desired pattern onto the main surface of the semiconductor wafer by an exposure process using light reflected when a surface of the mask on which the multilayer film and the absorber pattern are formed is irradiated with exposure light having a desired wavelength. Have
The step (b) comprises:
(B1) irradiating extreme ultraviolet light having the same wavelength as the exposure light used in the exposure processing using the mask on the surface of the mask substrate on which the multilayer film is formed, and reflecting the light reflected from the multilayer film on an imaging optical system. Detecting with a sensor via
(B2) storing the position information of the defect detected in (b1);
The step (c) comprises:
(C1) comparing the position information of the defect stored in (b2) with the position information of the absorber pattern;
(C2) moving and forming the absorber pattern based on the comparison result of (c1) so that the defect is not transferred to a semiconductor wafer by the exposure processing;
(C3) storing a moving amount of the absorber pattern,
The step (d) includes:
Transferring a pattern while shifting a relative plane position between the mask and the semiconductor wafer based on the movement amount stored in the step (c3). .

Images