JP2004186295A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce GIDL which increases due to the influence of a high electric field within a semiconductor device and moreover reduce the short-channel effect which increases when a specific dielectric constant of a gate insulation film becomes high. <P>SOLUTION: An insulating interface layer 22 is formed on the channel region 12 of a silicon substrate 1, a gate insulating film 21 having the specific dielectric constant which is higher than that of such interface layer is then formed on such insulating interface layer 22, and a gate electrode 5 is formed on the gate insulating film 21. The side surfaces of the insulating interface layer 22 and the gate insulating film 21 enter the internal side of the side surface of the gate electrode 5 as much as amount of offset B. Accordingly, these side surfaces are located on the overlap region A of the source drain regions 3, 4 overlapping on the gate electrode 5. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a structure of a gate insulating film of a MISFET (Metal Insulator Silicon Field Effect Transistor).
[0002]
[Prior art]
FIG. 12 is a cross-sectional view illustrating a conventional semiconductor device (especially, MISFET).
As shown in FIG. 12, a channel region 12 is formed in a surface layer of a well layer 11 of a substrate 1, and a source region 3 and a drain region 4 are formed on both sides of the channel region 12. A gate insulating film 25 is formed on the channel region 12, and a gate electrode 5 is formed thereon. The gate insulating film 25 is made of SiO ₂ And the like, and is formed over the entire lower surface of the gate electrode 5.
[0003]
Also, in order to suppress the short channel effect, an LDD (Lightly Doped Drain) structure in which an extension connected to a source / drain region is formed shallowly below a sidewall covering a side surface of a gate electrode is known.
[0004]
As the speed and performance of the semiconductor device increase, and the semiconductor device is miniaturized, the extension is formed to be shallower. Thereby, the sheet resistance of the extension increases. Therefore, in order to maintain the current driving capability, it is difficult to lower the voltage, and it becomes difficult to scale the voltage. As a result, the electric field inside the semiconductor device increases.
[0005]
As an effect of a high electric field in a semiconductor device, there is a drain current leak (GIDL: Gate Induced Drain Leakage) caused by a gate electric field (for example, see Non-Patent Document 1).
[0006]
A mechanism in which the above-described GIDL occurs in the semiconductor device illustrated in FIG. 12 will be described.
When a drain voltage is applied to the source region 3, the drain voltage in the channel direction and the gate electric field from the gate electrode 5 are superimposed in the overlap region A of the drain region 4 near the interface with the gate insulating film 25. You. As a result, carriers are generated by the band-to-band tunnel and leak.
This GIDL increases as the gate insulating film 25 becomes thinner and the relative dielectric constant of the gate insulating film 25 becomes higher.
[0007]
As a method of suppressing the GIDL, a structure has been proposed in which the thickness of the gate insulating film 25 in the overlap region A is increased to reduce the gate electric field in this portion. However, in this structure, there is a problem that the gate insulating film around the overlap region becomes thick due to, for example, bird's beak, and it becomes difficult to manufacture the MISFET as the miniaturization proceeds.
[0008]
Although the gate voltage is reduced as the semiconductor device is miniaturized, the gate insulating film is formed thinner so as not to reduce the gate electric field. In this case, since the tunnel current flows through the gate insulating film, the gate-drain current when the MISFET is off becomes too large to be ignored with respect to the off current of the MISFET.
[0009]
Therefore, in order to reduce the tunnel current between the gate and the drain, as shown in FIG. 13, the gate insulating film 26 has a ratio at which the physical thickness can be increased even if the electrical thickness is reduced. A material having a high dielectric constant is used.
[0010]
Next, other factors that hinder miniaturization of the MISFET will be described.
As described above, the electric field inside the MISFET increases with miniaturization. In particular, the electric field between the source and the drain becomes extremely high due to a remarkable reduction in the gate length and an increase in the drain voltage.
[0011]
As an effect of the high electric field between the source and the drain, there is a decrease in the threshold voltage (DIBL: Drain Induced Barrier Lowering) caused by the drain electric field.
[0012]
A mechanism in which the above-described DIBL occurs in the semiconductor device illustrated in FIG. 12 will be described.
When a drain voltage is applied to the source region 3, a drain electric field acts on an interface (junction) between the overlap region A of the drain region 4 and the well region 11, and a work function between the drain region 4 and the well region 11 is formed. The difference reduces the height of the formed barrier. As a result, the ON current flows at a low threshold voltage. This is due to the short channel effect.
[0013]
A device simulation of the semiconductor device shown in FIG. 12 was performed in consideration of the DIBL. FIG. 14 shows the simulation result as gate length-threshold voltage characteristics. The device simulation result of the structure of FIG. 12 in consideration of the DIBL is shown by a solid line in FIG.
Here, the conditions of the parameters of the device simulation are as follows: drain voltage Vd = gate voltage Vg = 1.0 V, source voltage Vs = substrate bias voltage Vsub = 0 V, thickness of gate insulating film 25 = 1.5 nm, gate insulating film 25 Was set to k = 3.9.
[0014]
Next, a device simulation was performed on the semiconductor device shown in FIG. This simulation result is shown by a dotted line in FIG. Here, in the semiconductor device shown in FIG. 13, a gate insulating film 26 having a high relative dielectric constant (k = 40) is used. The equivalent oxide film thickness of the gate insulating film 26 is 1.5 nm. The physical thickness of the gate insulating film 26 is about 10 times the thickness of the gate insulating film 25 (FIG. 12) having a relative dielectric constant k of 3.9. The other structure in FIG. 13 is the same as the semiconductor device shown in FIG.
As shown in FIG. 14, it was found that when a material having a high relative dielectric constant was used for the gate insulating film, the short channel effect was larger than when a material having a low relative dielectric constant was used.
[0015]
[Non-patent document 1]
T. Y. Chan et al. , "The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling", IEDM, 1987, p. 718-721
[0016]
[Problems to be solved by the invention]
As described above, if the relative dielectric constant of the gate insulating film is increased in order to reduce the gate-drain tunnel current, there is a problem that the short channel effect becomes large and miniaturization becomes difficult. As described above, when the relative dielectric constant of the gate insulating film is increased, the short-channel effect is increased because the electric field from the drain is absorbed by the gate insulating film, which acts on the source end, and the height of the barrier is reduced. May be reduced. Although this effect exists regardless of the relative dielectric constant of the gate insulating film, it can be seen from the results of device simulation that the effect becomes more significant as the relative dielectric constant increases.
[0017]
In addition, when a gate insulating film having a high relative dielectric constant is formed directly over the channel, an interface state is easily formed at an interface between the gate insulating film and the substrate, so that carrier mobility is reduced and transistor on-current is deteriorated. There was a problem of doing.
In addition, since the gate insulating film having a high relative dielectric constant easily reacts with silicon, which is a main component of the semiconductor substrate, there is a problem that heat treatment stability in a normal semiconductor manufacturing process is low.
Further, there is a problem that the dopant contained in the gate electrode easily diffuses into the semiconductor substrate via the gate insulating film having a high relative dielectric constant.
[0018]
The present invention has been made to solve the above-mentioned conventional problems, and has as its object to reduce GIDL, which increases due to the influence of a high electric field inside a semiconductor device. Another object of the present invention is to reduce the short channel effect that increases when the relative dielectric constant of the gate insulating film is increased.
[0019]
[Means for solving the problem]
A semiconductor device according to the present invention includes a channel region formed on a surface layer of a substrate;
Source / drain regions formed on both sides of the channel region;
An insulating interface layer having a first relative dielectric constant and formed on the channel region;
A gate insulating film having a second dielectric constant higher than the first dielectric constant and formed on the insulating interface layer;
A gate electrode formed on the gate insulating film;
It is characterized by having.
[0020]
The semiconductor device according to the present invention is characterized in that the side surfaces of the insulating interface layer and the gate insulating film are inside the side surfaces of the gate electrode.
[0021]
In the semiconductor device according to the present invention, a part of the source / drain region is formed inside a side surface of the gate electrode,
The insulating interface layer and the side surface of the gate insulating film are located on a part of the source / drain region.
[0022]
The semiconductor device according to the present invention further includes a second insulating interface layer having a dielectric constant lower than the second dielectric constant between the gate insulating film and the gate electrode. It is assumed that.
[0023]
The semiconductor device according to the present invention is characterized in that the side surfaces of the insulating interface layer, the gate insulating film, and the second insulating interface layer are inside the side surfaces of the gate electrode. is there.
[0024]
In the semiconductor device according to the present invention, a part of the source / drain region is formed inside a side surface of the gate electrode,
Side surfaces of the insulating interface layer, the gate insulating film, and the second insulating interface layer are located on a part of the source / drain region.
[0025]
The semiconductor device according to the present invention has a relative dielectric constant lower than the second relative dielectric constant and further includes a side insulating film covering at least a side surface of the gate insulating film. .
[0026]
A semiconductor device according to the present invention includes a channel region formed on a surface layer of a substrate;
Source / drain regions formed on both sides of the channel region;
A gate insulating film having a relative dielectric constant of 30 or more and formed on the channel region;
A gate electrode formed on the gate insulating film;
With
The side surface of the gate insulating film is inside the side surface of the gate electrode.
[0027]
In the semiconductor device according to the present invention, a part of the source / drain region is formed inside a side surface of the gate electrode,
A side surface of the gate insulating film is located on a part of the source / drain region.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts have the same reference characters allotted, and description thereof may be simplified or omitted.
[0029]
Embodiment 1 FIG.
FIG. 1 is a sectional view illustrating a semiconductor device according to a first embodiment of the present invention.
As shown in FIG. 1, a channel region 12 is formed in a surface layer of a well region 11 formed in a semiconductor substrate 1 such as a silicon substrate, and a source region 3 and a drain region 4 are formed on both sides of the channel region 12. I have. A gate insulating film 21 having a high relative dielectric constant (k = 40) is formed on the channel region 12, and the gate electrode 5 is formed on the gate insulating film 21.
Part of the source / drain regions 3 and 4 (hereinafter referred to as “overlap region A”) overlaps with the gate electrode 5. That is, the boundary between the channel region 12 and the source / drain regions 3 and 4 is located inside the side surface of the gate electrode 5. The side surface of the gate insulating film 21 is inside the side surface of the gate electrode 5. Specifically, the side surface of the gate insulating film 21 enters the inside of the side surface of the gate electrode 5 by the offset amount B, and is located on the overlap region A.
[0030]
Device simulation was performed for each of the semiconductor devices shown in FIG. 1 having an offset amount B of 10 nm and 15 nm. FIG. 2 shows the simulation result as a gate voltage-drain current characteristic. FIG. 2 is a diagram for explaining a device simulation result of the semiconductor device shown in FIG. In FIG. ₂ A simulation result of a conventional semiconductor device (see FIG. 12) using (dielectric constant k = 3.9) as a gate insulating film 25 and an offset using a gate insulating film 26 having a high relative dielectric constant (k = 40). Simulation results of a conventional semiconductor device with the amount B = 0 nm (see FIG. 13) are also shown as a comparative example of the first embodiment.
Here, the conditions of the simulation parameters are: drain voltage Vd = gate voltage Vg = 1.0 V, source voltage Vs = substrate bias voltage Vsub = 0 V, length of overlap region A = 10 nm, oxide film of gate insulating film 21 The converted film thickness was 1.5 nm, and the relative dielectric constant k of the gate insulating film 21 was 40.
[0031]
First, the simulation result of the comparative example will be described.
As shown in FIG. 2, in the case of the semiconductor device shown in FIG. 12, the drain current Id at the gate voltage Vg = 0 V, that is, the off current Ioff is not determined by the subthreshold characteristic but is increased by the influence of GIDL. . Therefore, it is apparent that the off-state current Ioff cannot be reduced even if the threshold voltage is increased, and it is difficult to further reduce the off-state current Ioff.
In the case of the semiconductor device shown in FIG. 13, the gate electric field is applied to the overlap region A of the drain region 4 because the gate insulating film 26 having a high relative dielectric constant covers the entire overlap region A of the drain region 4. Concentration tends to occur, and the effect of GIDL is further increased as compared with the case of the semiconductor device shown in FIG. 12, and the off-state current Ioff increases.
[0032]
Next, the simulation result of the semiconductor device according to the first embodiment, that is, the case where the offset amount B of the gate insulating film 21 is 10 nm and 15 nm will be described.
As described above, since the length of the overlap region A = 10 nm, when the offset amount B = 10 nm, the side surface (offset position) of the gate insulating film 21 and the end portions of the source / drain regions 3 and 4 are one. It is in the state of doing. When the offset amount B is 15 nm, a part of the channel region 12 (near the end) is not covered with the gate insulating film 21.
As shown in FIG. 2, since the gate insulating film 21 having a high relative dielectric constant (k = 40) has an offset structure (offset amount B = 10 nm, 15 nm), the influence of GIDL is greatly reduced, Accordingly, the off current Ioff is reduced. The effect of reducing the off current Ioff is more remarkable when B = 15 nm than when the offset amount B = 10 nm. That is, the off current Ioff can be further reduced by increasing the offset amount B of the gate insulating film 21.
[0033]
FIG. 3 shows a result of the simulation calculation shown in FIG. 2 displayed linearly so that the driving capability of the transistor can be understood.
As shown in FIG. 3, the on-current Ion when the offset amount B = 10 nm is substantially equal to the on-current Ion of the conventional semiconductor device (see FIGS. 12 and 13). However, the on-state current Ion when the offset amount B = 15 nm is smaller than the on-state current Ion of the conventional semiconductor device, and it has been found that the driving capability of the transistor deteriorates. This is because the ON current Ion is affected by the gate electric field on the channel region 12. That is, as described above, in the semiconductor device having the offset amount B = 15 nm, a part of the channel region 12 is not covered with the gate insulating film 21 and the gate electric field does not sufficiently act on the part.
Therefore, it is necessary to set the offset amount B of the gate insulating film 21 having a high relative dielectric constant (k = 40) from the viewpoint of both the off current Ioff and the on current Ion. From both viewpoints, for example, when the length of the overlap region A is 10 nm, the offset amount B is preferably larger than 0 nm and 10 nm or less.
[0034]
As described above, in the semiconductor device according to the first embodiment, the gate insulating film 21 having a high relative dielectric constant is formed on the semiconductor substrate 1, and the gate electrode 5 is formed on the gate insulating film 21. Then, the side surface of the gate insulating film 21 enters the inside of the side surface of the gate electrode 5 and is located on the overlap region A of the source / drain regions 3 and 4 overlapping the gate electrode 5.
Therefore, GIDL, which increases due to the influence of a high electric field inside the semiconductor device, can be reduced.
[0035]
In the first embodiment, since the length of the overlap region A is 10 nm, the upper limit of the offset amount B is set to 10 nm. The length of the overlap region A is not limited to 10 nm and may be changed as appropriate. When the range of the offset amount B is generalized and expressed, the range of the offset amount B is larger than 0 nm and equal to or less than the length of the overlap region A (the same applies to Embodiments 3 and 5 described later). ).
[0036]
Further, in the first embodiment, the case where the relative dielectric constant k of the gate insulating film 21 is 40 has been described. However, the present invention is not limited to this. For example, the relative dielectric constant k may be 30 or more.
[0037]
Embodiment 2 FIG.
FIG. 4 is a sectional view illustrating a semiconductor device according to a second embodiment of the present invention.
As shown in FIG. 4, a channel region 12 is formed in a surface layer of a well region 11 formed in a semiconductor substrate 1 such as a silicon substrate, and a source region 3 and a drain region 4 are formed on both sides of the channel region 12. I have. An insulating interface layer 22 having a relative permittivity k = 3.9 is formed on the channel region 12, and a relative permittivity (k = higher than the relative permittivity of the insulating interface layer 22) on the insulating interface layer 22. The gate insulating film 21 having the pattern 40) is formed, and the gate electrode 5 is formed on the gate insulating film 21. Here, the insulating interface layer 22 is made of, for example, SiO 2 ₂ Film, SiN film, HfSiOx film, ZrSiOx film, AlSiOx film and the like.
As in the first embodiment, the overlap region A, which is a part of the source / drain regions 3 and 4, overlaps with the gate electrode 5. That is, the boundary between the channel region 12 and the source / drain regions 3 and 4 is located inside the side surface of the gate electrode 5.
Note that the semiconductor device according to the second embodiment does not have an offset structure in which the side surface of the gate insulating film enters inside the side surface of the gate electrode 5 as in the first embodiment.
[0038]
A device simulation was performed on the semiconductor device illustrated in FIG. FIG. 5 shows the simulation results as gate length-threshold voltage characteristics. FIG. 5 is a diagram for explaining a device simulation result of the semiconductor device shown in FIG. In FIG. ₂ A simulation result of a conventional semiconductor device (see FIG. 12) using (dielectric constant k = 3.9) as the gate insulating film 25 and insulation using the gate insulating film 26 having a high relative dielectric constant (k = 40). Simulation results of a conventional semiconductor device having no conductive interface layer (see FIG. 13) are also shown as a comparative example of the second embodiment.
Here, the conditions of the simulation parameters are, as in the first embodiment, the drain voltage Vd = the gate voltage Vg = 1.0 V, the source voltage Vs = the substrate bias voltage Vsub = 0 V, and the length of the overlap region A = 10 nm. The equivalent oxide thickness of the gate insulating film 21 was 1.5 nm, and the relative dielectric constant k of the gate insulating film 21 was 40.
[0039]
As shown in FIG. 5, in the semiconductor device according to the second embodiment in which the gate insulating film 21 having a high relative dielectric constant (k = 40) is formed via the insulating interface layer 22, the insulating interface layer 22 is formed. The increase in the short channel effect can be reduced as compared with a conventional semiconductor device without such a device (see FIG. 13).
The reason that increasing the relative dielectric constant of the gate insulating film increases the short-channel effect is that the electric field from the drain is absorbed by the gate insulating film, and this acts on the source end to lower the height of the barrier. As described above, this effect exists regardless of the relative dielectric constant of the gate insulating film, and becomes more remarkable as the relative dielectric constant increases.
However, in the second embodiment, even when the relative dielectric constant of the gate insulating film 21 is high, an increase in the short channel effect can be suppressed. This is formed between the gate insulating film 21 having a high relative dielectric constant (k = 40) and the silicon substrate 1 and has an insulating property having a lower relative dielectric constant (k = 3.9) than the gate insulating film 21. This is because the shield effect of the interface layer 22 makes it difficult for the gate insulating film 21 to absorb the electric field from the drain region 4, which can be seen from the above-described simulation results.
[0040]
As described above, in the semiconductor device according to the second embodiment, the insulating interface layer 22 is formed on the semiconductor substrate 1, and the insulating interface layer 22 has a higher dielectric constant than the relative permittivity of the interface layer 22. A gate insulating film 21 having a dielectric constant was formed, and a gate electrode 5 was formed on the gate insulating film 21. Therefore, the short channel effect, which is increased by increasing the relative dielectric constant of the gate insulating film, can be reduced by the shielding effect of the insulating interface layer 22.
[0041]
In the second embodiment, since the gate insulating film 21 is formed via the insulating interface layer 22, the following effects can be further obtained.
As described above, when a gate insulating film having a high relative dielectric constant is formed directly on the channel region, an interface state is easily formed at an interface between the gate insulating film and the semiconductor substrate, thereby reducing carrier mobility. As a result, the ON current of the transistor deteriorates. Further, the gate insulating film having a high relative dielectric constant relatively easily undergoes a thermochemical reaction with silicon which is a main component of the semiconductor substrate, has low heat treatment stability in a normal semiconductor manufacturing process, and further has a dopant contained in the gate electrode 5. Is easily diffused into the semiconductor substrate via the gate insulating film having a high relative dielectric constant.
Therefore, an insulating interface layer 22 that hardly forms an interface state, has excellent thermal stability, and suppresses diffusion of a dopant is interposed between the gate insulating film 21 having a high relative dielectric constant and the semiconductor substrate 1. Thus, a semiconductor device (transistor) having excellent thermal stability can be obtained without deteriorating the ON current Ion of the transistor.
[0042]
In the second embodiment, the relative dielectric constant k of the insulating interface layer 22 has been described as 3.9. However, the present invention is not limited to this, as long as it is smaller than the relative dielectric constant (k = 40) of the gate insulating film 21. Good.
Further, the thickness of the insulating interface layer 22 may be at least larger than 0, and the larger the thickness, the greater the shielding effect is obtained, and the increase in the short channel effect can be further suppressed.
Further, the gate insulating film 21 is a film having a relative dielectric constant k = 40, but is not limited thereto, and may be a high dielectric constant film having a relative dielectric constant higher than the relative dielectric constant of the insulating interface layer 22. . For example, Al ₂ O ₃ Membrane, ZrO ₂ Membrane, HfO ₂ Film, HfSiOx film, ZrSiOx film, Y ₂ O ₃ Membrane, La ₂ O ₃ A film, a PrOx film, or the like can be used.
[0043]
Further, in the second embodiment, nothing is formed on the sides of the insulating interface layer 22, the gate insulating film 21, and the gate electrode 5, but the relative dielectric constant lower than the relative dielectric constant of the gate insulating film 21 is reduced. May be formed. In this case, the gate insulating film 21 may be formed so as to cover at least the side surface thereof, and the same effect as that of the second embodiment can be obtained (the same applies to the later-described embodiment 3-5).
[0044]
Embodiment 3 FIG.
FIG. 6 is a sectional view illustrating a semiconductor device according to a third embodiment of the present invention.
The semiconductor device according to the third embodiment shown in FIG. 6 is different from the semiconductor device according to the second embodiment (see FIG. 4) in that the side surfaces of the insulating interface layer 22 and the gate insulating film 21 are different from the side surfaces of the gate electrode 5. Is also inside. More specifically, the side surfaces of the insulating interface layer 22 and the gate insulating film 21 enter the inside of the side surface of the gate electrode 5 by the offset amount B, and are located on the overlap region A.
The other components are the same as those of the second embodiment, and therefore, detailed description of the third embodiment will be omitted.
[0045]
Device simulation was performed on the semiconductor device shown in FIG. 6 having an offset amount B = 10 nm. FIG. 7 shows the simulation result as gate voltage-drain current characteristics. FIG. 7 is a diagram for explaining a device simulation result of the semiconductor device shown in FIG. In FIG. ₂ A simulation result of a conventional semiconductor device (see FIG. 12) using (dielectric constant k = 3.9) as a gate insulating film 25 and an offset using a gate insulating film 26 having a high relative dielectric constant (k = 40). Simulation results of a conventional semiconductor device with the amount B = 0 nm (see FIG. 13) are also shown as a comparative example of the third embodiment.
Here, as in the second embodiment, the conditions of the simulation parameters are as follows: drain voltage Vd = gate voltage Vg = 1.0 V, source voltage Vs = substrate bias voltage Vsub = 0 V, length of overlap region A = 10 nm The equivalent oxide thickness of the gate insulating film 21 was 1.5 nm, and the relative dielectric constant k of the gate insulating film 21 was 40.
[0046]
First, the simulation result of the comparative example will be described.
In the case of the semiconductor device illustrated in FIG. 12, as described in Embodiment 1, the off-state current Ioff is not determined by the sub-threshold characteristic and is high under the influence of GIDL, and it is difficult to reduce the off-state current Ioff. It is.
Further, in the case of the semiconductor device shown in FIG. 13, as described in the first embodiment, the gate electric field tends to concentrate on the overlap region A of the drain region 4, which is greater than in the case of the semiconductor device shown in FIG. , And GIDL increase, and the off-current Ioff increases.
[0047]
Next, simulation results of the semiconductor device according to the third embodiment will be described.
As described above, since the length of the overlap region A = 10 nm and the offset amount B = 10 nm, the side surfaces (offset positions) of the insulating interface layer 22 and the gate insulating film 21 and the end portions of the source / drain regions 3 and 4. Are in agreement with each other.
As shown in FIG. 7, the insulating interface layer 22 and the gate insulating film 21 having a high relative dielectric constant (k = 40) have an offset structure (offset amount B = 10 nm). As in the case, the effect of the GIDL is greatly reduced, and the off-current Ioff is accordingly reduced.
[0048]
FIG. 8 shows the simulation result shown in FIG. 7 in a linear display so that the driving capability of the transistor can be understood.
As shown in FIG. 8, as in the first embodiment, the on-state current Ion of the conventional semiconductor device (see FIGS. 12 and 13) when the offset amount B = 10 nm is almost equal to the on-state current Ion of the conventional semiconductor device (see FIGS. 12 and 13). Equivalent values are obtained.
[0049]
Also in the third embodiment, as in the first embodiment, the offset amount B of the gate insulating film 21 having a high relative dielectric constant (k = 40) is set from the viewpoint of both the off current Ioff and the on current Ion. There is a need to. From both viewpoints, for example, when the length of the overlap region A is 10 nm, the offset amount B is preferably larger than 0 nm and 10 nm or less.
[0050]
Next, the influence on the short channel effect will be described.
FIG. 9 shows the above simulation results as gate length-threshold voltage characteristics. In FIG. ₂ A simulation result of a conventional semiconductor device (see FIG. 12) using (dielectric constant k = 3.9) as the gate insulating film 25 and insulation using the gate insulating film 26 having a high relative dielectric constant (k = 40). Simulation results of a conventional semiconductor device having no conductive interface layer (see FIG. 13) are also shown as a comparative example of the third embodiment.
As shown in FIG. 9, similarly to the second embodiment, a semiconductor device according to the third embodiment in which a gate insulating film 21 having a high relative dielectric constant (k = 40) is formed via an insulating interface layer 22 is provided. As compared with the conventional semiconductor device in which the gate insulating film 26 having a high relative dielectric constant (k = 40) is formed directly on a semiconductor substrate (see FIG. 13), an increase in the short channel effect can be reduced. .
[0051]
As described above, in the semiconductor device according to the third embodiment, the insulating interface layer 22 is formed on the semiconductor substrate 1, and the insulating interface layer 22 has a higher dielectric constant than the relative dielectric constant of the interface layer 22. A gate insulating film 21 having a dielectric constant was formed, and a gate electrode 5 was formed on the gate insulating film 21. Therefore, the same effect as in the second embodiment can be obtained.
Further, in the third embodiment, the side surfaces of the insulating interface layer 22 and the gate insulating film 21 are located inside the side surface of the gate electrode 5 by the offset amount B, and overlap the gate electrode 5. It was arranged on the overlap area A of 3,4. Therefore, GIDL, which increases due to the influence of a high electric field inside the semiconductor device, can be reduced.
[0052]
Embodiment 4 FIG.
FIG. 10 is a sectional view illustrating a semiconductor device according to a fourth embodiment of the present invention.
The semiconductor device according to the fourth embodiment shown in FIG. 10 is different from the semiconductor device according to the second embodiment (see FIG. 4) in that the relative dielectric constant of the gate insulating film 21 is provided between the gate insulating film 21 and the gate electrode 5. The insulating interface layer 23 having a relative dielectric constant (k = 3.9) lower than the dielectric constant (k = 40) is interposed.
The other components are the same as those in the second embodiment, and therefore, detailed descriptions thereof will be omitted in the fourth embodiment.
[0053]
Device simulation was performed on the semiconductor device shown in FIG. This simulation result was similar to the simulation result of the semiconductor device according to the second embodiment (see FIG. 5).
[0054]
As described above, in the semiconductor device according to the fourth embodiment, the insulating interface layer (first insulating interface layer) 22 is formed on the semiconductor device 1, and the interface layer is formed on the insulating interface layer 22. A gate insulating film 21 having a relative dielectric constant (k = 40) higher than the relative dielectric constant (k = 3.9) of the gate insulating film 21 is formed on the gate insulating film 21 and lower than the relative dielectric constant of the gate insulating film 21. An insulating interface layer (second insulating interface layer) 23 having a relative dielectric constant (k = 3.9) was formed, and the gate electrode 5 was formed on the insulating interface layer 23. Therefore, the same effect as in the second embodiment can be obtained.
[0055]
According to the fourth embodiment, the relative dielectric constant k of the two insulating interface layers 22 and 23 is set to 3.9. However, the present invention is not limited to this, as long as the relative dielectric constant of the gate insulating film 21 is lower than 3.9. Good. Further, the relative dielectric constants of the two insulating interface layers 22 and 23 may be different from each other.
[0056]
Embodiment 5 FIG.
FIG. 11 is a sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention.
The semiconductor device according to the fifth embodiment shown in FIG. 11 is different from the semiconductor device according to the fourth embodiment (see FIG. 10) in that the side surfaces of the insulating interface layers 22 and 23 and the gate insulating film 21 correspond to the gate electrode 5. It is inside the side. In detail, the side surfaces of the insulating interface layers 22 and 23 and the gate insulating film 21 are located inside the side surface of the gate electrode 5 by the offset amount B and on the overlap region A.
[0057]
Device simulation was performed on the semiconductor device shown in FIG. 11 having an offset amount B = 10 nm. The simulation result was similar to the simulation result of the semiconductor device according to the third embodiment (see FIGS. 7 to 9).
[0058]
As described above, in the semiconductor device according to the fifth embodiment, the insulating interface layer 22 is formed on the semiconductor device 1, and the relative permittivity (k = 3) of the interface layer 22 is formed on the insulating interface layer 22. .9) is formed on the gate insulating film 21 having a relative dielectric constant (k = 40) higher than the relative dielectric constant of the gate insulating film 21 (k = 3.9). ) Was formed, and the gate electrode 5 was formed on the insulating interface layer 23. Then, the side surfaces of the insulating interface layers 22 and 23 and the gate insulating film 21 enter the inside of the side surface of the gate electrode 5 and overlap the source / drain regions 3 and 4 overlapping the gate electrode 5. It was located in. Therefore. The same effect as in the third embodiment can be obtained.
[0059]
【The invention's effect】
According to the present invention, it is possible to reduce GIDL that increases due to the influence of a high electric field inside a semiconductor device. In addition, when the relative dielectric constant of the gate insulating film is increased, a short channel effect which is increased can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram for describing device simulation results (gate voltage-drain current characteristics) of the semiconductor device shown in FIG.
FIG. 3 is a diagram in which the device simulation results shown in FIG. 2 are linearly displayed.
FIG. 4 is a sectional view illustrating a semiconductor device according to a second embodiment of the present invention;
FIG. 5 is a diagram for explaining a device simulation result (gate length-threshold voltage characteristic) of the semiconductor device shown in FIG. 4;
FIG. 6 is a sectional view for illustrating a semiconductor device according to a third embodiment of the present invention;
7 is a diagram for describing a device simulation result (gate voltage-drain current characteristics) of the semiconductor device shown in FIG. 6;
8 is a diagram linearly displaying the device simulation results shown in FIG.
9 is a diagram for explaining a device simulation result (gate length-threshold voltage characteristic) of the semiconductor device shown in FIG. 6;
FIG. 10 is a sectional view illustrating a semiconductor device according to a fourth embodiment of the present invention;
FIG. 11 is a sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention;
FIG. 12 is a cross-sectional view illustrating a conventional semiconductor device.
FIG. 13 is a cross-sectional view illustrating a conventional semiconductor device using a high dielectric constant film.
FIG. 14 is a diagram for explaining a device simulation result (gate length-threshold voltage characteristic) of the semiconductor device shown in FIGS. 12 and 13;
[Explanation of symbols]
1 semiconductor substrate (silicon substrate)
3 Source area
4 Drain region
5 Gate electrode
11 well area
12 channel area
21 Gate insulating film
22 Insulating interface layer
23 Insulating interface layer

Claims (9)

A channel region formed in a surface layer of the substrate;
Source / drain regions formed on both sides of the channel region;
An insulating interface layer having a first relative dielectric constant and formed on the channel region;
A gate insulating film having a second dielectric constant higher than the first dielectric constant and formed on the insulating interface layer;
A gate electrode formed on the gate insulating film;
A semiconductor device comprising: The semiconductor device according to claim 1,
A semiconductor device, wherein the side surfaces of the insulating interface layer and the gate insulating film are inside the side surfaces of the gate electrode. The semiconductor device according to claim 2,
A part of the source / drain region is formed inside a side surface of the gate electrode,
A semiconductor device, wherein a side surface of the insulating interface layer and a side surface of the gate insulating film are located on a part of the source / drain region. The semiconductor device according to claim 1,
A semiconductor device, further comprising a second insulating interface layer having a relative dielectric constant lower than the second relative dielectric constant between the gate insulating film and the gate electrode. The semiconductor device according to claim 4,
A semiconductor device, wherein the side surfaces of the insulating interface layer, the gate insulating film, and the second insulating interface layer are inside the side surfaces of the gate electrode. The semiconductor device according to claim 5,
A part of the source / drain region is formed inside a side surface of the gate electrode,
A semiconductor device, wherein side surfaces of the insulating interface layer, the gate insulating film, and the second insulating interface layer are located on a part of the source / drain region. The semiconductor device according to claim 1, wherein
A semiconductor device, further comprising a side insulating film having a relative dielectric constant lower than the second relative dielectric constant and covering at least a side surface of the gate insulating film. A channel region formed in a surface layer of the substrate;
Source / drain regions formed on both sides of the channel region;
A gate insulating film having a relative dielectric constant of 30 or more and formed on the channel region;
A gate electrode formed on the gate insulating film;
With
A semiconductor device, wherein a side surface of the gate insulating film is inside a side surface of the gate electrode. The semiconductor device according to claim 8,
A part of the source / drain region is formed inside a side surface of the gate electrode,
A semiconductor device, wherein a side surface of the gate insulating film is located on a part of the source / drain region.

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