JP2004185696A - Method and device for measuring jitters - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and a method for measuring jitters, capable of measuring jitters for the reproducing signal of disk recording media of various speeds by one device. <P>SOLUTION: This device is comprised of an A/D converter for converting the reproducing signal of a disk recording medium into a digital signal, an equalizer for amplifying the specific frequency component of the digital signal converted and output from the A/D converter, a phase difference generation circuit for generating and outputting a phase difference between timing at which the output signal of the equalizer crosses a predetermined threshold value and a clock, a phase synchronizing circuit for using the phase difference output of the phase difference generation circuit as the phase error input signal of a phase synchronous loop, and applying phase synchronization to reproduce a reading clock, and a standard deviation calculation circuit for calculating standard deviation from the phase difference output of the phase difference generation circuit. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a jitter measuring device and a jitter measuring method, and more particularly to an improvement in a device and a measuring method for measuring jitter at a time interval in a reproduction signal of a disk recording medium such as an optical disk or a magnetic disk.
[0002]
[Prior art]
One of the items for evaluating the characteristics of a disk recording device such as a DVD is a jitter representing the magnitude of variation in time intervals in a reproduction signal.
[0003]
FIG. 6 is a block diagram showing an example of a conventional jitter measuring device.
For example, a reproduction signal of an optical disk (hereinafter, referred to as an RF signal) is input to the input amplifier 10. An AGC amplifier is often used as the input amplifier 10.
[0004]
An output signal of the input amplifier 10 is input to one input terminal of a comparator 12 via an equalizer circuit 11. The equalizer circuit 11 has a function of amplifying only a specific frequency component of the RF signal. By the action of the equalizer, the amplitude of only a narrow pulse is amplified, and as a result, signal jitter can be suppressed.
[0005]
FIG. 7 is an example of frequency characteristics of an equalizer used in an optical disc. Although the amplification factor at the frequency f ₀ is (gain) G ₀ is the largest, since the amplification factor G ₀ at f ₀ by a user different amplification factor G ₀ is used as a measuring instrument is required to be variable. The gain G ₀ of the equalizer circuit 11 is set by the gain setting holding unit 12.
[0006]
The comparator 13 converts the output signal of the equalizer circuit 11 into a binary signal, and outputs a threshold voltage _Vth for binarizing the output signal of the equalizer circuit 11 to the other input terminal. Source 14 is connected.
[0007]
The output signal of the comparator 13 is directly input to one input terminal of the phase difference measuring circuit 16 and is output from the other side of the phase difference measuring circuit 16 via the PLL circuit 15 which reproduces a read clock synchronized with the binarized signal. Input to the input terminal. The phase difference measuring circuit 16 measures the phase difference between the binarized signal edge and the clock signal. Here, it is desirable that the phase difference between the edge of the binarized signal and the clock signal is ideally always constant, but actually, variation (jitter) tends to occur.
[0008]
The standard deviation measuring circuit 17 measures the standard deviation σ as an index representing the jitter of the phase difference data based on the measurement data of the phase difference measuring circuit 16.
[0009]
The output unit 18 outputs the measurement result of the standard deviation σ in the standard deviation measurement circuit 17 as a numerical value, outputs the result with a panel meter, or converts and outputs the voltage information.
[0010]
FIG. 8 is a waveform chart in each part of FIG.
S1 is an RF signal input to the input amplifier 10.
S2 is an output signal of the equalizer circuit 11, and the amplitude of only a narrow pulse is amplified.
[0011]
S3 is an output signal of the comparator 13, which is obtained by binarizing the output signal S2 of the equalizer circuit 11 with a predetermined threshold voltage _Vth . This binarized signal S3 is generated for clock recovery in the PLL circuit 15 and for measuring the phase difference between the recovered clock and both edges.
[0012]
S4 is a read clock signal reproduced by the PLL circuit 15, and FIG. 8 shows only the rising edge of the clock for simplification of the drawing.
S5 is a voltage signal obtained by converting the phase difference between the binary signal S3 and the clock signal S4 into a voltage amount proportional to the phase difference. The voltage of the voltage signal S5 is updated at each edge of the binarized signal S3, and the voltage is held until the next edge.
[0013]
The jitter measuring apparatus is for obtaining a phase difference between an RF signal and a reproduced clock. The conventional equalizer circuit 11 is an analog circuit in which an OP amplifier and a delay line and R, L, and C passive components are combined. Was composed.
[0014]
On the other hand, the standard deviation measuring circuit 17 converts the voltage signal S5 into a digital signal with an A / D converter and obtains the digital signal by digital operation, or converts the voltage signal S5 into an effective value using an effective value conversion circuit, for example, an RMS-DC conversion IC. The conversion is required.
[0015]
An example of the transfer function of the equalizer circuit 11 having a frequency characteristic as shown in FIG.
y (t) = x (t) −k {x (t + nτ) + x (t−nτ)} / 2 (1)
Where x (t): input, y (t): output, k: constant, n: any integer.
Considering that the characteristic of the equation (1) is configured by an analog circuit, since τ is a delay of a certain time, it is necessary to use a delay line corresponding to the delay time τ. Specifically, τ is the value of the read clock cycle.
[0017]
[Problems to be solved by the invention]
Incidentally, the frequency characteristics of the equalizer circuit 11 and the like greatly affect the measurement result of the jitter. For example, the equalizer circuit 11 is configured by the delay line and the analog circuit such as R, L, and C as described above. Therefore, variations in component constants cannot be ignored.
[0018]
Therefore, in order to correct these variations, conventionally, many adjustment points such as a variable delay line and a variable capacitor are provided, and an equalizer is adjusted to a desired characteristic.
[0019]
Also, in order to measure the jitter of the reproduction signal on various types of disk recording media having different speeds with one jitter measuring device, it is necessary to incorporate an equalizer circuit having predetermined characteristics corresponding to each speed, The circuit scale of the entire device becomes large. Specifically, an equalizer 11n having a delay line for realizing a delay time τ corresponding to a clock cycle for each speed is required.
[0020]
The present invention focuses on such a problem, and an object of the present invention is to provide a jitter measuring apparatus and a measuring method which can perform jitter measurement on reproduced signals of a disk recording medium of various speeds by one unit. .
[0021]
[Means for Solving the Problems]
The invention of claim 1, which achieves such an object,
An A / D converter for converting a reproduction signal of a disk recording medium into a digital signal;
An equalizer that amplifies a specific frequency component of a digital signal converted and output from the A / D converter;
A phase difference generation circuit that generates and outputs a phase difference between a timing and a clock at which the output signal of the equalizer crosses a predetermined threshold;
A phase synchronization circuit that reproduces a phase-locked read clock using the phase difference output of the phase difference generation circuit as a phase error input signal of a phase locked loop and supplies the clock to each unit;
A standard deviation calculation circuit for calculating a standard deviation from the phase difference output of the phase difference generation circuit,
And a jitter measuring device comprising:
[0022]
According to a second aspect of the present invention, in the jitter measuring apparatus according to the first aspect,
The equalizer includes a plurality of serially connected delay factors that generate a delay time corresponding to a clock cycle, a plurality of tap coefficient setting means connected to a connection point of these delay factors, and an arbitrary tap coefficient that can be set. The FIR filter includes an adding means for adding the output of the setting means.
[0023]
According to a third aspect of the present invention, in the jitter measuring apparatus according to the first aspect,
The phase difference generating circuit generates and outputs phase difference data p (k) represented by the following equation.
_{p (k) = {y (} k) -V th} · T / {y (k) -y (k-1)}
y (k): output signal V _{th of the} equalizer circuit: threshold voltage y (k−1), y (k): temporally continuous sample data T: sampling period
Thus, jitter measurement of RF signals at various speeds can be performed by one device.
[0025]
The invention of claim 4 is
Converting the reproduction signal of the disk recording medium into a digital signal;
Amplifying a specific frequency component of the converted digital signal;
A step of generating and outputting a phase difference between a timing and a clock at which the digital signal crosses a predetermined threshold from the amplified output of the specific frequency component,
A step of reproducing a phase-synchronized read clock from the phase difference output and supplying the read clock to each unit;
Calculating the standard deviation from the phase difference output,
And a jitter measuring method.
[0026]
According to such a jitter measuring method, the jitter of the phase difference can be measured from the digital signal.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an example of an embodiment of the present invention.
For example, a reproduction signal (RF signal) of a disk recording medium such as an optical disk is input to the input amplifier 20. As the input amplifier 20, an AGC amplifier is generally used.
[0028]
The output signal of the input amplifier 20 is input to the A / D converter 21 and is converted into a digital signal. As the A / D converter 21, for example, a flash type having an 8-bit output configuration at 50 megasamples / second is used. The A / D converter 21 performs sampling based on a read clock to be reproduced.
[0029]
The equalizer circuit 22 has a function of amplifying only a specific frequency component of the RF signal, similarly to the equalizer circuit 11 of FIG. 6, and has a characteristic as shown in FIG. As the equalizer circuit 22 in FIG. 1, a general FIR filter as shown in FIG. 2 is used. D in FIG. 2 represents a delay factor for one cycle of the sampling clock. The equalizer circuit 22 operates based on the timing of the read clock to be reproduced, and the gain _G0 is set by the gain setting holding unit 23.
[0030]
The output signal of the equalizer circuit 22 is input to the phase difference generation circuit 24, and the threshold voltage data _Vth output from the threshold voltage setting holding unit 25 is also input to the phase difference generation circuit 24. The phase difference generation circuit 24 generates a phase difference signal between the timing at which the output signal of the equalizer circuit 22 crosses the threshold voltage data _Vth and the read clock. The output signal of the phase difference generation circuit 24 is input to the PLL circuit 26 and also to the standard deviation measurement circuit 27.
[0031]
The PLL circuit 26 reads the output signal of the phase difference generation circuit 24 as a phase error input signal of the phase locked loop and applies a phase lock to the clock to reproduce the read clock. The read clock reproduced by the PLL circuit 26 is input as a timing signal to the A / D converter 21, the equalizer circuit 22, and the phase difference generating circuit 24.
[0032]
The standard deviation calculation circuit 27 calculates a standard deviation σ as an index representing the jitter of the phase difference data based on the output signal of the phase difference generation circuit 24.
[0033]
The output unit 28 outputs a calculation result of the standard deviation σ in the standard deviation calculation circuit 24 as a numerical value, a panel meter, or converts and outputs voltage information.
[0034]
FIG. 3 is a waveform chart in each part of FIG.
S1 is an RF signal input to the input amplifier 10. This RF signal is digitized by the PLL clock in the A / D converter 21 and is converted into discrete data x (k).
S2 is an output signal of the equalizer circuit 22, which becomes y (k) as a result of signal processing.
[0035]
S3 is a read clock signal reproduced by the PLL circuit 26. This read clock signal is input to each unit as a timing clock.
[0036]
FIG. 4 is an explanatory diagram of a measuring method of the phase difference data p (k), and is an enlarged view of the output signal y (k) of the equalizer circuit 22. A method for measuring phase difference data will be described.
Of the output signals of the equalizer circuit 22, only two samples that cross the threshold voltage _Vth when binarization is assumed will be noted. y (k−1) and y (k) are two samples that are temporally continuous. The phase difference data p (k) corresponds to the time from the time crossing the threshold voltage _Vth to the time y (k) when linearly interpolating y (k-1) and y (k). Thus, the phase difference data p (k) is obtained from the following calculation.
_{p (k) = {y (} k) -V th} · T / {y (k) -y (k-1)} (2)
y (k): output signal V _{th of the} equalizer circuit: threshold voltage y (k−1), y (k): temporally continuous sample data T: sampling cycle
By determining the standard deviation σ based on the phase difference data p (k) determined by the equation (2), the jitter value of the RF signal can be measured.
[0038]
Here, in the present invention, since the digital equalizer having the configuration shown in FIG. 2 is used as the equalizer 22 in FIG. 1, there is no variation in the characteristics seen in the analog circuit components, and the circuit adjustment step can be eliminated.
The variation among the devices is limited to the reference voltage of the A / D converter 21 and only the AGC amplifier 20 at the preceding stage. Can be suppressed.
[0039]
For input signals of different speeds, there is a delay factor D corresponding to the clock period, so that it is not necessary to prepare a delay line for each speed as in the prior art, and one circuit can support various speeds.
[0040]
Further, the equalizer 22 may use a general-purpose circuit as shown in FIG. Circuit of Figure 5 is a FIR filter tap number 5, by arbitrarily setting the G ₄ for each of the tap from the tap coefficient G _0, it can be constructed equalizer various characteristics.
For example,
G ₀ = G ₄ = −k / 2
G ₁ = G ₃ = 0
G ₂ = 1
Then, the circuit of FIG. 2 can be realized.
[0041]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a jitter measuring apparatus and a measuring method that can perform jitter measurement on reproduction signals of disk recording media of various speeds by one unit, and realize a time relationship of reproduction signals of various disk recording media. It is suitable as a measuring device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of an embodiment of the present invention.
FIG. 2 is a block diagram of a general FIR filter.
FIG. 3 is a waveform chart in each part of FIG.
FIG. 4 is an explanatory diagram of a method of measuring phase difference data p (k).
FIG. 5 is a block diagram of a general-purpose FIR filter.
FIG. 6 is a block diagram showing an example of a conventional jitter measuring device.
FIG. 7 is a diagram illustrating an example of frequency characteristics of an equalizer used in an optical disc;
FIG. 8 is a waveform chart in each part of FIG. 6;
[Explanation of symbols]
Reference Signs List 20 input amplifier 21 A / D converter 22 equalizer circuit 23 gain setting holding unit 24 phase difference generation circuit 25 threshold voltage source 26 PLL circuit 27 standard deviation measurement circuit 28 output unit

Claims (4)

An A / D converter for converting a reproduction signal of a disk recording medium into a digital signal;
An equalizer that amplifies a specific frequency component of a digital signal converted and output from the A / D converter;
A phase difference generation circuit that generates and outputs a phase difference between a timing and a clock at which the output signal of the equalizer crosses a predetermined threshold;
A phase-locked loop circuit that uses the phase-difference output of the phase-difference circuit as a phase error input signal of a phase-locked loop, performs phase synchronization, reproduces a read clock, and supplies the read clock to each unit;
A standard deviation calculation circuit for calculating a standard deviation from the phase difference output of the phase difference generation circuit,
And a jitter measuring device. The equalizer includes a plurality of serially connected delay factors that generate a delay time corresponding to a clock cycle, a plurality of tap coefficient setting means connected to a connection point of these delay factors, and an arbitrary tap coefficient that can be set. 2. The jitter measuring apparatus according to claim 1, wherein the jitter measuring apparatus is an FIR filter including an adding means for adding an output of the setting means. 2. The jitter measuring apparatus according to claim 1, wherein the phase difference generating circuit generates and outputs phase difference data p (k) represented by the following equation.
_{p (k) = {y (} k) -V th} · T / {y (k) -y (k-1)}
y (k): output signal _{Vth of the} equalizer circuit: threshold voltage y (k-1), y (k): temporally continuous sample data T: sampling cycle Converting the reproduction signal of the disk recording medium into a digital signal;
Amplifying a specific frequency component of the converted digital signal;
A step of generating and outputting a phase difference between a timing and a clock at which the digital signal crosses a predetermined threshold from the amplified output of the specific frequency component,
A step of reproducing a phase-synchronized read clock from the phase difference output and supplying the read clock to each unit;
Calculating the standard deviation from the phase difference output,
And a jitter measuring method.

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