JP2004182297A

JP2004182297A - Tray for semiconductor integrated circuit

Info

Publication number: JP2004182297A
Application number: JP2002352173A
Authority: JP
Inventors: Seiji Azuma; 聖治東
Original assignee: SHINON DENKI SANGYO KK
Current assignee: SHINON DENKI SANGYO KK
Priority date: 2002-12-04
Filing date: 2002-12-04
Publication date: 2004-07-02
Anticipated expiration: 2022-12-04
Also published as: JP3993078B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tray capable of preventing terminal damages and dust deposition causing defective mounting of integrated circuits having a ball grid array terminal, and accommodating a plurality of kinds of integrated circuits of different dimensions. <P>SOLUTION: In the tray for accommodating ball grid array type semiconductor integrated circuits, a large number of projections 6 and 6 having a substantially semi-spherical top portion and an inclined side surface 6a expanding outwardly toward a base portion are provided on an upper surface of the tray, the arrangement spacing of the projections is twice or integer times of the arrangement spacing of terminals 8 and 8 of the semiconductor integrated circuits 7 to be accommodated in the tray. When the semiconductor integrated circuit is placed on the upper surface of the tray so that a bottom surface thereof is downwardly directed, a side surface in a lower half portion of the terminal 8 is abutted on the inclined side surface 6a of the projection to support the semiconductor circuit while a semiconductor integrated circuit body 9 is in a non-contact manner with the projection 6, and the movement in the horizontal direction of the semiconductor integrated circuit is regulated thereby. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明はボールグリッドアレイ端子を有する集積回路を収納するためのトレーに関する。
【０００２】
【従来の技術とその問題点】
ボールグリッドアレイ（ＢａｌｌＧｒｉｄＡｒｒａｙ）タイプ（以下、ＢＧＡタイプと略称）の半導体集積回路は、集積回路チップを内蔵する集積回路本体と、この集積回路本体の底面に配設された多数の略球状（ボール状）の端子を備えるものとしてあり、前記端子は半田よりなり、プリント基板等の外部の配線回路と接続するためのもので、各端子の直径は０．６〜１．０ｍｍ程度のものであり、０．５〜１．２７ｍｍ程度のピッチ（配設間隔）で数百個設けられている。
【０００３】
上述したＢＧＡタイプの集積回路を配線回路に搭載（実装）する際には、集積回路を配線回路上に載せた状態で加熱装置に入れて半田を融かし、その後温度を下げて半田を固化することによって集積回路の端子と外部の配線回路とを溶着させて接続する構成となっている。
【０００４】
ところで、集積回路はその端子が外部からの衝撃等の外力によって脱落すると商品価値がなくなり、特にＢＧＡタイプのものでは端子が配線回路への溶着手段を兼ねているので、端子にトレーの微細な樹脂片や樹脂に混入されているカーボンブラックなどの不純物が付着したり傷が付いたりしただけでも配線回路への接続不良（実装不良）の原因となる場合がある。
【０００５】
したがって、ＢＧＡタイプの集積回路用の保管や運搬に使用されるトレーでは、端子がトレーに接触しない状態で集積回路を収納できるものを要求されることが多い。
【０００６】
このような要求に対し、従来のトレーでは図１３に示されるようにトレー３１の壁３２に段差３２ａを形成し、この段差によって集積回路本体３６の端子側の面における端子よりも外側の部分を支持し、端子を底３３の上方に浮かせた状態で収納して壁３２や底３３が集積回路３４の端子３５、３５に接触しないようにしている。
【０００７】
すなわち、ＢＧＡタイプの半導体集積回路を収納するトレーにおいては、半導体集積回路の実装不良を解消するには、トレーを半導体集積回路本体だけに接触させて半導体集積回路の支持および位置決めをするようにして、端子はトレーの構成部分に全く接触させないように収納しなければならないというのが従来の技術的常識である。
【０００８】
しかし、集積回路の高密度化が進むにつれて集積回路全体の寸法は小型化する反面、端子の数は増大し、最も外側に位置する端子と集積回路本体３６の外周辺部との間すなわちトレーの段差３２ａによる被支持部分のスペースが殆どないというケースが多くなっており、端子の下端部にある程度の不純物や傷が付くことを承知で、端子の下端を、前記壁で囲まれる平坦面で直接支持するタイプのトレーも実用に供されている。
【０００９】
また、従来のトレーは壁３２によって区画された複数のポケット３７を有し、１つのポケットに１つの集積回路を収容して壁３２によって半導体集積回路の水平方向の動きを規制する構成となっており、各ポケットの形状すなわち壁や段差の高さおよび縦横寸法などは、集積回路本体のサイズに合わせて専用のものに設計しなければならず、サイズの異なる複数種類の集積回路に共用できるトレーはない。
【００１０】
【目的】
本発明の目的とするところは、ボールグリッドアレイ端子を有する集積回路の実装不良の原因となる端子の損傷や塵埃の付着を防止でき、しかも寸法の異なる複数種類の集積回路を収容することができるトレーを提供することにある。
【００１１】
【発明の構成】
上記目的を達成するために、本発明の請求項１に係るトレーは、半導体集積回路本体の底面に多数の端子を備えるボールグリッドアレイ型の半導体集積回路を収納するためのトレーにおいて、頂部が略半球状に形成され、かつ基部に向って外側に広がる傾斜側面を有する多数の突起をトレー上面に備え、これら突起の配設間隔が、トレーに収容される半導体集積回路の端子の配設間隔の２以上の整数倍であり、前記半導体集積回路をその底面が下向きとなるようにトレー上面に載せると、半導体集積回路本体と突起とは非接触であるが、突起の前記傾斜側面に端子の下半部における側面が当接して半導体集積回路が支持され、かつ半導体集積回路の水平方向の動きが規制されるように構成したものとしてある。
【００１２】
本発明の請求項２に係るトレーは、上面に半導体集積回路を個別に収容するためのエリアを有し、かつこれらのエリアを囲むガイドリブを備え、各ガイドリブは少なくともエリアの中央に臨む内側面が内側に向って下傾するテーパー状に形成され、上記エリア内に前記突起を設けた構成のものとしてある。
【００１３】
【実施例】
以下、本発明に係るトレーの実施例を添付図面に示す具体例に基づいて詳細に説明する。
トレー１は平面形状が略矩形を呈する合成樹脂材製のものとしてあり、この合成樹脂材は表面電気抵抗値を大ならしめるための例えばカーボンブラック等の導電性粉末を含有せしめたものとしてある。
【００１４】
トレー１の上面における外周辺部には、平面形状がトレーの外形に倣う略矩形状の立ち上がり枠辺２が形成されており、かつトレーの下面における外周辺部には立ち下がり枠辺３とその基部内周に沿う周溝４が形成されていて、複数のトレーを上下に積み重ねた際に、立ち上がり枠辺２の上端部が周溝４に嵌入するとともに立ち上がり枠辺の外周面が立ち下がり枠辺３の内周面に嵌入して上下のトレー間の位置決めがなされるようになっている。
【００１５】
両枠辺２、３間の嵌合には若干の遊びを持たせてあり、上記立ち上がり枠辺２の高さと周溝４の深さの関係により、複数のトレーを上下に積み重ねた際の下側トレー上面と上側トレーの下面との間の距離が設定される。
【００１６】
しかして、トレー１のベース５は下面が平坦に形成されているが、上面に多数の突起６、６が形成されていて、これら多数の突起６、６にて集積回路が支持される構成となっている。
【００１７】
上記突起６、６はベース５と一体に形成され、それぞれ基部に向って外側へ広がる傾斜側面６ａを有する略円錐状で頂部が半球状に形成されており、各突起は上部が集積回路７の端子８、８間に入り込むが、集積回路本体９の底面には接触せず、突起の傾斜側面６ａが端子の下半部側面に当接する配設間隔および寸法のものとしてある。
【００１８】
具体的には、突起６、６がベース５上の前後左右方向に等間隔で配設され、その配設間隔ＰＰと、収容される集積回路７のボール端子８、８の配設間隔ＰＴとの関係が、
ＰＰ＝ｎＰＴ（ｎは２以上の整数）
となるように構成してあり、本実施例では突起の配設間隔ＰＰが端子の配設間隔ＰＴの２倍となるように構成してある。
【００１９】
なお、突起は等間隔に設けない場合もあり、例えば一部の突起を省いたり、あるいは一部の突起を端子の配設間隔の整数倍分前後または左右方向にずらして設けたりする場合もある。
【００２０】
また突起６、６の寸法は、半導体集積回路をトレー上に載せた際に、正方形状に近接する４つの端子間に突起が入り込み、図５のように突起６、６の上端は半導体集積回路本体９の底面に非接触であるが、突起の傾斜側面６ａに端子の下端部以外の下半部側面が接点ＣＰにて接触して半導体集積回路が支持されるようにしてある。
【００２１】
また、１つの突起を囲む４つの端子は、突起の同一水平断面上において等間隔で点接触するので、半導体集積回路がトレー内に収容された状態で集積回路に外部からの衝撃等による外力が掛かった場合、外力の水平方向成分は端子から突起へ水平方向に掛かり、集積回路の水平方向の移動が阻止される。
【００２２】
上述のように構成されたトレー１上面に半導体集積回路７を収容して他のトレーを積み重ねた状態において、本実施例のトレーは半導体集積回路の上面と上側のトレー下面との間には、図３に示されるように隙間αが形成されるように前記立ち上がり枠辺２の高さと周溝４の深さを設定してある。
【００２３】
上記隙間αは、上下のトレー間に半導体集積回路を収納して多数のトレーを積み重ねた状態において、上方からの荷重が半導体集積回路に掛からないようにするための遊びである。
【００２４】
また上記隙間αは、突起６、６の上端を通る平面Ａと端子８、８の下端を通る平面Ｂとの間の距離、すなわち突起と端子の嵌め合い深さβよりも小なるものとしてあって、トレー間に収容された半導体集積回路の端子がトレーの突起を乗り越えて移動するのを防止している。
【００２５】
上述のように構成したトレーにおいては、トレーの上面に半導体集積回路７をその端子８、８側の面が下向きとなるようにして載せると、端子８、８の表面が突起の頂部の曲面に案内されて端子が突起の側部に入り込み、端子の下半部側面が突起の傾斜側面６ａに当接して半導体集積回路が支持される。
【００２６】
なお、半導体集積回路をトレー上面に載せる際に、端子の下端部が突起の上端面に接触する可能性はあるが、突起の頂部は略半球状の曲面に形成されており、しかも突起頂部との接触は瞬間的なものであって長時間あるいは繰り返し摺接することはあり得ないので、端子の下端部に実装不良の原因となるような不純物の付着や損傷のおそれはない。
【００２７】
その後、上記トレーの立ち上がり枠辺２まわりに別のトレーの立ち下り枠辺３を嵌合せしめて積み重ねると、上側のトレーの下面が半導体集積回路７の上面に非接触で臨み、半導体集積回路は上下のトレー間に収納される。
【００２８】
しかして半導体集積回路をトレー間に収納した状態において、外部からの振動や衝撃で半導体集積回路に水平方向の外力が掛かった場合、突起の側面に端子の側面が当接しているので、半導体集積回路の水平方向の移動が防止され、また半導体集積回路が上下方向に動揺した場合、上側トレーの下面が半導体集積回路の上面に非接触で臨んでおり、しかも上側トレーの下面と半導体集積回路の上面との間の隙間αが端子と突起の嵌め合い深さβよりも小であるので、端子が突起の上方を乗り越えて移動するのが防止される。
【００２９】
上述のようにトレー間に収納された半導体集積回路の端子は、その側面が突起の側面に当接するが、半導体集積回路をプリント基板等の配線回路に実装する際の接続部分となる端子の下端部は突起およびその他のトレーの構成部分に接触しない。
【００３０】
したがって、端子の下端部に不純物が付着したり傷が付いたりするおそれはまずなく、半導体集積回路の実装不良を防止することができる。
【００３１】
また、本実施例のトレーにおいては、半導体集積回路を個別に収容するための壁等の仕切がないので、半導体集積回路をトレー上の任意の位置に収容することができ、さらに端子の配設間隔が同じものであれば集積回路本体の縦横寸法の異なる他の仕様の半導体集積回路を収容することもできる。
【００３２】
次ぎに、本発明に係るトレーの第２実施例を図６〜１２に基づいて以下に説明する。
上述した第１実施例のトレーにおいては、トレーの上面、下面ともに半導体集積回路を個々に収容するための仕切がなく、半導体集積回路の収容位置を任意に設定することができる構成としてあるが、第２実施例のものはトレーの上面および下面に半導体集積回路を収容する際のガイドを備え所定のエリア内に個々の半導体集積回路を収容できるようにしたものとしてある。
【００３３】
しかして、トレー１０は上面に個々の半導体集積回路を収容するためのエリア１１を有し、これらのエリアの各４隅は略Ｌ字状の上向きガイドリブ１２によって囲まれており、各上向きガイドリブは少なくともエリアの中央に臨む内側面１２ａが内側に向って下傾するテーパー状に形成されている。
【００３４】
上記エリア１１内におけるトレー上面には、第１実施例のものと同様に多数の突起６、６が形成されていて、これら突起の配設間隔や寸法も第１実施例ものと同じである。
【００３５】
なお、本第２実施例のものではエリア中央部分のいくつかの突起が省略され、配設間隔も等間隔ではない点が第１実施例のものと異なるが、突起の配設間隔は端子の配設間隔のｎ倍（ｎは２以上の整数）であれば事が足り、したがって一部分における突起の配設間隔が例えば２倍で、他の部分における突起の配設間隔が例えば３倍あるいは４倍というように異なる配設間隔にすることができる。
【００３６】
また、トレー１０下面には上面の収容エリア１１に対応する位置に同じく収容エリア１３を有し、これらのエリアの各４辺に下向きガイドリブ１４を備えていて、各下向きガイドリブは少なくともエリアの中央に臨む内側面１４ａが内側に向って下傾するテーパー状に形成されている。
【００３７】
なお、第２実施例のものも第１実施例のものと同様に上面に立ち上がり枠辺２と下面に立ち下り枠辺３および周溝４を備え、トレーどうしを上下に積み重ねた際に下側トレーの立ち上がり枠辺２まわりに上側トレーの立ち下り枠辺３が嵌合するようになっている。
【００３８】
しかして、上述したトレー１０上面の上向きガイドリブ１２はトレー上面に半導体集積回路を載せる際に、半導体集積回路の位置が所定の位置からずれていてもガイドリブの内側面１２ａによって適正位置に案内するためのガイドであり、またトレー下面の下向きガイドリブ１４は、上下のトレー間に半導体集積回路を収容して上下を反転させた場合に、ガイドリブの内側面１４ａによって適正位置に案内するためのガイドである。
【００３９】
すなわち、これらのガイドリブ１２、１４は半導体集積回路の水平方向の動きを規制するためのものではなく、半導体集積回路を適正位置に導入するためのものとしてあり、半導体集積回路の水平方向の動きは第１実施例のものと同様に突起の傾斜側面６ａに端子の下半部における側面が当接することによって防止される。
【００４０】
したがって、半導体集積回路本体の縦横寸法がガイドリブにて囲まれるスペースよりも小で、かつ端子の配設間隔が同じものであれば集積回路本体の縦横寸法が異なる複数種類の仕様の半導体集積回路に共用することもできる。
【００４１】
なお、本第２実施例のものにおいては、複数のトレーを上下に積み重ねた際に、図１２に示されるようにトレー上面の上向きガイドリブ１２の間に上側トレー下面の下向きガイドリブ１４が入り込む構成としてあるが、上下のトレー間は下側トレー上面の立ち上がり枠辺２と上側トレー下面の立ち下り枠辺３との係合により位置合わせが行なわれるようになっているので、前記上向きガイドリブと下向きガイドリブは上下のトレーの位置合わせには関係がなく、これらのガイドリブは互いの端面が接触あるいは隙間をあけて対峙する形状、寸法とする場合もあり、このような場合には両ガイドリブを各エリアの４隅または４辺を囲む形状のものにしたり、あるいは一方または両方のガイドリブを略正方形状のものにしたりすることもできる。
【００４２】
【発明の効果】
本発明によれば、トレー上面に設けた多数の突起の傾斜側面に、半導体集積回路の端子の下半部における側面を当接させて支持し、かつ半導体集積回路の水平方向の動きを防止するという全く新規な技術的発想により、半導体集積回路の実装不良の原因となる端子下端部への不純物の付着や損傷が防止され、半導体集積回路の信頼性を低下させることなく収納できるトレーを提供することができる。
【００４３】
また本発明のトレーは、突起が半導体集積回路の水平方向の位置決めを行なうので、従来のトレーにおいて半導体集積回路の水平方向の動きを規制するために必要であった壁に相当する構成が不要であり、したがって端子の配設間隔が同じものであれば集積回路本体の縦横寸法が異なる仕様の半導体集積回路を壁の縦横寸法に制限されることなく収容することができる。
【図面の簡単な説明】
【図１】本発明に係るトレーの第１実施例を示す平面図。
【図２】本発明に係るトレーの第１実施例を示す底面図。
【図３】本発明の第１実施例のトレーを積み重ねた状態の拡大縦断面図。
【図４】端子の中心を通る水平面における突起と端子との位置関係を示す横断面図。
【図５】図４のＶ−Ｖ線上における突起と端子との位置関係を示す横断面図。
【図６】本発明に係るトレーの第２実施例を示す平面図。
【図７】本発明に係るトレーの第２実施例を示す底面図。
【図８】本発明に係るトレーの第２実施例の一部を拡大して示す平面図。
【図９】本発明に係るトレーの第２実施例の一部を拡大して示す底面図。
【図１０】本発明に係る第２実施例のトレーのＸ−Ｘ線拡大縦断面図。
【図１１】本発明に係る第２実施例のトレーのＸＩ−ＸＩ線拡大縦断面図。
【図１２】本発明の第２実施例のトレーを積み重ねた状態の拡大縦断面図。
【図１３】従来のトレーを積み重ねた状態を示す縦断面図。
【符号の説明】
１トレー
２立ち上がり枠辺
３立ち下がり枠辺
４周溝
５ベース
６突起
７半導体集積回路
８端子
９集積回路本体
１０トレー
１１収容エリア
１２上向きガイドリブ
１３収容エリア
１４下向きガイドリブ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a tray for storing an integrated circuit having a ball grid array terminal.
[0002]
[Conventional technology and its problems]
2. Description of the Related Art A ball grid array (BGA type) semiconductor integrated circuit includes an integrated circuit main body having an integrated circuit chip and a plurality of substantially spherical (disclosed on the bottom surface of the integrated circuit main body). The terminal is made of solder and is for connection to an external wiring circuit such as a printed circuit board. Each terminal has a diameter of about 0.6 to 1.0 mm. Some hundreds are provided at a pitch (arrangement interval) of about 0.5 to 1.27 mm.
[0003]
When mounting (mounting) the above-mentioned BGA type integrated circuit on a wiring circuit, put the integrated circuit on the wiring circuit and put it in a heating device to melt the solder, then lower the temperature and solidify the solder. By doing so, the terminal of the integrated circuit and the external wiring circuit are welded and connected.
[0004]
By the way, the integrated circuit loses its commercial value if its terminals fall off due to external force such as external impact. In particular, in the case of BGA type, the terminals also serve as the means for welding to the wiring circuit, so the fine resin of the tray is attached to the terminals. Even if an impurity such as carbon black mixed in a piece or resin adheres or is scratched, it may cause a poor connection (improper mounting) to a wiring circuit.
[0005]
Therefore, trays used for storage and transportation of BGA type integrated circuits are often required to be capable of storing the integrated circuits without the terminals being in contact with the trays.
[0006]
In response to such a requirement, in the conventional tray, a step 32a is formed on the wall 32 of the tray 31 as shown in FIG. The terminal 32 is supported in a state of being floated above the bottom 33 so that the wall 32 and the bottom 33 do not contact the terminals 35 of the integrated circuit 34.
[0007]
That is, in a tray for storing a BGA type semiconductor integrated circuit, in order to eliminate a mounting defect of the semiconductor integrated circuit, the tray is brought into contact only with the semiconductor integrated circuit body to support and position the semiconductor integrated circuit. It is conventional technical knowledge that the terminals must be housed so as not to contact the components of the tray at all.
[0008]
However, as the density of the integrated circuit has increased, the dimensions of the entire integrated circuit have been reduced, but the number of terminals has increased, and between the outermost terminals and the outer periphery of the integrated circuit body 36, that is, the tray has In many cases, there is little space in the supported portion due to the step 32a, and the terminal lower end is directly connected to the flat surface surrounded by the wall, knowing that the terminal lower end has a certain amount of impurities and scratches. Supporting trays are also in practical use.
[0009]
Further, the conventional tray has a plurality of pockets 37 partitioned by walls 32, one integrated circuit is accommodated in one pocket, and the wall 32 regulates the horizontal movement of the semiconductor integrated circuit. In addition, the shape of each pocket, that is, the height and length and width of walls and steps, must be designed exclusively for the size of the integrated circuit body, and a tray that can be shared by multiple types of integrated circuits of different sizes. There is no.
[0010]
【Purpose】
An object of the present invention is to prevent damage to terminals and adhesion of dust, which may cause defective mounting of an integrated circuit having ball grid array terminals, and to accommodate a plurality of types of integrated circuits having different dimensions. To provide trays.
[0011]
Configuration of the Invention
In order to achieve the above object, a tray according to claim 1 of the present invention is a tray for accommodating a ball grid array type semiconductor integrated circuit having a large number of terminals on a bottom surface of a semiconductor integrated circuit main body, the top of which is substantially the same. A large number of protrusions having a hemispherical shape and having inclined side surfaces extending outward toward the base are provided on the upper surface of the tray, and the interval between these projections is smaller than the interval between the terminals of the semiconductor integrated circuit accommodated in the tray. When the semiconductor integrated circuit is placed on the upper surface of the tray such that the bottom surface faces downward, the semiconductor integrated circuit main body and the projection are not in contact with each other. The semiconductor integrated circuit is supported by contacting the side surfaces in the half, and the horizontal movement of the semiconductor integrated circuit is restricted.
[0012]
The tray according to claim 2 of the present invention has areas on the upper surface for individually accommodating semiconductor integrated circuits, and includes guide ribs surrounding these areas, and each guide rib has at least an inner side facing the center of the area. It is formed in a tapered shape inclined downward toward the inside, and has a configuration in which the protrusion is provided in the area.
[0013]
【Example】
Hereinafter, embodiments of the tray according to the present invention will be described in detail based on specific examples shown in the accompanying drawings.
The tray 1 is made of a synthetic resin material having a substantially rectangular planar shape. The synthetic resin material contains a conductive powder such as carbon black for increasing the surface electric resistance.
[0014]
A substantially rectangular rising frame side 2 whose planar shape follows the outer shape of the tray is formed in an outer peripheral portion on the upper surface of the tray 1, and a falling frame side 3 is formed in the outer peripheral portion on the lower surface of the tray 1. A peripheral groove 4 is formed along the inner circumference of the base, and when a plurality of trays are stacked up and down, the upper end of the rising frame side 2 fits into the peripheral groove 4 and the outer peripheral surface of the rising frame side is a falling frame. The upper and lower trays are fitted into the inner peripheral surface of the side 3 to perform positioning between the upper and lower trays.
[0015]
The fitting between the two frame sides 2 and 3 has some play, and depending on the relationship between the height of the rising frame side 2 and the depth of the circumferential groove 4, the lower side when a plurality of trays are stacked up and down. The distance between the upper surface of the side tray and the lower surface of the upper tray is set.
[0016]
The lower surface of the base 5 of the tray 1 is flat, but a number of protrusions 6 are formed on the upper surface, and the integrated circuit is supported by the number of protrusions 6. Has become.
[0017]
The protrusions 6 and 6 are formed integrally with the base 5. Each protrusion 6 is formed in a substantially conical shape having an inclined side surface 6 a extending outward toward the base, and the top is formed in a hemispherical shape. Although it enters between the terminals 8 and 8, it does not contact the bottom surface of the integrated circuit main body 9, and the arrangement interval and dimensions are such that the inclined side surface 6 a of the protrusion contacts the lower half side surface of the terminal.
[0018]
More specifically, the protrusions 6 are arranged at equal intervals in the front-rear and left-right directions on the base 5, and the arrangement interval PP and the arrangement interval PT of the ball terminals 8, 8 of the integrated circuit 7 to be accommodated. The relationship is
PP = nPT (n is an integer of 2 or more)
In this embodiment, the interval PP between the projections is twice as large as the interval PT between the terminals.
[0019]
Note that the projections may not be provided at equal intervals, and for example, some projections may be omitted, or some projections may be shifted in the front and rear direction or the left and right direction by an integral multiple of the terminal arrangement interval. .
[0020]
When the semiconductor integrated circuit is placed on a tray, the protrusions enter between four terminals which are close to a square, and the upper ends of the protrusions 6 are formed as shown in FIG. Although not in contact with the bottom surface of the main body 9, the lower half side surface other than the lower end portion of the terminal is in contact with the inclined side surface 6a of the terminal at the contact point CP to support the semiconductor integrated circuit.
[0021]
In addition, since the four terminals surrounding one projection make point contact at equal intervals on the same horizontal cross section of the projection, external force due to external impact or the like is applied to the integrated circuit while the semiconductor integrated circuit is housed in the tray. When it is applied, the horizontal component of the external force is applied horizontally from the terminal to the protrusion, and the horizontal movement of the integrated circuit is prevented.
[0022]
In a state where the semiconductor integrated circuit 7 is accommodated on the upper surface of the tray 1 configured as described above and other trays are stacked, the tray of the present embodiment is provided between the upper surface of the semiconductor integrated circuit and the lower surface of the upper tray. As shown in FIG. 3, the height of the rising frame side 2 and the depth of the circumferential groove 4 are set so that the gap α is formed.
[0023]
The gap α is a play for preventing a load from above from being applied to the semiconductor integrated circuit in a state where the semiconductor integrated circuits are accommodated between the upper and lower trays and a large number of trays are stacked.
[0024]
The gap α is smaller than the distance between the plane A passing through the upper ends of the projections 6 and 6 and the plane B passing through the lower ends of the terminals 8 and 8, that is, the fitting depth β between the projection and the terminal. Thus, the terminal of the semiconductor integrated circuit accommodated between the trays is prevented from moving over the protrusions of the tray.
[0025]
In the tray constructed as described above, when the semiconductor integrated circuit 7 is placed on the upper surface of the tray with the terminals 8 and 8 facing downward, the surfaces of the terminals 8 and 8 become curved at the tops of the protrusions. The terminal is guided and enters the side of the protrusion, and the lower half side surface of the terminal contacts the inclined side surface 6a of the protrusion to support the semiconductor integrated circuit.
[0026]
When the semiconductor integrated circuit is placed on the upper surface of the tray, the lower end of the terminal may come into contact with the upper end of the protrusion, but the top of the protrusion is formed into a substantially hemispherical curved surface, and the top of the protrusion is formed. Contact is instantaneous and cannot be slid in contact for a long time or repeatedly, so that there is no possibility that impurities may be attached to the lower end of the terminal or may be damaged, which may cause a mounting failure.
[0027]
Thereafter, when the falling frame side 3 of another tray is fitted around the rising frame side 2 of the tray and stacked, the lower surface of the upper tray faces the upper surface of the semiconductor integrated circuit 7 without contact, and the semiconductor integrated circuit is Stored between the trays.
[0028]
However, if a horizontal external force is applied to the semiconductor integrated circuit by external vibration or impact in a state where the semiconductor integrated circuit is stored between the trays, the side surfaces of the terminals are in contact with the side surfaces of the protrusions. When the circuit is prevented from moving in the horizontal direction, and when the semiconductor integrated circuit swings up and down, the lower surface of the upper tray faces the upper surface of the semiconductor integrated circuit in a non-contact manner. Since the gap α between the upper surface and the terminal is smaller than the fitting depth β between the terminal and the protrusion, the terminal is prevented from moving over the protrusion.
[0029]
As described above, the terminals of the semiconductor integrated circuit housed between the trays have their side surfaces abutting on the side surfaces of the protrusions, but the lower ends of the terminals serving as connection portions when the semiconductor integrated circuit is mounted on a wiring circuit such as a printed circuit board. The parts do not touch the projections and other components of the tray.
[0030]
Therefore, it is unlikely that impurities are attached to the lower end of the terminal or the terminal is damaged, so that a mounting failure of the semiconductor integrated circuit can be prevented.
[0031]
Further, in the tray of this embodiment, since there is no partition such as a wall for individually storing the semiconductor integrated circuits, the semiconductor integrated circuits can be stored in an arbitrary position on the tray, and furthermore, the terminals are arranged. As long as the intervals are the same, semiconductor integrated circuits of different specifications having different vertical and horizontal dimensions of the integrated circuit body can be accommodated.
[0032]
Next, a second embodiment of the tray according to the present invention will be described below with reference to FIGS.
In the tray of the first embodiment described above, there is no partition for individually housing the semiconductor integrated circuits on both the upper surface and the lower surface of the tray, and the housing position of the semiconductor integrated circuit can be set arbitrarily. In the second embodiment, a guide for accommodating semiconductor integrated circuits is provided on the upper and lower surfaces of the tray so that individual semiconductor integrated circuits can be accommodated in a predetermined area.
[0033]
The tray 10 has areas 11 for accommodating individual semiconductor integrated circuits on its upper surface, and four corners of each of these areas are surrounded by substantially L-shaped upward guide ribs 12. At least the inner side surface 12a facing the center of the area is formed in a tapered shape inclined downward toward the inside.
[0034]
A large number of protrusions 6 are formed on the upper surface of the tray in the area 11 as in the first embodiment, and the arrangement intervals and dimensions of these protrusions are the same as those in the first embodiment.
[0035]
The second embodiment differs from the first embodiment in that some projections at the center of the area are omitted and the arrangement intervals are not equal. However, the arrangement intervals of the projections are different from those of the terminal. It suffices that n times the arrangement interval (n is an integer of 2 or more). Therefore, the arrangement interval of the protrusions in one part is, for example, twice, and the arrangement interval of the protrusions in the other part is, for example, three times or four. It is possible to set different arrangement intervals such as double.
[0036]
The lower surface of the tray 10 also has a storage area 13 at a position corresponding to the storage area 11 on the upper surface, and a downward guide rib 14 is provided on each of four sides of these areas, and each downward guide rib is provided at least in the center of the area. The facing inner side surface 14a is formed in a tapered shape inclined downward toward the inside.
[0037]
Note that the second embodiment also has a rising frame side 2 on the upper surface and a falling frame side 3 and a peripheral groove 4 on the lower surface, like the first embodiment, so that when the trays are stacked up and down, the lower side is formed. The falling frame side 3 of the upper tray fits around the rising frame side 2 of the tray.
[0038]
The upward guide rib 12 on the upper surface of the tray 10 guides the semiconductor integrated circuit to the proper position by the inner side surface 12a of the guide rib even when the position of the semiconductor integrated circuit is shifted from a predetermined position when the semiconductor integrated circuit is placed on the upper surface of the tray. The downward guide ribs 14 on the lower surface of the tray are guides for guiding the semiconductor integrated circuit between the upper and lower trays to an appropriate position by the inner side surface 14a of the guide rib when the semiconductor integrated circuit is turned upside down. .
[0039]
That is, these guide ribs 12 and 14 are not for regulating the horizontal movement of the semiconductor integrated circuit, but for introducing the semiconductor integrated circuit to an appropriate position. As in the case of the first embodiment, this is prevented by the side surface of the lower half of the terminal abutting on the inclined side surface 6a of the projection.
[0040]
Therefore, if the vertical and horizontal dimensions of the semiconductor integrated circuit main body are smaller than the space surrounded by the guide ribs and the arrangement intervals of the terminals are the same, the semiconductor integrated circuit of different types having different vertical and horizontal dimensions of the integrated circuit main body can be used. They can be shared.
[0041]
In the second embodiment, when a plurality of trays are vertically stacked, the downward guide ribs 14 on the lower surface of the upper tray enter between the upward guide ribs 12 on the upper surface of the tray as shown in FIG. However, since the upper and lower trays are aligned by engaging the rising frame side 2 on the upper surface of the lower tray and the falling frame side 3 on the lower surface of the upper tray, the upward guide rib and the downward guide rib are used. Is not related to the alignment of the upper and lower trays, and these guide ribs may be shaped and dimensioned so that their end faces are in contact with each other or with a gap between them. The guide ribs may be formed so as to surround four corners or four sides, or one or both guide ribs may be formed into a substantially square shape.
[0042]
【The invention's effect】
According to the present invention, the side surface in the lower half portion of the terminal of the semiconductor integrated circuit is brought into contact with and supported by the inclined side surfaces of a number of protrusions provided on the upper surface of the tray, and prevents the semiconductor integrated circuit from moving in the horizontal direction. By providing a tray that can be stored without lowering the reliability of the semiconductor integrated circuit by preventing the adhesion and damage of impurities to the lower end of the terminal, which causes the mounting failure of the semiconductor integrated circuit, by a completely new technical idea of be able to.
[0043]
Further, in the tray of the present invention, since the protrusions position the semiconductor integrated circuit in the horizontal direction, a structure corresponding to a wall required for restricting the horizontal movement of the semiconductor integrated circuit in the conventional tray is unnecessary. Therefore, as long as terminals are arranged at the same interval, semiconductor integrated circuits having different specifications of the vertical and horizontal dimensions of the integrated circuit body can be accommodated without being limited to the vertical and horizontal dimensions of the wall.
[Brief description of the drawings]
FIG. 1 is a plan view showing a first embodiment of a tray according to the present invention.
FIG. 2 is a bottom view showing the first embodiment of the tray according to the present invention.
FIG. 3 is an enlarged vertical sectional view showing a state in which trays according to the first embodiment of the present invention are stacked.
FIG. 4 is a cross-sectional view showing a positional relationship between a terminal and a protrusion on a horizontal plane passing through the center of the terminal.
FIG. 5 is a cross-sectional view showing the positional relationship between the protrusion and the terminal on the line VV in FIG. 4;
FIG. 6 is a plan view showing a second embodiment of the tray according to the present invention.
FIG. 7 is a bottom view showing a second embodiment of the tray according to the present invention.
FIG. 8 is an enlarged plan view showing a part of a second embodiment of the tray according to the present invention.
FIG. 9 is an enlarged bottom view showing a part of a second embodiment of the tray according to the present invention.
FIG. 10 is an enlarged vertical sectional view taken along line XX of a tray according to a second embodiment of the present invention.
FIG. 11 is an enlarged vertical sectional view taken along line XI-XI of a tray according to a second embodiment of the present invention.
FIG. 12 is an enlarged vertical sectional view of a state in which trays according to the second embodiment of the present invention are stacked.
FIG. 13 is a longitudinal sectional view showing a state where conventional trays are stacked.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Tray 2 Rising frame side 3 Falling frame side 4 Peripheral groove 5 Base 6 Projection 7 Semiconductor integrated circuit 8 Terminal 9 Integrated circuit main body 10 Tray 11 Storage area 12 Upward guide rib 13 Storage area 14 Downward guide rib

Claims

A tray for accommodating a ball grid array type semiconductor integrated circuit having a large number of terminals on a bottom surface of a semiconductor integrated circuit body, a top having a substantially hemispherical shape, and having a plurality of inclined side surfaces extending outward toward a base. Are provided on the upper surface of the tray, and the arrangement interval of these projections is an integral multiple of 2 or more of the arrangement interval of the terminals of the semiconductor integrated circuit accommodated in the tray, and the bottom surface of the semiconductor integrated circuit faces downward. When the semiconductor integrated circuit is placed on the upper surface of the tray as described above, the semiconductor integrated circuit body and the projection are not in contact with each other, but the side surface in the lower half of the terminal abuts on the inclined side surface of the projection, and the semiconductor integrated circuit is supported. A semiconductor integrated circuit tray configured to restrict horizontal movement of the semiconductor integrated circuit.

The top surface has areas for individually accommodating the semiconductor integrated circuits, and includes guide ribs surrounding these areas, and each guide rib is formed in a tapered shape in which at least an inner surface facing the center of the area is inclined downward toward the inside. 2. The semiconductor integrated circuit tray according to claim 1, wherein said projection is provided in said area.