JP2004179320A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with its power consumption efficiently reduced by constantly setting optimum data for each LSI. <P>SOLUTION: The semiconductor device has a replica control circuit 15 having a decoder circuit 151 for reading data to be determined by the state of fuse in the fuse circuit 152, and for generating a control signal SADJ for a replica circuit 12 by decoding the read data. The device further has a replica circuit 12 capable of selecting the number of stages in the line of elements according to the control signal SADJ indicating structural data set in the replica control circuit 15, and capable of adjusting the delay characteristics to be the same as the critical path characteristics of a target circuit 11. In this way, dispersion in characteristics due to the manufacturing process is properly dealt with after the manufacturing of LSIs. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a monitor circuit for grasping a critical path delay characteristic of a target circuit, and in particular, to reduce power consumption by adaptively controlling a power supply voltage supplied to an LSI which is a target circuit. It is about technology.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in a semiconductor circuit, a method of lowering a power supply voltage has been generally adopted to reduce power consumption. This is because the AC component of the power consumption of the semiconductor circuit (LSI) is proportional to the square of the power supply voltage, and the reduction of the power supply voltage is most effective in reducing the power consumption of the LSI.
[0003]
From such a viewpoint, in recent years, there has been reported a method of dynamically controlling a power supply voltage with respect to an operating frequency, a process variation, and a temperature change of an LSI, and adaptively supplying a minimum voltage at which the LSI can operate. .
[0004]
As an example of realizing such adaptive power supply voltage control, a delay circuit for generating a delay equivalent to a critical path of an LSI is mounted, an operation clock frequency of a target circuit to be controlled by the power supply voltage, and a delay of the delay circuit. By comparing the values, the power supply voltage is controlled so that the delay value of the delay circuit falls within the operation clock cycle (for example, see Patent Document 1, Patent Document 2, and Patent Document 3).
[0005]
These semiconductor devices include a delay element whose delay value can be adjusted by a control signal of a control circuit as a component, and a replica circuit that receives a reference signal of a predetermined cycle as input and propagates the signal.
The control signal supplied to the replica circuit is generated by decoding data stored in the register by a decoder. Then, the delay characteristics of the replica circuit can be adjusted by rewriting the data stored in the register.
As described above, since the delay characteristic of the replica circuit can be adjusted by the data stored in the register, the data to be stored in the register can be determined after measuring the delay characteristic after manufacturing the LSI.
[0006]
[Patent Document 1]
JP 2000-216338 A
[Patent Document 2]
JP 2000-295084 A
[Patent Document 3]
JP-A-2002-100967
[0007]
[Problems to be solved by the invention]
Conventionally, after manufacturing an LSI, data to be stored in a register is determined after measuring a delay characteristic thereof. However, data is already determined at the time of manufacturing and shipping an electric product including the LSI as a component. There is a need.
Therefore, it is necessary to determine the data from the delay characteristics of a limited number of samples at the early stage of manufacturing, and thereafter, when manufacturing and shipping a large amount of LSIs and electrical products using the same as components, In other words, data cannot be updated, that is, software for setting a value in a register cannot be updated.
Therefore, it is necessary to determine the setting data in consideration of a certain margin.
[0008]
In this case, even if a change occurs in the delay characteristic of the LSI due to reasons for manufacturing the LSI, such as a variation in characteristics due to manufacturing or a change in the manufacturing process after the data is determined, it cannot be accommodated.
When the delay characteristic of the LSI is improved and the margin is increased, further reduction in power becomes possible, but it cannot be realized.
Further, when the delay characteristic of the LSI is deteriorated and the margin is reduced, there is a disadvantage that the LSI may malfunction.
[0009]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of efficiently realizing low power consumption by always setting optimal data for each LSI. It is to be.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention is a semiconductor device having delay monitoring means for grasping a critical path delay characteristic of a target circuit, wherein the delay monitoring means is provided inside the target circuit. Including a delay component that causes a signal propagation delay, the semiconductor device includes a plurality of delay elements that form a delay element array according to a supplied control signal, and further includes desired configuration information for forming the delay element array. There is a setting means which can be set after the semiconductor device is manufactured and which generates the control signal based on the set data and outputs the control signal to the delay monitoring means.
[0011]
Preferably, the setting means includes a fuse circuit for determining data, reads data determined by a fuse state of the fuse circuit, and generates the control signal according to the read data.
[0012]
Preferably, the setting means includes a non-volatile memory to which data can be written from the outside, reads the data written in the non-volatile memory, and generates the control signal according to the read data.
[0013]
According to a second aspect of the present invention, there is provided a semiconductor device having delay monitoring means for grasping a critical path delay characteristic of a target circuit, wherein the delay monitoring means causes a signal propagation delay inside the target circuit. A plurality of delay elements including a delay component and forming a delay element array according to a supplied control signal are provided, and desired configuration information for forming the delay element array can be set after manufacturing the semiconductor device. And setting means for generating the control signal based on the set data and outputting the control signal to the delay monitor means, the setting means comprising: a register in which the configuration information is set; and a correction value of the register setting data. Correction value setting means that can set
[0014]
Preferably, the correction value setting means of the setting means includes a fuse circuit for determining a correction value, wherein the setting means reads data determined by a fuse state of the fuse circuit, and reads the data according to the read data. The register setting data is corrected, and the control signal is generated based on the corrected data.
[0015]
Preferably, the correction value setting means of the setting means includes a non-volatile memory capable of externally writing the correction value, and the setting means reads the correction value written in the non-volatile memory, and reads the read data. , The setting data of the register is corrected according to the above formula, and the control signal is generated based on the corrected data.
[0016]
According to a third aspect of the present invention, there is provided delay monitoring means for grasping a critical path delay characteristic of a target circuit, and a value of a power supply voltage supplied to the target circuit is determined based on a result of delay monitoring by the delay monitoring means. A semiconductor device including a power supply voltage control function for controlling, comprising setting means capable of setting data for invalidating the power supply voltage control function and supplying a fixed power supply voltage to the target circuit after manufacturing the semiconductor device.
[0017]
Preferably, the setting means includes a fuse circuit for determining data, reads data determined by a fuse state of the fuse circuit, and generates an invalidation signal according to the read data.
[0018]
Preferably, the setting means includes a non-volatile memory to which data can be written from the outside, reads the data written in the non-volatile memory, and generates an invalidation signal according to the read data.
The semiconductor device according to claim 7.
[0019]
According to a fourth aspect of the present invention, there is provided a delay monitor for grasping a critical path delay characteristic of a target circuit, and a value of a power supply voltage supplied to the target circuit is determined based on a result of the delay monitor by the delay monitor. A semiconductor device including a power supply voltage control function for controlling, wherein the delay monitoring means includes a delay component which causes a signal propagation delay inside the target circuit, and forms a delay element row according to a supplied control signal. A plurality of delay elements, the desired configuration information for forming the delay element array can be set after the semiconductor device is manufactured, and the control signal is generated based on the set data to generate the control signal. First setting means for outputting to the means, data for causing the target circuit to supply a fixed power supply voltage by disabling the power supply voltage control function. And a second setting means settable to post-production.
[0020]
According to a fifth aspect of the present invention, there is provided a delay monitor for grasping a critical path delay characteristic of a target circuit, and a value of a power supply voltage supplied to the target circuit is determined based on a result of the delay monitor by the delay monitor. A semiconductor device including a power supply voltage control function for controlling, wherein the delay monitoring means includes a delay component which causes a signal propagation delay inside the target circuit, and forms a delay element row according to a supplied control signal. A plurality of delay elements, the desired configuration information for forming the delay element array can be set after the semiconductor device is manufactured, and the control signal is generated based on the set data to generate the control signal. First setting means for outputting to the means, data for causing the target circuit to supply a fixed power supply voltage by disabling the power supply voltage control function. Second setting means that can be set after the device is manufactured. The first setting means is a register in which the configuration information is set, and a correction value setting means that can set a correction value of the setting data of the register. And
[0021]
According to the present invention, the following processing is performed, for example, as part of an LSI shipping test after LSI manufacture.
First, the power supply voltage delay characteristics of the delay monitor and the target circuit are obtained. Next, based on the obtained power supply voltage delay characteristics, the delay monitor calculates a set value for realizing the same power supply voltage delay characteristics as that of the target circuit.
Then, the calculated set value is set in the fuse circuit.
That is, if necessary, the fuse corresponding to the desired bit is blown by a laser, and the calculated value is set.
The setting means decodes data determined by the fuse state of the fuse circuit, thereby generating a control signal and outputting the control signal to the delay monitoring means.
In the delay monitoring means, the number of stages of the element row can be switched according to a control signal indicating the configuration information set in the setting means. As a result, the characteristic of the delay monitor is adjusted to be substantially the same as the characteristic of the critical path of the target circuit.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
[0023]
First embodiment
FIG. 1 is a block diagram showing a first embodiment of a semiconductor device according to the present invention.
[0024]
As shown in FIG. 1, the semiconductor device 10 includes a target circuit (TGT) 11, a replica circuit (RPLC) 12 as delay monitoring means, a delay detection circuit (DLDET) 13, a power supply voltage control circuit (PWRCTL) 14, and A replica control circuit (PRLCTL) 15 as setting means is configured.
[0025]
The target circuit 11 controls the power supply voltage V_DDAnd a semiconductor circuit (LSI) having a transmission path, for example, including a DSP or CPU, and other logic circuits.
[0026]
The replica circuit 12 has a plurality of delay elements having a delay component that causes a signal propagation delay inside the target circuit 11, and the power supply voltage control circuit 14 controls the power supply voltage V_DDIs supplied.
The replica circuit 12 switches the configuration of the delay element array based on the control signal SADJ including the configuration information CNF set in the replica control circuit 15, and inputs the reference signal SIN having a predetermined cycle to the switched delay element array. The reference signal after propagation is output to the delay detection circuit 13 as a signal S12.
[0027]
FIG. 2 is a circuit diagram illustrating a specific configuration example of the replica circuit according to the present embodiment.
[0028]
As shown in FIG. 2, the replica circuit 12 includes a gate element column 121 whose configuration can be adjusted (switchable) and a wiring delay column 1422.
[0029]
The gate element row 121 has a plurality of gate elements 1211-1, 1211-2, 1211-3,..., 1211-n and a selector 1212 connected in series to the input of the reference signal SIN.
Each output terminal of each of the gate elements 1211-1 to 14211-n is connected to the selector 1212, and based on a control signal SADJ from the replica control circuit 15, any one of the outputs of the gate elements 1211-1 to 1211-n is output. Alternatively, the reference signal SIN is selected and output.
[0030]
As described above, the replica circuit 12 can switch the number of stages of the element row according to the control signal SADJ indicating the configuration information set in the replica control circuit 15, and the characteristics of the replica circuit 12 are different from those of the critical path of the target circuit 11. It is possible to adjust to the same characteristics.
[0031]
Here, a gate element has been described as an example of a delay element constituting the replica circuit 12. However, the present invention is not limited to this. For example, a configuration in which a gate element row and a wiring element row are combined and other factors of signal delay inside the LSI Further delay elements may be added.
[0032]
The delay detection circuit 13 detects a delay time of the signal S12 transmitted through the replica circuit 12 based on the reference signal SIN, and outputs a detection signal (instruction signal) S13 to the power supply voltage control circuit 14.
The delay detection signal 13 compares, for example, the phase of the reference signal SIN with the phase of the delay signal S12 of the replica circuit 12. When the delay signal S12 lags behind the reference signal SIN by one cycle or more, the power supply voltage V_DDIs generated, and a detection signal S13 for instructing the power supply voltage to be higher is generated._DDThe detection signal S13 instructing to lower the threshold value is generated.
[0033]
The power supply voltage control circuit 14 controls the power supply voltage V so that the detection signal S13 from the delay detection circuit 13 indicates._DDIs adjusted and supplied to the target circuit 11 and the replica circuit 12.
[0034]
The replica control circuit 15 sets configuration information CNFG for configuring a desired delay element array in the replica circuit 12, decodes the set configuration information, and supplies the decoded configuration information to the replica circuit 12 as a control signal SADJ.
[0035]
FIG. 3 is a block diagram illustrating a configuration example of the replica control circuit 15 according to the first embodiment.
[0036]
The replica control circuit 15 includes a decoder circuit 151 and a fuse circuit 152, as shown in FIG.
[0037]
The decoder circuit 151 has a function of reading data determined by the state of the fuse of the fuse circuit 152, and generates a control signal SADJ to the replica circuit 12 by decoding the read data.
The delay characteristics of the manufactured LSI are measured in the test process, and the setting data of the replica circuit 12 adapted to the delay characteristics can be set in the fuse circuit 152.
Therefore, the setting according to the delay characteristic of each LSI can be set after manufacturing.
[0038]
FIG. 4 is a circuit diagram showing a specific configuration example of the fuse circuit according to the present embodiment.
[0039]
As shown in FIG. 4, this fuse circuit 152 is a circuit that can set an n-bit value, and includes fuses F1521-1, F1521-2,..., F1521-n, and an n-channel MOS (NMOS) transistor NT1521-1. , NT1521-2, ..., NT152-n, and latches L1521-1, L1521-2, ..., L1521-n.
In the present embodiment, the NMOS transistors NT1521-1 to NT1521-n are designed to have higher resistance than the fuses F1521-1 to F15231-n.
[0040]
One end of each of the fuses F1521-1 to F1521-n is connected to a supply line for the power supply voltage VS, and the other end is connected to the drain of each of the NMOS transistors NT1521-1 to NT1521-n. The source of NT1521-n is grounded. The gate of each of the NMOS transistors NT1521-1 to NT1521-n is connected to a supply line of a read enable signal REN by the decoder circuit 151.
The terminals G of the latches L1521-1 to L1521-n are connected to the supply line of the read enable signal REN, and the input D is connected to the other ends of the fuses F1521-1 to F1521-n and the NMOS transistors NT152-1 to NT152-n, respectively. The drains are connected to connection nodes ND1521-1 to ND1521-n.
The latches L1521-1 to L1521-n latch the data "1" of the power supply voltage VS or the data "0" of the ground level from the input D at the rising timing of the read enable signal REN to the terminal G, for example. The touch data is inverted at the falling timing and output from the terminal XQ.
[0041]
In the replica control circuit 15 having such a configuration, the read enable signal REN is supplied from the decoder circuit 151 to the fuse circuit 152, and the read operation is performed while the enable signal REN is at a high level.
When the read enable signal REN is at a high level, the NMOS transistor NT1521-m (1 ≦ m ≦ n) turns on.
At this time, when the fuse F1521-m is blown by the laser, the node ND1521-m is set to the ground level by the NMOS transistor NT1521-m. On the other hand, when the fuse F1521-m is not blown, the node ND1521-m is at the power supply voltage VS level because the fuse F1521-m has a lower resistance than the NMOS transistor NT1521-m.
In the latch L1521-m, the value of the node ND1521-m is latched when the read enable signal REN is at a high level, and the inverted signal is output.
[0042]
In the example of FIG. 4, since the fuse F1521-1 is not blown in the first bit, the node ND1521-1 is at the power supply voltage VS level, and the latch L1521-1 outputs "0".
In the second bit, since the fuse F1521-2 is blown, the node ND1521-2 is at the ground level, and the latch L1521-2 outputs "1".
In the third bit, since the fuse F1521-3 is not blown, the node ND1521-3 is at the power supply voltage VS level, and the latch L1521-3 outputs "0".
Since the fuse F1521-n is blown at the n-th bit, the node ND1521-n is at the ground level, and the latch L1521-n outputs "1".
[0043]
Next, the operation of the above configuration will be described with reference to the flowchart of FIG. FIG. 5 is a flowchart illustrating a process of setting a value as configuration information in the replica control circuit 15 according to the present embodiment.
[0044]
In the processing of FIG. 5, the following processing is performed as a part of an LSI shipping test after manufacturing the LSI.
First, in step ST1, the power supply voltage delay characteristics of the replica circuit 12 and the target circuit 11 are obtained.
Next, in step ST2, based on the power supply voltage delay characteristics acquired in step ST1, a set value at which the replica circuit 12 realizes a power supply voltage delay characteristic equivalent to that of the target circuit 11 is calculated.
Then, in step ST3, the set value calculated in step ST12 is set in the fuse circuit 152.
That is, if necessary, the fuse corresponding to the desired bit is blown by a laser, and the calculated value is set.
[0045]
In the replica control circuit 15, the read enable signal REN is supplied from the decoder circuit 151 to the fuse circuit 152, and the read operation is performed while the enable signal REN is at a high level.
The decoder circuit 151 decodes data determined by the state of the fuse in the fuse circuit 152, thereby generating a control signal SADJ and outputting it to the replica circuit 12.
[0046]
In the replica circuit 12, the number of stages in the element row can be switched according to the control signal SADJ indicating the configuration information set in the replica control circuit 15. Thereby, the characteristics of the replica circuit 12 are adjusted to substantially the same characteristics as the characteristics of the critical path of the target circuit 11.
In the replica circuit 12, the reference signal SIN having a predetermined period is propagated to the switched delay element array, and the propagated reference signal is output to the delay detection circuit 13 as the delay signal S12.
[0047]
In the delay detection circuit 13, the phases of the reference signal SIN and the delay signal S12 of the replica circuit 12 are compared. As a result of the comparison, when the delay signal S12 is delayed by one cycle or more from the reference signal SIN, the power supply voltage V_DDIs generated, and a detection signal S13 for instructing the power supply voltage to be higher is generated._DDIs generated and output to the power supply voltage control circuit 14.
[0048]
Then, in the power supply voltage control circuit 14, the power supply voltage V_DDIs adjusted and supplied to the target circuit 11 and the replica circuit 12.
[0049]
As described above, according to the first embodiment, the function of reading data determined by the state of the fuse of the fuse circuit 152 is provided, and the control signal to the replica circuit 12 is provided by decoding the read data. A replica control circuit 15 having a decoder 151 for generating SADJ and a control signal SADJ indicating configuration information set in the replica control circuit 15 can switch the number of stages of the element row, and can set the delay characteristic of the critical path of the target circuit 11 Since the replica circuit 12 that can be adjusted to the same characteristics as the characteristics is provided, it is possible to cope with a change in variation in characteristics due to manufacturing after manufacturing the LSI.
Further, it is possible to cope with a change in characteristics due to a change in a manufacturing process due to manufacturing after the LSI is manufactured, and it is possible to change a delay value of a delay element after manufacturing an LSI chip.
Further, there is no need to change the software for setting the value, and the same software can be used.
Further, an excessive margin setting can be prevented, and when the margin is smaller than expected, a malfunction can be prevented by increasing the setting.
Furthermore, the function can be disabled when tracking can no longer be obtained.
[0050]
Second embodiment
FIG. 6 is a diagram for explaining a second embodiment of the semiconductor device according to the present invention.
[0051]
The second embodiment is different from the first embodiment in that a nonvolatile memory 153 is provided in the replica control circuit 15A instead of providing a fuse circuit.
[0052]
Also in the second embodiment, the manufactured LSI can measure the delay characteristics in the test process, and write the setting data of the replica circuit adapted to the delay characteristics to the nonvolatile memory 153.
Therefore, the setting according to the delay characteristic of each LSI can be set after manufacturing.
[0053]
In the replica control circuit 15A, the decoder circuit 151 has a function of reading data from the nonvolatile memory 153, and generates a control signal SADJ to the replica circuit 12 by decoding the read data.
The value setting procedure in the second embodiment is similar to the procedure of the flowchart in FIG. 5 described in the first embodiment. However, the set value calculated in step ST2 is written to the nonvolatile memory 153 in step ST3.
[0054]
According to the second embodiment, the same effects as those of the above-described first embodiment can be obtained.
[0055]
Third embodiment
FIG. 7 is a diagram for explaining a third embodiment of the semiconductor device according to the present invention.
[0056]
The difference of the third embodiment from the first embodiment is that the replica control circuit 15B has a register 154 in addition to the decoder circuit 151B and the fuse circuit 152. In this case, the fuse circuit 152 forms a correction value setting unit.
[0057]
In the replica control circuit 15B according to the third embodiment, the decoder circuit 151B has a function of reading data determined by the state of the fuse circuit 152, and stores the data in the register 154 according to the data read from the fuse circuit 152. The control signal SADJ to the replica circuit 12 is generated by correcting the decoded data and decoding.
[0058]
In the third embodiment, the delay characteristics of a certain number of samples are measured at the beginning of shipment, and data determined to be appropriate at that time is stored in the register 154.
Thereafter, in the test process, the LSI manufactured at the time of manufacture and shipment measures delay characteristics, and if the delay characteristics differ from the initially assumed delay characteristics, a correction value is set in the fuse 152.
Therefore, the setting according to the delay characteristic of each LSI can be set after manufacturing.
[0059]
FIG. 8 is a flowchart for explaining a process of setting a value as configuration information in the replica control circuit 15B according to the third embodiment.
[0060]
In the processing of FIG. 8, the following processing is performed as a part of an LSI shipping test after manufacturing the LSI.
First, in step ST11, a value written from software is written into the register 154.
Next, in step ST12, the power supply voltage delay characteristics of the replica circuit 12 and the target circuit 12 are obtained.
In step ST13, based on the power supply voltage delay characteristics obtained in step ST12, it is determined whether or not the replica circuit 12 has realized the same power supply voltage delay characteristics as the target circuit 11, and in step ST11, the register 154 is determined. It is determined whether the set value written in is valid.
Then, if the set value is appropriate, the process ends here.
If it is determined in step ST13 that the set value is not appropriate and correction is necessary, an appropriate correction value is calculated based on the power supply voltage delay characteristics of the replica circuit 12 and the target circuit 11 acquired in step ST14. I do.
Then, in step ST15, the set value calculated in step ST14 is set in the fuse circuit 152.
That is, if necessary, the fuse corresponding to the desired bit is blown by a laser, and the calculated value is set.
[0061]
In the replica control circuit 15B, the read enable signal REN is supplied from the decoder circuit 151B to the fuse circuit 152, and the read operation is performed while the enable signal REN is at a high level.
The decoder circuit 151B decodes the data determined by the fuse state of the fuse circuit 152, corrects the data stored in the register 154 based on the decoded data, decodes the corrected data, and outputs a control signal SADJ to the replica circuit 12. Is generated.
[0062]
According to the third embodiment, the same effects as those of the above-described first embodiment can be obtained.
That is, it is possible to cope with a change in variation in characteristics due to manufacturing after manufacturing the LSI.
Further, it is possible to cope with a change in characteristics due to a change in a manufacturing process due to manufacturing after the LSI is manufactured, and it is possible to change a delay value of a delay element after manufacturing an LSI chip.
Further, there is no need to change software for setting a value in a register, and the same software can be used.
Further, an excessive margin setting can be prevented, and when the margin is smaller than expected, a malfunction can be prevented by increasing the setting.
Furthermore, the function can be disabled when tracking can no longer be obtained.
[0063]
Fourth embodiment
FIG. 9 is a diagram for explaining a fourth embodiment of the semiconductor device according to the present invention.
[0064]
The fourth embodiment is different from the third embodiment in that a nonvolatile memory 153C is provided in the replica control circuit 15C instead of providing a fuse circuit.
[0065]
Also in the fourth embodiment, the delay characteristics of a certain number of samples are measured at the beginning of shipping, and data determined to be appropriate at that time is stored in a register.
Thereafter, in the test process, the LSI manufactured at the time of manufacture and shipment measures the delay characteristics, and if the delay characteristics differ from the initially assumed delay characteristics, writes the correction value into the nonvolatile memory 153C.
Therefore, the setting according to the delay characteristics of each LSI can be set after manufacturing.
[0066]
In the replica control circuit 15C, the decoder circuit 151B has a function of reading data from the nonvolatile memory 153C, and corrects and decodes the data stored in the register 154 according to the data read from the nonvolatile memory 153C. A control signal SADJ for the replica circuit 12 is generated.
The value setting procedure in the fourth embodiment is similar to the procedure in the flowchart of FIG. 8 described in the third embodiment. However, the set value calculated in step ST14 is written to the nonvolatile memory 153C in step ST15.
[0067]
According to the fourth embodiment, it is possible to obtain the same effect as that of the third embodiment described above.
[0068]
Fifth embodiment
FIG. 10 is a block diagram showing a fifth embodiment of the semiconductor device according to the present invention.
[0069]
The fifth embodiment is different from the first to fourth embodiments in that a fixed power supply voltage V_DDA fuse circuit 16 is provided as second setting means capable of setting data (invalidation data) for instructing the generation of the signal S12, and the delay detection circuit 13D detects the delay time of the signal S12 transmitted through the replica circuit 12. In addition to the function of generating the power supply voltage instruction signal S13, the LSI has a function of reading data (invalidation signal) determined by the state of the fuse circuit 16, and the LSI operates according to the data read from the fuse circuit 16. It also has a function of generating an instruction signal S13 of a possible power supply voltage.
In the fifth embodiment, the power supply voltage control circuit 14 receiving the instruction signal S13 corresponding to the invalidation signal_DDIs stopped based on the result of monitoring, and the fixed value of the power supply voltage V_DDSupply.
In the fifth embodiment, the replica circuit 12 configures a first setting unit, and the delay detection circuit 13D and the power supply voltage control circuit 14 configure a power supply voltage control function.
[0070]
FIG. 11 is a flowchart illustrating a process of setting configuration information and a value for setting a power supply voltage in the replica control circuit and the fuse circuit according to the fifth embodiment.
[0071]
The process of FIG. 11 is performed as a part of an LSI shipping test after manufacturing the LSI.
First, in step ST21, the power supply voltage delay characteristics of the replica circuit 12 and the target circuit 11 are obtained.
Here, for example, in the case where the replica control circuit 15 is the third embodiment or the fourth embodiment, a value written from software is written into a register, and then a power supply voltage delay characteristic is obtained.
Next, in step ST22, it is determined from the obtained power supply voltage delay characteristics of the replica circuit 12 and the target circuit 11 whether the operation of the LSI can be guaranteed by checking the set value and the operation of the LSI.
In the case where the replica control circuit is the third embodiment or the fourth embodiment, a correction value is calculated, and it is determined whether or not the operation of the LSI can be guaranteed within a settable correction value range.
If it is determined that the operation cannot be guaranteed, invalidation data indicating this is set in the fuse circuit 16 in step ST23.
[0072]
In the fifth embodiment, in the LSI manufactured at the time of manufacture and shipment, the delay characteristic is measured in the test process, and the delay characteristic differs from the initially assumed delay characteristic, and the setting of the replica circuit 12 is updated. If the operation of the LSI alone cannot be guaranteed, the operation of the LSI can be guaranteed by setting data indicating this to the fuse circuit 16.
[0073]
Sixth embodiment
FIG. 12 is a block diagram showing a sixth embodiment of the semiconductor device according to the present invention.
[0074]
The sixth embodiment is different from the fifth embodiment in that a nonvolatile memory 17 is provided instead of the fuse circuit 16.
[0075]
In the sixth embodiment, the delay detection circuit 13E detects the delay time of the signal S12 propagated through the replica circuit 12, and detects the variable power supply voltage V_DDAn instruction signal S13 for instructing generation is generated.
In addition, the delay detection circuit 13E has a function of reading data from the nonvolatile memory 17, and according to the data read from the nonvolatile memory 17, a fixed power supply voltage V at which the LSI can operate._DDIt also has a function of generating an instruction signal S13 for instructing generation.
In an LSI manufactured at the time of manufacture and shipment, the delay characteristic is measured in the test process, and the delay characteristic is different from the delay characteristic assumed at the beginning, and the operation of the LSI cannot be guaranteed only by updating the setting of the replica circuit 12. In such a case, the operation of the LSI can be guaranteed by writing data indicating this to the nonvolatile memory 17.
[0076]
The value setting procedure in the sixth embodiment is similar to the procedure of the flowchart in FIG. 11 described in the fifth embodiment. However, as a result of the determination in step ST22, data indicating that the operation of the LSI cannot be guaranteed is written to the nonvolatile memory 17 in step ST23.
[0077]
According to the sixth embodiment, it is possible to obtain the same effects as those of the fifth embodiment described above.
[0078]
【The invention's effect】
As described above, according to the present invention, it is possible to respond to a change in variation in characteristics due to manufacturing after manufacturing LSI.
Further, it is possible to cope with a change in characteristics due to a change in a manufacturing process due to manufacturing after the LSI is manufactured, and it is possible to change a delay value of a delay element after manufacturing an LSI chip.
Further, there is no need to change software for setting a value in a register, and the same software can be used.
Further, an excessive margin setting can be prevented, and when the margin is smaller than expected, a malfunction can be prevented by increasing the setting.
Furthermore, the function can be disabled when tracking can no longer be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a semiconductor device according to the present invention.
FIG. 2 is a circuit diagram showing a specific configuration example of a replica circuit according to the embodiment.
FIG. 3 is a block diagram illustrating a configuration example of a replica control circuit according to the first embodiment.
FIG. 4 is a circuit diagram showing a specific configuration example of a fuse circuit according to the embodiment.
FIG. 5 is a flowchart illustrating a process of setting a value as configuration information in the replica control circuit according to the first embodiment.
FIG. 6 is a diagram for explaining a second embodiment of the semiconductor device according to the present invention.
FIG. 7 is a diagram for explaining a third embodiment of the semiconductor device according to the present invention.
FIG. 8 is a flowchart illustrating a process of setting a value as configuration information in a replica control circuit according to the third embodiment.
FIG. 9 is a view for explaining a fourth embodiment of the semiconductor device according to the present invention.
FIG. 10 is a block diagram showing a fifth embodiment of the semiconductor device according to the present invention.
FIG. 11 is a flowchart illustrating a process of setting configuration information and a value for setting a power supply voltage in a replica control circuit and a fuse circuit according to a fifth embodiment;
FIG. 12 is a block diagram showing a sixth embodiment of the semiconductor device according to the present invention.
[Explanation of symbols]
10, 10A to 10E: semiconductor device, 11: target circuit (TGT), 12: replica circuit (RPLC), 13, 13D, 13E: delay detection circuit (DLDET), 14: power supply voltage control circuit (PWRCTL), 15, 15A to 15D: replica control circuit (ROCTL), 16: fuse circuit, 17: nonvolatile memory, 1211: gate element row, 1211-1 to 1211-n: gate element, 1212: selector, 151, 151B: decoder circuit, 152: fuse circuit; 153, 153C: nonvolatile memory; 154: register.

Claims (11)

A semiconductor device having delay monitoring means for grasping a critical path delay characteristic of a target circuit,
The delay monitoring means includes:
Including a delay component causing a signal propagation delay inside the target circuit, having a plurality of delay elements forming a delay element row according to the supplied control signal,
further,
Desirable configuration information for forming the delay element array can be set after manufacturing the semiconductor device, and the setting device generates the control signal based on the set data and outputs the control signal to the delay monitoring device. 2. The semiconductor device according to claim 1, wherein said setting means includes a fuse circuit for determining data, reads data determined by a fuse state of said fuse circuit, and generates said control signal according to the read data. 2. The semiconductor device according to claim 1, wherein said setting means includes a non-volatile memory to which data can be written from the outside, reads the data written in said non-volatile memory, and generates said control signal according to the read data. A semiconductor device having delay monitoring means for grasping a critical path delay characteristic of a target circuit,
The delay monitoring means includes:
Including a delay component causing a signal propagation delay inside the target circuit, having a plurality of delay elements forming a delay element row according to the supplied control signal,
further,
Desired configuration information for forming the delay element array can be set after the semiconductor device is manufactured, and has setting means for generating the control signal based on the set data and outputting the control signal to the delay monitoring means,
The setting means,
A register in which the configuration information is set;
A correction value setting unit that can set a correction value of setting data of a register. The correction value setting means of the setting means includes a fuse circuit for determining a correction value,
The setting means,
5. The semiconductor device according to claim 4, wherein data determined by a fuse state of the fuse circuit is read, setting data of the register is corrected according to the read data, and the control signal is generated based on the corrected data. The correction value setting means of the setting means includes a nonvolatile memory capable of externally writing a correction value,
The setting means,
5. The semiconductor device according to claim 4, wherein a correction value written in said non-volatile memory is read out, the setting data of said register is corrected according to the read data, and said control signal is generated based on the corrected data. Semiconductor having delay monitor means for grasping a critical path delay characteristic of a target circuit, and a power supply voltage control function for controlling a value of a power supply voltage supplied to the target circuit based on a delay monitor result of the delay monitor means A device,
A semiconductor device having setting means for disabling the power supply voltage control function and setting data for supplying a fixed power supply voltage to the target circuit after manufacturing the semiconductor device. 8. The semiconductor device according to claim 7, wherein said setting means includes a fuse circuit for determining data, reads data determined by a fuse state of said fuse circuit, and generates an invalidation signal according to the read data. 8. The semiconductor device according to claim 7, wherein said setting means includes a non-volatile memory to which data can be externally written, reads the data written in said non-volatile memory, and generates an invalidation signal according to the read data. Semiconductor having delay monitor means for grasping a critical path delay characteristic of a target circuit, and a power supply voltage control function for controlling a value of a power supply voltage supplied to the target circuit based on a delay monitor result of the delay monitor means A device,
The delay monitoring means includes:
Including a delay component causing a signal propagation delay inside the target circuit, having a plurality of delay elements forming a delay element row according to the supplied control signal,
further,
First setting means for setting desired configuration information for forming the delay element array after manufacturing the semiconductor device, generating the control signal based on the set data, and outputting the control signal to the delay monitoring means;
And a second setting unit that can set data for disabling the power supply voltage control function and supplying a fixed power supply voltage to the target circuit after manufacturing the semiconductor device. Semiconductor having delay monitor means for grasping a critical path delay characteristic of a target circuit, and a power supply voltage control function for controlling a value of a power supply voltage supplied to the target circuit based on a delay monitor result of the delay monitor means A device,
The delay monitoring means includes:
Including a delay component causing a signal propagation delay inside the target circuit, having a plurality of delay elements forming a delay element row according to the supplied control signal,
further,
First setting means for setting desired configuration information for forming the delay element array after manufacturing the semiconductor device, generating the control signal based on the set data, and outputting the control signal to the delay monitoring means;
A second setting unit that can set data for disabling the power supply voltage control function and supplying a fixed power supply voltage to the target circuit after manufacturing the semiconductor device;
The first setting means includes:
A register in which the configuration information is set;
A correction value setting unit that can set a correction value of setting data of a register.

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