KR20010066212A - Fuse Program Circuit and Programming Method, Delay Circuit having the Fuse Program Circuit and Dely Control Method using the same - Google Patents

Abstract

PURPOSE: A fuse program circuit and a programming method and a delay circuit including the fuse program circuit and a method for controlling delay using the delay circuit is provided to change the value preset during design process. CONSTITUTION: The fuse program circuit(20) includes a fuse, the first current source(21), a current path(22) and an output controller(24). The fuse program circuit generates a program signal with response to the first control signal. The first current source is driven with response to the second control signal and supplies current to the first terminal of the fuse. The current path is driven with response to the first control signal and forms a current path between the second terminal of the fuse and a ground voltage. The output controller receives the signal from the second terminal of the fuse and generates the program signal with response to the first control signal. The fuse is further electrically cut by a current bigger than a reference value.

Description

Fuse program circuit and programming method and delay circuit having fuse program circuit and delay control method using same {Fuse Program Circuit and Programming Method, Delay Circuit having the Fuse Program Circuit and Dely Control Method using the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit, and more particularly, to a fuse program circuit including a fuse and generating a predetermined program signal, a program signal generating method using the same, and a delay circuit including the fuse program circuit and a delay control method using the same. .

In a semiconductor device, it is sometimes necessary to change a value set at the time of designation at a semi-finished product or a later stage without changing the design. For example, when a bad memory cell occurs in a semiconductor memory device, a method of replacing the defective memory cell with a redundancy cell is mainly used. In this case, programming to change an address corresponding to the bad memory cell to an address of the redundancy cell is necessary. Such programming is mainly performed using a program circuit inside the semiconductor device. In general, a fuse programming method in which a fuse is burned and cut using a fuse program circuit having a conventional fuse that can be cut by a laser is used.

1 is a view showing a fuse program circuit according to the prior art. Referring to this, the fuse program circuit according to the prior art includes a fuse 11 that can be cut by a laser. Whether the program signal FOUT, which is an output signal of the fuse program circuit of FIG. 1, is activated is determined by whether the fuse 11 is disconnected. That is, when the fuse 11 is not cut, the program signal FOUT is inactivated to a low level, and when the fuse 11 is cut off, the program signal FOUT is activated to a high level. By the way, since the fuse 11 cut by the laser must be cut at the semi-finished stage in the wafer state, programming by the fuse program circuit of FIG. 1 must also be made in the wafer state. Therefore, the fuse program circuit according to the prior art has a disadvantage in that programming is impossible in the finished product stage after assembly. Programming at the end-product level allows chip characteristics to be tuned on a commercialized chip basis, thereby significantly improving chip performance and yield.

On the other hand, the synchronous semiconductor device operates in synchronization with a reference clock signal input from the outside. Accordingly, there is a need for a circuit that receives an external reference clock signal and generates an internal clock whose frequency and phase are synchronized with the reference clock signal. One of such internal clock generating circuits is a delay circuit such as a delay lock loop. Internal circuits of the semiconductor device including the delay circuit operate based on an internal clock signal generated in the delay circuit. That is, the internal clock signal output from the final stage of the delay circuit is distributed to the entire semiconductor device and provided as a clock signal necessary for circuit operation.

By the way, the output signal of the delay circuit is provided to various circuits inside the semiconductor device and thus has a very large output load. Due to this large output load, the delay circuit can consume a lot of power. Therefore, in order to minimize unnecessary power consumption, the semiconductor device subdivides the operation mode of the delay circuit according to the operation of the semiconductor device, and provides different output signals according to each mode. At this time, in order for the internal circuits of the semiconductor device to operate correctly, the output signals of the delay circuits acting as input signals must exactly match phase and frequency. If the phase and frequency of the output signals of the delay circuit do not exactly match, the semiconductor device cannot be controlled accurately. Ultimately, the operating speed of the entire semiconductor device is significantly lowered or malfunctions are caused.

One way to avoid the above problem is to adjust the delay time by programming a delay control signal in a delay circuit having a delay control unit controlled by a predetermined delay control signal. However, in the related art, a fuse program circuit including a laser cuttable fuse as shown in FIG. 1 is used for programming a delay control signal. Therefore, as described above, since the cutting of the fuse 11, which is cut by the laser, must be performed in the semi-finished step of the wafer state, the programming of the delay control signal by the fuse program circuit of Fig. 1 must also be made in the wafer state. Therefore, there is a disadvantage that the delay time of the delay circuit cannot be adjusted in the finished product stage after assembly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fuse program circuit capable of changing a set value at the time of design by predetermined programming in an assembled semiconductor chip state without changing the design in a semiconductor manufacturing process.

Another object of the present invention is to provide a programming method using the fuse program circuit.

It is still another object of the present invention to provide a delay circuit capable of adjusting the delay time by predetermined programming in an assembled semiconductor chip state without a design change in a semiconductor manufacturing process.

Still another object of the present invention is to provide a delay control method of minimizing skew between a plurality of delay signals using the delay circuit.

1 is a view showing a fuse program circuit according to the prior art.

2 illustrates a fuse program circuit according to an exemplary embodiment of the present invention.

3 illustrates a fuse program circuit according to another exemplary embodiment of the present invention.

4 is a timing diagram of main signals in the program mode of the fuse program circuit of FIG.

5 is a flowchart illustrating a programming method using the fuse program of FIG. 2.

6 is a diagram illustrating a delay circuit having a fuse program according to an exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a plurality of delay signal generation circuits for generating a plurality of delay signals as a delay circuit including a fuse program circuit according to another exemplary embodiment of the present invention.

FIG. 8 is a flowchart showing a delay control method using the multiple delay signal generation circuit of the present invention shown in FIG.

9 is a timing diagram of key signals in a test mode of the circuit of FIG.

FIG. 10 is a timing diagram of major signals when simultaneously programming using a plurality of fuse program circuits in the circuit of FIG. 7.

FIG. 11 is a plan view illustrating a portion of a fuse program circuit including a conventional fuse and an electrical fuse, according to another embodiment of the present invention.

The present invention for achieving the above object of the present invention relates to a fuse program circuit for generating a program signal in response to the first predetermined control signal. A fuse program circuit according to a preferred embodiment includes a fuse; A first current source driven in response to a second control signal to supply current to the first terminal of the fuse; A current path portion forming a current path between the second terminal of the fuse and a ground voltage in response to the first control signal; And an output control unit which receives a signal of a second terminal of the fuse and generates the program signal in response to the first control signal.

In addition, the present invention for achieving another object of the present invention relates to a programming method including a fuse, the fuse program circuit for generating a program signal in response to the predetermined first control signal. A programming method of the present invention according to a preferred embodiment comprises the steps of A) selecting a program mode; B) applying the first control signal; C) the fuse is cut; And D) generating the program signal in response to the first control signal.

In addition, the present invention for achieving another object of the present invention relates to a delay circuit for delaying a received input signal with a predetermined delay time. According to a preferred embodiment of the present invention, a delay circuit includes: a delay unit configured to delay the input signal by a predetermined delay path to generate a delay signal; At least one delay adjuster connected to the delay path of the delay unit, the delay adjuster controlling the delay time in response to a predetermined delay control signal; And a fuse program circuit for programming the delay control signal by generating a program signal in response to a first predetermined control signal, the fuse program circuit including a fuse electrically cut in response to the first control signal. do.

The present invention for achieving another object of the present invention is provided with a plurality of delay circuits of the present invention, and between the delay signals of the plurality of delay signal generation circuits for generating a plurality of delayed signals with respect to an input signal. A delay control method for minimizing skew is provided. A delay control method of the present invention according to a preferred embodiment comprises the steps of A) measuring actual skews between the delay signals by the delay circuit in a test mode; B) selecting an address signal that generates the smallest skew of the measured skews; C) executing programming using the selected address signal.

By the fuse program circuit of the present invention, in a semiconductor chip state assembled without a design change in a semiconductor manufacturing process, a set value at design time can be changed only by programming. Therefore, the characteristics of the semiconductor chip can be optimized. In addition, by the delay circuit and the delay control method of the present invention, skew between a plurality of delay signals with respect to one input signal can be minimized without changing the design.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, for convenience of description, signals and components that perform the same roles throughout the drawings are denoted by the same reference numerals and reference numerals.

2 illustrates a fuse program circuit according to an exemplary embodiment of the present invention. Referring to this, the fuse program circuit 20 according to the preferred embodiment includes a fuse R0, a first current source 21, a current path unit 22, and an output controller 24.

The first current source 21 is driven in response to the second control signal to supply current to the first terminal 25a of the fuse R0. The first current path unit 22 forms a current path between the second terminal 25b of the fuse R0 and the ground voltage GND in response to the first control signal. The output control unit 24 receives a signal of the second terminal 25b of the fuse R0 and generates a program signal FOUT in response to the first control signal.

Preferably, the fuse R0 is a fuse which is electrically cut when a current of a reference amount or more flows. In a preferred embodiment of the present invention, the first control signal is an address signal ADDR and the second control signal is a power-up signal PWUP. Here, the address signal ADDR is a signal set to select a signal (not shown) to be programmed. The power-up signal PWUP is a signal that increases for a predetermined time and is maintained at a low level by the power supply voltage VCC applied to the semiconductor device.

In the present embodiment, the first current source 21 receives a power-up (PWUP) signal to the gate terminal, the source terminal to the power supply voltage VCC, and the drain terminal to the first terminal 25a of the fuse R0. ) Is a first PMOS transistor MP1. Accordingly, the first PMOS transistor MP1 is turned on when the power-up signal PWUP is at a low level, and supplies a current from the power supply voltage VCC to the first terminal 25a of the fuse R0.

The current path unit 22 includes a first NMOS transistor MN1 and a transmitter 221. In the first NMOS transistor MN1, a drain terminal is connected to the second terminal 25b of the fuse R0, and a source terminal is connected to the ground voltage GND, and is turned on in response to the address signal ADDR. The transmitter 221 transmits the address signal ADDR to the gate terminal of the first NMOS transistor MN1 in the program mode. The transmitter 221 is implemented as a transmission gate TG1 in this embodiment. Here, the program mode is a mode in which programming is executed and is a period in which the program mode signal PROG is activated. In the program mode, when the address signal ADDR is activated to a high level, the first NMOS transistor MN1 is turned on to form a current path from the fuse R0 to the ground voltage GND. Preferably, the current path section 22 further includes a second NMOS transistor MN2. When the second NMOS transistor MN2 is other than the program mode, the gate terminal of the first NMOS transistor MN1 is floating by connecting the gate terminal of the first NMOS transistor MN1 with a ground voltage. Prevent it.

The output control unit 24 includes an operation unit 241 and a logic sum unit 243. The calculator 241 receives the signal of the second terminal 25b of the fuse R0 and the power-up signal PWUP to generate the fuse signal FS. The logical sum unit 243 generates the program signal FOUT by logically combining the fuse signal FS and the address signal ADDR. In the present embodiment, the calculation unit 241 is composed of the negative logic gate NOR1 and the third NMOS transistor MN3. A power-up signal PWUP is input to one input terminal of the negative logic gate NOR1. The signal of the second terminal 25b of the fuse R0 is input to the input terminal on the other side, and they are negatively logically outputted as the fuse signal FS. The third NMOS transistor MN3 is turned on in response to the activation of the fuse signal FS, and connects the other terminal of the negative logic gate NOR1 to the ground voltage.

The logic sum unit 243 is constituted by a negative logic gate NOR2 and an inverter INV. The fuse signal FS is input to one input terminal of the logic sum unit 243, and the address signal ADDR is input to the other input terminal. Therefore, if either of the fuse signal FS and the address signal ADDR is high level, the logic sum unit 243 outputs the high level program signal FOUT.

Preferably, the fuse program circuit 20 further includes a current sink for discharging the current of the second terminal 25b of the fuse R0 in response to a power-up (PWUP) signal at the initial stage of power-up. In the present embodiment, the current sink receives the power-up signal PWUP as the gate terminal, the drain terminal is connected to the second terminal 25b of the fuse R0, and the source terminal is connected to the ground voltage GND. 4 NMOS transistor MN4.

3 illustrates a fuse program circuit according to another exemplary embodiment of the present invention. 3, the fuse program circuit of FIG. 3 further includes a second current source 32 in the fuse program circuit 20 of FIG. 2. The second current source 32 supplies the current to the first terminal 25a of the fuse R0 in the program mode so that the current flowing through the fuse R0 can be equal to or greater than the reference amount. In the present embodiment, the second current source 32 receives the inverted signal (/ PROG) signal of the program mode signal to the gate terminal, the source terminal to the power supply voltage VCC and the drain terminal to the first of the fuse R0. It is the 2nd PMOS transistor MP2 connected to the terminal 25a.

Referring to the operation of the fuse program circuit 20 according to an embodiment of the present invention as a whole.

First, when the power supply voltage VCC is applied to the fuse program circuit, the power-up signal PWUP increases with the power supply voltage VCC and then falls to a low level. Before entering the program mode, both the program mode signal PROG and the address signal ADDR are deactivated to the low level. Therefore, the transfer unit 221 is turned off, the second NMOS transistor MN2 is turned on, and the gate terminal of the first NMOS transistor MN1 becomes low level. Therefore, the first NMOS transistor MN1 is turned off. In addition, the first PMOS transistor MP1 is turned on by the low-level power-up signal PWUP, and the fourth NMOS transistor MN4 is turned off. Therefore, since no current path from the power supply voltage VCC to the ground voltage GND is formed through the fuse R0, no current flows through the fuse RO. Therefore, the fuse R0 is not electrically cut. Since the second terminal 25b of the fuse R0 is connected to the power supply voltage VCC through the fuse R0 and the first PMOS transistor MP1, the second terminal 25b is at a high level. The calculator 241 receives the signal of the second terminal 25b of the high level fuse R0 and the low level power-up signal PWUP, and outputs the low level fuse signal FS. Therefore, the program signal FOUT is deactivated to the low level.

On the other hand, in the program mode, both the program mode signal PROG and the address signal ADDR are activated at a high level. 4 is a timing diagram of main signals in a program mode of a fuse program circuit according to an exemplary embodiment of the present invention. Referring to this, the program mode signal PROG is activated for the time T3 and the address signal ADDR is activated for the time 'T1 + T2'. When both the program mode signal PROG and the address signal ADDR are activated, the transfer unit 221 is turned on, the second NMOS transistor MN2 is turned off, and the gate terminal of the first NMOS transistor MN1 is turned off. It goes high during 'T1 + T2' time. Therefore, the first NMOS transistor MN1 is turned on. In addition, the first PMOS transistor P1 is turned on by the low-level power-up signal PWUP, and the fourth NMOS transistor MN4 is turned off. Therefore, a current path is formed from the power supply voltage VCC to the ground voltage GND via the fuse R0, and a predetermined current flows through the fuse RO.

If the intensity of the current flowing at this time is equal to or greater than the reference amount, the fuse R0 is electrically disconnected after the time T1, and the second terminal 25b of the fuse R0 is connected to the ground voltage GND through the second NMOS transistor MN2. ) Is completely low level. The calculator 241 receives the signal of the second terminal 25b of the low-level fuse R0 and the low-level power-up signal PWUP, and outputs a high-level fuse signal FS. Therefore, the program signal FOUT is activated to the high level. Since the third NMOS transistor MN3 is turned on by the high level fuse signal FS, the fuse signal FS is kept at the high level, and the program signal FOUT is also activated at the high level. As a result, programming is performed, and the program signal FOUT is not changed even after the address signal ADDR is changed.

The total time required for programming is T3 time at which the program mode signal PROG is active, but the actual time for programming is T1, and the T2 time is extra time.

However, when programming is performed, since the program signal FOUT cannot be changed later, it is necessary to test the semiconductor device using the activated program signal FOUT before programming. In the test mode, the program mode signal PROG is inactivated and the address signal ADDR is activated. Therefore, the transfer unit 221 is turned off, the second NMOS transistor MN2 is turned on, and the gate terminal of the first NMOS transistor MN1 becomes low level. Therefore, the first NMOS transistor MN1 is turned off. Since the current path from the power supply voltage VCC to the ground voltage GND through the fuse R0 is not formed, the fuse RO is not electrically disconnected. Since the second terminal 25b of the fuse R0 is connected to the power supply voltage VCC through the fuse and the first PMOS transistor MP1, the second terminal 25b is at a high level. The calculator 241 receives the signal of the second terminal 25b of the high level fuse R0 and the low level power-up signal PWUP, and outputs the low level fuse signal FS. The logic sum unit 243 receives the fuse signal FS at the low level and the address signal ADDR at the high level, and outputs a program signal FOUT that is activated at the high level.

In the present exemplary embodiment, a fuse program circuit for generating a program signal FOUT that is activated to a high level is described by programming, but it may be implemented as a fuse program circuit for generating a program signal FOUT to be activated to a low level.

5 is a flowchart illustrating a programming method using a fuse program circuit according to an exemplary embodiment of the present invention. First, the program mode is selected (503). The selection of the program mode is made by activating the program mode signal PROG. Then, the first control signal is applied (505). Then, a current flows through the fuse, the fuse is blown after a predetermined time (507), and a program signal (FOUT) that is activated is generated (509).

According to the fuse program circuit of the present invention and a programming method using the same, a value set at the time of designing in an assembled semiconductor chip state may be changed without changing the design in a semiconductor manufacturing process.

6 is a diagram illustrating a delay circuit including a fuse program circuit according to an exemplary embodiment of the present invention. Referring to this, the delay circuit 60 according to the preferred embodiment includes a delay unit 62, first and second delay control units 64a and 64b, and first and second fuse program circuits 66a and 66b. do.

The delay unit 62 delays the received input signal ICLK by a predetermined delay path 62n to generate the delay signal DCLK. The delay signal DCLK is a signal delayed with respect to the input signal RCLK by a predetermined delay time TD. In the present specification, for convenience of description, the delay unit 62 is implemented with two inverters INV61 and INV62. However, it is apparent to those skilled in the art that the delay unit 62 may be modified in various forms, and the number of inverters forming the inverter chain may be extended.

The first and second delay adjusting units 64a and 64b are connected to the delay path 62n of the delay unit 62, and respond to the predetermined delay control signals DCON1 and DCON2, respectively, to delay the delay time TD. To control. Preferably, the first and second delay adjusters 64a and 64b are implemented with MOS transistors. In the present specification, as illustrated in FIG. 6, the first and second delay adjusters 64a and 64b include a gate terminal connected to a delay path 62n and a first source and a second terminal respectively as source and drain terminals. The first and second PMOS transistors MPA and MPB commonly receive the delay control signals DCON1 and DCON2. When the first delay control signal DCON1 is activated, the first PMOS transistor MPA acts as a capacitor to delay the input signal, and when the first delay control signal DCON1 is deactivated, the first PMOS transistor MPA does not act as a capacitor. It does not cause a delay effect. Like the first PMOS transistor MPA, when the second delay control signal DCON2 is activated, the second PMOS transistor MPB acts as a capacitor to delay the input signal, and the second delay control signal DCON2 is applied to the second PMOS transistor MPB. When disabled, it does not act as a capacitor and does not introduce delay effects on the input signal. The first and second delay adjusters 64a and 64b may be implemented by NMOS transistors.

The first and second fuse program circuits 66a and 66b are circuits for generating the first and second delay control signals DCON1 and DCON2 in response to the first and second address signals ADDR1 and ADDR2, respectively. Since it is the same as the fuse program circuit 20 shown in FIG. 2, the detailed description thereof will be omitted.

The control register 68 may be further provided to store the program mode signal PROG and the first and second address signals ADDR1 and ADDR2.

In the delay circuit 60 of FIG. 6, the delay time TD may be adjusted according to whether the first and second delay control signals DCON1 and DCON2 are activated. The adjustment of the delay time TD according to whether the first and second delay control signals DCON1 and DCON2 are activated may be performed only by programming using the fuse program circuits 66a and 66b in the semiconductor chip state without changing the design. . Therefore, it can be adjusted to the most appropriate delay time for each semiconductor chip.

In the present embodiment, a delay circuit including two delay adjusters and a fuse program circuit is described, but it is apparent that the number of delay adjusters and fuse program circuits may be changed. As the number of delay adjusters is increased, the range of adjustable delay times TD may also increase.

FIG. 7 is a diagram illustrating a plurality of delay signal generation circuits for generating a plurality of delay signals as a delay circuit including a fuse program circuit according to another exemplary embodiment of the present invention. The multiple delay signal generation circuit of the present invention shown in FIG. 7 delays the input signal ICLK to generate three delay signals DCLK1, DCLK2, and DCLK3. The three delay signals DCLK1, DCLK2, and DCLK3 are signals input to the three circuit blocks B1, B2, and B3, respectively. The first delay circuit 72a adjusts the delay time TD1 by the delay control signals DCON1 and DCON2 generated in response to the first and second address signals ADDR1 and ADDR2, respectively. The second delay circuit 72b adjusts the delay time TD2 by the delay control signals DCON3 and DCON4 generated in response to the third and fourth address signals ADDR3 and ADDR4, respectively. The third delay circuit 72c adjusts the delay time TD3 by the delay control signals DCON5 and DCON6 generated in response to the fifth and sixth address signals ADDR5 and ADDR6, respectively. Since the first, second and third delay circuits 72a, 72b, 72c are the same as the delay circuit of the present invention described in FIG. 6, the detailed description is omitted here. The multiple delay signal generation circuit of FIG. 7 may further include a control register 78 for storing the program mode signal PROG and the first to sixth address signals ADDR1 to ADDR6.

As such, by generating and using the plurality of delay signals DCLK1, DCLK2, and DCL3 that are synchronized with one input signal ICLK, power consumption may be minimized. However, unlike setting the delay skew to 0 between the delay signals DCLK1, DCLK2, and DCL3 at this time, a process change, an external environment change, a delay path difference, or a parasitic capacitance difference due to a circuit block, etc. This may cause delay skew. The delay skew may be eliminated by the activation of the delay control signals DCON1 to DCON6 using the fuse program circuit.

FIG. 8 is a flowchart showing a delay control method using the multiple delay signal generation circuit of the present invention shown in FIG. First, in the test mode, the actual skew between the delay signals DCLK1, DCLK2, and DCLK3 by the first, second, and third delay circuits 72a, 72b, and 72c is measured (803).

9 is a timing diagram of key signals in a test mode of the circuit of FIG. Referring to this, in the test mode, the program mode signal PROG is inactivated to a low level. In this state, the first to sixth address signals ADDR1 to ADDR6 are changed to all possible combinations of high level or low level, and the actual skew between the delay signals DCLK1, DCLK2, DCLK3 is measured.

Next, a combination of the first to sixth address signals ADDR1 to ADDR6 generating the smallest value among the measured skews is found (805). Finally, programming mode is executed by activating the program mode signal PROG, setting the first to sixth address signals ADDR1 to ADDR6 in a combination that causes the smallest skew (807).

FIG. 10 is a timing diagram of major signals when simultaneously programming a plurality of delay control signals in the circuit of FIG. 7. Referring to this, the program mode signal PROG is activated, and the address signal corresponding to the delay control signal to be programmed among the first to sixth delay control signals DCON1 to DCON6 is simultaneously activated. If the first, second and sixth delay control signals DCON1, DCON2, and DCON6 are programmed to minimize the skew, the first, second and sixth address signals ADDR1, ADDR2, as shown in FIG. , ADDR6) are activated simultaneously. However, the programming of the first, second and sixth delay control signals DCON1, DCON2, and DCON6 may be performed when the program mode signal PROG is activated, and the first, second and sixth address signals ADDR1, ADDR2, By sequentially activating ADDR6), it may be executed sequentially.

As described above, the delay control method of the present invention illustrated in FIG. 8 may minimize skew between delay signals by programming using a fuse program circuit.

In the present specification, only the case where the number of delay signals is three is described, but it is obvious to those skilled in the art that the number of delay signals may be extended.

FIG. 11 is a plan view illustrating a portion of a fuse program circuit including a conventional fuse and an electrical fuse, according to another embodiment of the present invention. Referring to this, in the fuse program circuit of the present invention, a conventional fuse FUSE11 that can be cut by a laser and an electrical fuse EFUS11 that are electrically cut by a current higher than a reference amount are connected in parallel. One terminal of the normal fuse FUSE11 and the electrical fuse EFUS11 is connected to the first node N11a through the metal part MET11a, and the other terminals are connected to the second node N11b through the metal part MET11b. It is. In addition, the metal parts connecting the nodes and the fuses may be cut. Therefore, according to the convenience of the semiconductor chip developer, the other one may be selected by cutting one of the conventional fuse FUSE11 and the electrical fuse EFUS11. When the conventional fuse FUSE11 is selected, programming is possible by cutting the normal fuse FUSE11 in the wafer state, so that programming is possible in large quantities, thereby saving time in the semiconductor manufacturing process. When the electric fuse (EFUS11) is selected, since the programmable state of the chip in the finished product can be programmed, performance can be optimized for each chip and the overall yield is improved. Therefore, according to the present invention shown in Fig. 11, the choice of developers is increased.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the fuse program circuit and the programming method of the present invention, the set value at the time of design can be changed in the assembled semiconductor chip state without changing the design in the semiconductor manufacturing process. The delay circuit of the present invention can accurately control the delay time in the semiconductor chip state. In addition, by the delay circuit and the delay control method of the present invention for generating a plurality of delay signals, skew between delay signals can be minimized only by programming in a semiconductor chip state without design change.

Claims (15)

A fuse program circuit for generating a program signal in response to a first predetermined control signal, fuse; A first current source driven in response to a second control signal to supply current to the first terminal of the fuse; A current path portion forming a current path between the second terminal of the fuse and a ground voltage in response to the first control signal; And And an output controller configured to receive a signal at a second terminal of the fuse and generate the program signal in response to the first control signal. The method of claim 1, wherein the fuse A fuse program circuit which is electrically cut by a current equal to or greater than a reference amount. The method of claim 1, wherein the current path portion A first NMOS transistor electrically connected to a second terminal of the fuse, a source terminal connected to a ground voltage, and turned on in response to the first control signal; And And a transmitter configured to transmit the first control signal to a gate terminal of the first NMOS transistor in a program mode. The method of claim 3, wherein the current path portion And a second NMOS transistor for connecting the gate terminal of the first NMOS transistor to a ground voltage in a case other than the program mode. The method of claim 1, wherein the output control unit A calculator configured to receive a signal of the second terminal of the fuse and the second control signal and generate a fuse signal; And And a logic summation unit configured to generate the program signal by ORing the fuse signal and the first control signal. According to claim 1, The first control signal is an address signal, And the second control signal is a power-up signal. The method of claim 6, wherein the fuse program circuit is And a current sink for discharging a current of a second terminal of the electrical fuse in response to the power-up signal at the initial stage of power-up. The method of claim 1, wherein the fuse program circuit is And in a program mode, a second current source for supplying current to the first terminal of the fuse. A delay circuit for delaying a received input signal with a predetermined delay time, A delay unit for delaying the input signal by a predetermined delay path and generating a delay signal; At least one delay adjuster connected to a delay path of the delay unit, the delay adjuster controlling the delay time in response to a predetermined delay control signal; And A fuse program circuit for programming the delay control signal by generating a program signal in response to a first predetermined control signal, the fuse program circuit comprising a fuse electrically disconnected in response to the first control signal. Delay circuit, characterized in that. 10. The method of claim 9, wherein the fuse program circuit is The fuse; A current source driven in response to a second control signal to supply current to the first terminal of the fuse; A current path unit forming a current path between the second terminal of the fuse and a ground voltage in response to the first control signal; And And an output controller for receiving a signal at a second terminal of the fuse and generating the program signal in response to the first control signal. The method of claim 10, wherein the fuse A delay circuit characterized in that it is electrically cut by a current of a reference amount or more. The method of claim 10, The first control signal is an address signal, And the second control signal is a power-up signal. A programming method comprising a fuse program circuit comprising a fuse and generating a program signal in response to a first predetermined control signal, A) selecting a program mode; B) applying the first control signal; C) the fuse is cut; And D) generating the fuse program signal in response to the first control signal. The method of claim 13, wherein the fuse A method of generating a program signal, characterized in that it is electrically cut by a current higher than a reference amount. A delay unit for delaying an input signal by a predetermined delay path and generating a delay signal; At least one delay adjuster connected to a delay path of the delay unit, the delay adjuster controlling the delay time in response to a predetermined delay control signal; And a fuse program circuit for programming the delay control signal by generating a program signal in response to a first predetermined control signal, the fuse program circuit including a fuse electrically cut in response to the first control signal. A delay control method comprising a plurality of delay circuits for minimizing skew between the delay signals of a plurality of delay signal generation circuits for generating a plurality of delay signals delayed with respect to the input signal. A) measuring actual skews between the delay signals by the delay circuit in a test mode; B) selecting an address signal that generates the smallest skew of the measured skews; C) executing programming using the selected address signal.