JP2004171072A - Fault detecting system composed of multiprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fault detecting system composed of a multiprocessor for separating a troubled processor card with fault from a common bus even when causing fault of the common bus unrecognizable by the processor card itself. <P>SOLUTION: The processor cards 2 and 3 are connected to the common bus 4. The processor card 3 has a bus interface circuit 32 for receiving a response signal from a bus card 1 by transmitting a request signal to the bus card 1 and a power source control circuit 31 for controlling a power source of a bus interface 32 by receiving a power source control signal 5 from the bus card 1, and transmits the power source control signal from the bus card 1 when the bus interface circuit 32 causes the fault having effect on the common bus 4, and separates and cuts off the processor card 3 with fault from the common bus 4 by stopping the power source of the bus interface circuit 3 from the power source control circuit 31 of the processor card 3. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a failure detection method of a multiprocessor configuration in which a plurality of processor cards are connected to a common bus and provided with a bus arbitration circuit for arbitrating a bus transmission right of the common bus. The present invention relates to a failure detection method of a multiprocessor configuration that operates so as to be disconnected from a bus.
[0002]
[Prior art]
Conventionally, in a system including a bus card having a plurality of processor cards connected to a common bus and having a bus arbitration circuit for arbitrating the bus transmission right of the common bus, when each processor card performs data transmission on the common bus, The interface circuit transmits data by transmitting a request signal to the bus arbitration circuit and receiving a response signal from the bus arbitration circuit. If a failure occurs in the bus interface circuit and the transmission right of the common bus is maintained, other processor cards connected to the common bus cannot transmit data.
[0003]
FIG. 3 is a block diagram showing the configuration of a conventional multiprocessor configuration fault detection system. A plurality of processor cards 2 and 3 are connected to the common bus 4. The processor cards 2 and 3 have bus interface circuits 22 and 33 and are connected to the common bus 4. The bus card 1 includes a bus arbitration circuit 11 for arbitrating the bus transmission right of the common bus 4, and the bus arbitration circuit 11 is connected to the common bus 4.
[0004]
When the processors 23 and 33 in each of the processor cards 2 and 3 transmit data to the common bus 4, the bus interface circuits 22 and 32 transmit a request signal to the bus arbitration circuit 11 and a response signal from the bus arbitration circuit 11. To perform data transmission. For example, if a failure occurs in the bus interface circuit 32 of the processor card 3 and the transmission right of the common bus 4 is maintained, the other processor cards 2 connected to the common bus 4 cannot transmit data.
[0005]
If the processor 33 in the processor card 3 can detect a failure by means of a periodic access signal or the like, the bus interface circuit 32 can be closed and disconnected from the common bus 4 by itself. If the failure cannot be recognized by the failure on the side 4 or the like, the other processor card 2 cannot transmit data unless it is manually disconnected from the common bus 4.
[0006]
As described above, the prior art manually disconnects the processor card from the common bus. As such a failure detection method of the conventional multiprocessor configuration, a new failure monitoring circuit is provided so that the bus arbitration circuit deprives the failed processor of the bus right and does not newly grant the bus right. There is one configured (see Patent Document 1).
[0007]
[Patent Document 1]
JP-A-10-31656 [0008]
[Problems to be solved by the invention]
However, in the above-described conventional technology, if the processor in the processor card detects a fault by itself, the bus interface circuit can be closed and disconnected from the common bus. If it cannot be recognized by itself, there is a problem that other processor cards cannot transmit data unless they are manually disconnected from the common bus.
[0009]
Furthermore, since the restoration is not performed unless the separation is performed manually, it takes a long time to perform the restoration, the manual separation is inefficient, and the operation is complicated. For this reason, there is also a problem that the operation takes time and is uneconomical.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and the present invention has been made in consideration of the above-described circumstances. An object of the present invention is to provide a failure detection method for a processor configuration.
[0011]
It is another object of the present invention to provide a multi-processor fault detection method capable of automatically disconnecting a failed processor card from a common bus in a short time.
[0012]
[Means for Solving the Problems]
The present invention is directed to a multiprocessor configuration in which a bus card and a plurality of processor cards are connected via a common bus, wherein the bus card transmits a response to a request signal from the processor card, and after a predetermined time, the bus card transmits the response to the request signal. When the request signal from the processor card is continued, the bus card stops the power supply of the processor card and disconnects the processor card from the common bus.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment relating to a failure detection method having a multiprocessor configuration according to the present invention. A plurality of processor cards (in this embodiment, processor card 2 and processor card 3) are connected to the common bus 4. The processor cards 2 and 3 have bus interface circuits 22 and 32 and are connected to the common bus 4.
[0014]
The bus card 1 includes a bus arbitration circuit 11 that arbitrates the bus transmission right of the common bus 4 and is connected to the common bus 4. When the processors 23 and 33 in each of the processor cards 2 and 3 transmit data to the common bus 4, the bus interface circuits 22 and 32 transmit a request signal to the bus arbitration circuit 11 and a response signal from the bus arbitration circuit 11. And performs data transmission.
[0015]
Each of the processor cards 2 and 3 has a fault control circuit 21 or 31 that receives the power control signal 5 from the bus card 4 and controls power supply to the bus interface circuits 22 and 32.
[0016]
FIG. 2 is a block diagram showing details of the processor card 2 of the embodiment shown in FIG. In FIG. 2, the processor card 2 has a bus interface circuit 22 and is connected to the common bus 4. Further, the processor card 2 has a processor 23 for controlling the entire card and controlling data communication, and is connected to the bus interface circuit 22.
[0017]
Further, the processor card 2 has a fault control circuit 21 that receives the power control signal 5 and controls power supply to the bus interface circuit 22. The fault control circuit 21 receives the power control signal 5 and controls the relay circuit 212, and the relay circuit 212 controls ON / OFF of the +5 V power to the bus interface circuit 22 under the control of the power control circuit 211. It is composed of
[0018]
Next, the operation of the present embodiment will be described in detail with reference to the drawings. In FIG. 1, for example, it is assumed that a failure has occurred in the bus interface circuit 32 of the processor card 3 and that the state is maintained while a transmission request is issued to the common bus 4. At this time, even if another processor card 2 requests data transmission, the data transmission cannot be performed because the common bus 4 is occupied.
[0019]
The bus arbitration circuit 11 of the bus card 1 transmits the power control signal 5 when the data transmission is not performed and the transmission request is continued even after a certain period of time has passed after the transmission request and the response is returned, and the processor card 3 The power supply of the bus interface circuit 32 is stopped, and the bus interface circuit 32 is disconnected from the common bus 4.
[0020]
With this operation, the other processor card 2 can perform data transmission. Further, when it is not clear which part of the common bus 4 has a failure, the processor cards can be sequentially disconnected one by one to identify the failed part.
[0021]
Next, the power control operation will be described in detail with reference to FIG. In FIG. 2, when the power supply control circuit 211 of the fault control circuit 21 on the processor card 2 receives the power supply cutoff signal addressed to itself by the power supply control signal 5, it outputs a control signal to turn off the relay circuit 212.
[0022]
The relay circuit 212 operates to turn off the +5 V power supply in response to a control signal from the power supply control circuit 211, stop power supply to the bus interface circuit 22, and disconnect from the common bus 4.
[0023]
【The invention's effect】
As described above, according to the present invention, the power supply control signal is transmitted from the bus card, the power supply control circuit of each processor card controls the relay circuit, and the power supply of the bus interface circuit is stopped. Thus, the processor card can be separated and separated from the common bus.
[0024]
Further, since the faulty processor card is automatically separated from the common bus, it is possible to eliminate the need for manual work and to reduce the repair time.
[0025]
It should be noted that the present invention is not limited to the above embodiments, and it is obvious that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment relating to a failure detection system having a multiprocessor configuration according to the present invention.
FIG. 2 is a block diagram illustrating an internal configuration of a processor card according to the embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a conventional multiprocessor configuration fault detection system.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 bus card 2, 3 processor card 4 common bus 5 power control signal 11 bus arbitration circuit 21, 31 fault control circuit 22, 32 bus interface circuit 23, 33 processor 211 power control circuit 212 relay circuit

Claims (3)

In a multiprocessor configuration in which a bus card and a plurality of processor cards are connected via a common bus, after the bus card transmits a response to a request signal from the processor card, even if a certain period of time elapses, the bus card sends a response from the processor card. If the request signal continues, the bus card stops the power supply of the processor card, and disconnects the processor card from the common bus. In a multiprocessor configuration in which a bus card and a plurality of processor cards are connected via a common bus,
The plurality of multiprocessor cards have bus interface means connected to the common bus, and fault control means for stopping power supply to the bus interface means according to an instruction from the bus card,
When the bus card receives a request signal from the multiprocessor card, the bus card sends a response signal. After the response signal is sent, the power of the multiprocessor card is stopped when the request signal continues even after a certain period of time has passed. And a bus arbitration means for transmitting a power control signal to perform the fault detection. The fault control unit includes a power supply control circuit that receives a power supply control signal from the bus arbitration circuit, and a relay circuit that turns on and off power supply to the bus interface under the control of the power supply control circuit. 3. The fault detection method according to claim 2, wherein the fault detection method has a multiprocessor configuration.

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