JP2004165485A - Epitaxial wafer for field effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrain accumulation of carrier in an interface between an InAlAs buffer layer and an InP substrate in an epitaxial wafer of an n-type InAlAs/InGaAs system HEMT structure using InP in a substrate. <P>SOLUTION: After a first InAlAs buffer layer 2a whose film thickness is 50 nm or less is formed on a semiinsulating InP substrate 1 at a low temperature of 600°C or lower, the formation temperature is made higher, and a second InAlAs buffer layer 2b is formed changing or without changing the V/III ratio which is the supply ratio between a group V raw material and a group III raw material required for the formation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an epitaxial wafer for a field effect transistor, and more particularly to an epitaxial wafer for a field effect transistor having an n-type InAlAs / InGaAs HEMT structure using InP as a substrate and a method of manufacturing the same.
[0002]
[Prior art]
The structure in which a carrier transit layer (channel layer) containing no impurities, a carrier supply layer containing an n-type impurity (interfering with carrier transit), and a Schottky gate are stacked on a buffer layer provided on a substrate is a HEMT. (High electron mobility transistor). This has succeeded in improving noise characteristics and high-frequency characteristics by spatially separating the carrier transit layer and the carrier supply layer by a heterojunction.
[0003]
HEMTs have high performance in terms of higher electron mobility than GaAs FETs, higher sheet electron concentration in the channel, and confinement of channel electrons in a narrow region near the heterojunction interface. In particular, a strain-lattice type HEMT (Pseudo-morphic HEMT) in which the channel is an InGaAs layer and the electron supply layer is an AlGaAs layer has a higher electron mobility and a higher electron saturation speed in the InGaAs layer than GaAs. Attention should be paid to the fact that if the Al composition is set to about 0.2, the DX center is not much affected, and the band discontinuity at the AlGaAs / InGaAs heterojunction interface is large, the sheet electron concentration is high, and a high electron confinement effect can be obtained. Have been.
[0004]
Attention has been paid to the fact that a higher sheet electron concentration and room temperature mobility can be obtained than this strain lattice type HEMT, and that a high frequency of 20 GHz or more can be amplified with extremely low noise. An InGaAs layer lattice-matched to an InP substrate is used as a channel layer. And a lattice-matched HEMT using an InAlAs layer as a carrier supply layer.
[0005]
As an example of an epitaxial wafer for an InP lattice-matched high electron mobility transistor (HEMT) comprising an InGaAs channel layer and an InAlAs carrier supply layer, a document by Katsuhiko Higuchi et al. [Applied Physics 67, 139 (1998)] (Non-patent Document 1) FIG. 6) introduces a structure as shown in FIG. In FIG. 6, 21 is a semi-insulating InP substrate, 22 is an undoped InAlAs buffer layer, 23 is an undoped InGaAs channel layer, 24 is an undoped InAlAs spacer layer, 25 is n-type doping of Si, Se, Te or the like in whole or in part. Reference numeral 26 denotes an undoped InAlAs Schottky contact layer, and reference numeral 27 denotes an InGaAs ohmic contact layer in which Si, Se, Te, or the like is entirely or partially n-type doped.
[0006]
In this InP-based HEMT, a buffer layer made of InAlAs and a channel layer 3 made of InGaAs are provided on a semi-insulating InP substrate by metal organic vapor phase epitaxy (MOVPE). On this, a spacer layer made of InAlAs and a carrier supply layer made of Si-doped or Se-doped InAlAs are sequentially formed.
[0007]
Conventionally, when the above-mentioned undoped InAlAs buffer layer 22 is formed by the MOVPE method, M.P. Kamada [Current Topics in Crystal Growth Res. , 1 (1994)] (see Non-Patent Document 2), an undoped InAlAs buffer layer is grown at a substrate temperature of 670 ° C. or more and a V / III ratio of 100 or more.
[0008]
Also, N.I. Pan et al. [Appl. Phys. Lett. 63, 3029 (1993)] (see Non-Patent Document 3) discloses a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an InAlAs carrier at least partially n-type doped by MOVPE. The problem of an epitaxial wafer for a field effect transistor including a supply layer is described, and a configuration in which a buffer layer is a low-temperature buffer layer portion and a buffer layer portion thereon is shown.
[0009]
[Non-patent document 1]
Katsuhiko Higuchi, Applied Physics 67, 139 (1998)
[Non-patent document 2]
M. Kamada, Current Topics in Crystal Growth Res. , 1 (1994)
[Non-Patent Document 3]
N. Pan, Appl. Phys. Lett. 63, 3029 (1993)
[0010]
[Problems to be solved by the invention]
N. As described in Pan et al. (Non-Patent Document 3), a semi-insulating InP substrate, an undoped InAlAs buffer layer, and an undoped InGaAs channel layer were at least partially n-doped by MOVPE. When an epitaxial wafer for a field effect transistor including an InAlAs carrier supply layer is grown, carriers accumulate at the interface between the semi-insulating InP substrate and the undoped InAlAs buffer layer.
[0011]
This accumulation of carriers at the interface causes an increase in drain conductance, which degrades the pinch-off characteristics of the HEMT.
[0012]
However, the improvement of the pinch-off characteristics of the HEMT is not sufficient simply by using the above-mentioned buffer layer as a low-temperature buffer layer portion and a buffer layer portion thereon, and it is desired to further improve the pinch-off characteristics of the HEMT. .
[0013]
Accordingly, an object of the present invention is to solve the above-described problems, and to provide an electric field including a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an InAlAs carrier supply layer at least partially n-type doped. It is an object of the present invention to provide a manufacturing method and a structure for suppressing accumulation of carriers at an interface between an InAlAs buffer layer and an InP substrate in an epitaxial wafer for an effect transistor.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
[0015]
A method of manufacturing an epitaxial wafer for a field effect transistor according to the invention of claim 1, wherein the semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an InAlAs carrier supply layer at least partially n-doped. Forming a first InAlAs buffer layer having a thickness of 50 nm or less on a semi-insulating InP substrate at a low temperature of 600 ° C. or less by a MOVPE method. And the second InAlAs buffer layer is formed with or without a change in the V / III ratio, which is a supply ratio of the group V source and the group III source required for its formation.
[0016]
In the present invention, an InAlAs buffer layer includes a first InAlAs buffer layer and a second InAlAs buffer layer, and also includes a third or fourth InAlAs buffer layer. For example, an epitaxial wafer for a field-effect transistor including a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an InAlAs carrier supply layer at least partially doped with n-type is manufactured by MOVPE. A method of changing the formation temperature during formation of the InAlAs buffer layer, and / or the supply ratio (V / III ratio) of the group V material to the group III material required for the formation at least once or more, and the method of forming the InAlAs buffer layer. During the formation, there is included a production method in which the formation temperature is changed at least one or more times with or without changing the supply ratio (V / III ratio) of the group V raw material and the group III raw material required for the formation.
[0017]
A method for manufacturing an epitaxial wafer for a field effect transistor according to the invention of claim 2 includes a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an InAlAs carrier supply layer at least partially n-doped. In the method of manufacturing an epitaxial wafer for a field effect transistor by MOVPE, the first InAlAs buffer layer in the vicinity of the interface with the InP substrate is formed at a temperature of 480 ° C. or more and 600 ° C. or less in the InAlAs buffer layer. Crystal growth process formed in an atmosphere having a V / III ratio of 1 to 30 which is a supply ratio of a group V raw material and a group III raw material required for the above, and a second InAlAs buffer layer which is another InAlAs buffer layer portion At a temperature higher than 600 ° C and 700 ° C It is lower, and the V / III ratio is characterized in that it comprises a second crystal growth process for forming in an atmosphere is greater than 30 200 or less, a.
[0018]
In the method of manufacturing an epitaxial wafer for a field-effect transistor, a portion of an InAlAs buffer layer near an interface with an InP substrate is formed in an atmosphere having a temperature of 480 to 600 ° C. and a V / III ratio of 1 to 30. One crystal growth process and the other InAlAs buffer layer portion were heated to a temperature of 600 to 700 ° C. (but not 600 ° C.) and a V / III ratio of 30 to 200 (but not 30). A second crystal growth process formed in an atmosphere.
[0019]
According to a third aspect of the present invention, in the method for manufacturing an epitaxial wafer for a field effect transistor according to the second aspect, in the InAlAs buffer layer, a thickness of a first InAlAs buffer layer near an interface with an InP substrate is 50 nm or less. It is characterized by being.
[0020]
According to a fourth aspect of the present invention, in the method for manufacturing an epitaxial wafer for a field-effect transistor according to the second or third aspect, a first crystal growth process for forming a first InAlAs buffer layer near an interface with the InP substrate includes: The InP substrate is formed in an atmosphere at a temperature of 480 to 600 ° C. and a V / III ratio of 3 to 10, more preferably in an atmosphere at a temperature of 520 to 560 ° C. and a V / III ratio of 3 to 10, The first InAlAs buffer layer is formed in a portion near the interface with the first InAlAs buffer layer.
[0021]
The present invention provides an atmosphere for a first crystal growth process for forming a first InAlAs buffer layer near an interface with an InP substrate in an InAlAs buffer layer at a temperature of 480 to 600 ° C. and a V / III ratio of 3 -10 to 10 atmospheres, more preferably an atmosphere having a temperature of 520 to 560 ° C and a V / III ratio of 3 to 10.
[0022]
According to a fifth aspect of the present invention, in the method for manufacturing an epitaxial wafer for a field effect transistor according to the second or third aspect, a second crystal growth process for forming a second InAlAs buffer layer other than a portion near an interface with the InP substrate. In an atmosphere having a temperature higher than 600 ° C. and 700 ° C. or lower and a V / III ratio of 30 to 200, more preferably an atmosphere having a temperature of 640 to 660 ° C. and a V / III ratio of 100 to 200. And forming a second InAlAs buffer layer.
[0023]
According to a sixth aspect of the invention, an epitaxial wafer for a field effect transistor is formed by the method for manufacturing an epitaxial wafer for a field effect transistor according to any one of the first to fifth aspects.
[0024]
<Action>
The present invention relates to an epitaxial wafer for a field effect transistor including a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an InAlAs carrier supply layer at least partially n-doped by MOVPE. In the manufacturing process, during formation of the InAlAs buffer layer, the formation temperature and / or the supply ratio (V / III ratio) of the group V source to the group III source required for the formation (V / III ratio) is changed at least once or more. A method for manufacturing a wafer is provided.
[0025]
N. As described in Pan et al. (Non-Patent Document 3), a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and at least a part thereof are n-type doped by MOVPE. It is known that when an epitaxial wafer for a field effect transistor including an InAlAs carrier supply layer is grown, carrier accumulation occurs at the interface between the semi-insulating InP substrate and the undoped InAlAs buffer layer. The accumulation of carriers at the interface causes an increase in drain conductance, which degrades the pinch-off characteristics of the HEMT.
[0026]
As a result of intensive research efforts by the present inventors regarding the above problems, the following findings were obtained. That is, N.I. Pan et al. Formed a 75 nm low-temperature InAlAs buffer layer at a substrate temperature of 475 ° C. on a semi-insulating InP substrate and increased an InAlAs buffer layer at a substrate temperature of 650 ° C. to increase the resistance of the interface buffer layer. The thickness is 30 nm. However, the present inventors have found that high-concentration impurities exist in the low-temperature InAlAs buffer layer. For this reason, it is not desirable to include the low-temperature InAlAs buffer layer as much as 75 nm.
[0027]
Therefore, in the present invention, by setting the thickness of the low-temperature InAlAs buffer layer to 50 nm or less, accumulation of carriers at the interface between the InAlAs buffer layer and the InP substrate is suppressed, and the pinch-off characteristics of the HEMT are further improved. .
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described based on the illustrated embodiments.
[0029]
FIG. 1 shows the structure of an InAlAs / InGaAs HEMT epitaxial wafer according to an embodiment of the present invention. An InAlAs buffer layer 2 having a thickness of 200 nm is provided on an InP substrate 1, an undoped InGaAs channel layer (operating layer) 3 having a thickness of 25 nm is provided thereon, and an undoped InAlAs spacer layer 4 having a thickness of 3 nm is further provided thereon. An Si-doped n-type InAlAs carrier supply layer (doped layer) 5 having a thickness of 7 nm is provided therebetween. Reference numeral 6 denotes an undoped InAlAs Schottky contact layer having a thickness of 10 nm for forming a Schottky junction, and reference numeral 7 denotes a 50 nm-thick Si-doped n-type InGaAs ohmic contact layer for preventing oxidation and forming an ohmic junction.
[0030]
According to the present invention, the above-mentioned 200 nm-thick InAlAs buffer layer 2 is composed of the first InAlAs buffer layer 2a near the interface with the InP substrate and the second InAlAs buffer layer 2b as the other InAlAs buffer layer. ing.
[0031]
The first InAlAs buffer layer 2a near the interface with the InP substrate has a temperature of 480 ° C. or more and 600 ° C. or less and a V / III ratio of 1 to 30 which is a supply ratio of a group V material and a group III material required for formation. Is formed in the first crystal growth process in the atmosphere. The temperature of the second InAlAs buffer layer 2b, which is the portion of the InAlAs buffer layer other than the portion near the interface with the InP substrate, is higher than 600 ° C. and 700 ° C. or lower, and the V / III ratio is higher than 30 and 200 or lower. The atmosphere is formed in a second crystal growth process. The first InAlAs buffer layer 2a is formed to a thickness of 50 nm or less (here, a thickness of 5 nm). The thickness of the second InAlAs buffer layer 2b is set to the remaining thickness of the entire buffer layer 2, that is, 195 nm in this case.
[0032]
The reason for setting the formation temperature of the first InAlAs buffer layer 2a to 480 ° C. to 600 ° C. is to obtain high-quality crystals in this range, and preferably to 520 to 560 ° C. The temperature at which the second InAlAs buffer layer 2b is formed is set to be higher than 600 ° C., but it is preferable that the temperature is not too high and is set to 700 ° C. or lower.
[0033]
【Example】
[Example 1]
A method for manufacturing an epitaxial wafer, which is a first embodiment of the present invention, will be described below.
[0034]
Phosphine (PH) is placed in the reaction vessel of the MOVPE apparatus on which the InP substrate 1 is installed. ₃ ), The temperature of the substrate portion in the reaction vessel is raised from room temperature to 560 ° C. When the temperature of the substrate portion was stabilized at 560 ° C., the supply of phosphine was stopped, and trimethyl indium (TMI), trimethyl aluminum (TMA) and arsine (AsH) were added to the reaction vessel. ₃ ) Is supplied at a flow rate such that the molar ratio (V / III ratio) of the sum of arsine, which is a Group V material, and trimethylindium, and trimethylaluminum, which are Group III materials, is approximately 3. With such an atmosphere in the container maintained, an InAlAs layer (first InAlAs buffer layer 2a) equivalent to 5 nm is formed.
[0035]
Next, the supply of trimethylindium and trimethylaluminum is temporarily stopped, and the temperature of the substrate portion in the container is increased from 560 ° C. to 640 ° C. while arsine is supplied at an arbitrary flow rate into the reaction container. Observing that the temperature of the substrate portion was stabilized at 640 ° C., the reaction vessel was charged with trimethylindium, trimethylaluminum and arsine, and the molar ratio of the sum of the group V raw material arsine and the group III raw material trimethylindium and trimethylaluminum was changed. It is supplied at a flow rate of approximately 100. An InAlAs layer (second InAlAs buffer layer 2b) corresponding to 195 nm is formed while maintaining such an atmosphere in the container. FIG. 2 shows a sequence of forming the undoped InAlAs buffer layer 2 which is a feature of the present invention.
[0036]
Next, at the same time as the supply of trimethylaluminum into the reactor was stopped, trimethylgallium was supplied, and trimethylindium, trimethylgallium, and arsine were converted to the sum of arsine as a group V material and trimethylindium and trimethylaluminum as group III materials. Is supplied at such a flow rate that the molar ratio becomes approximately 100. While maintaining such a container atmosphere, an InGaAs layer (undoped InGaAs channel layer 3) equivalent to 25 nm is formed.
[0037]
Next, the supply of trimethylgallium into the reactor is stopped, and at the same time, trimethylaluminum is supplied, and trimethylindium, trimethylaluminum and arsine are converted into a group V material, arsine, and a group III material, trimethylindium and trimethylaluminum. Are supplied at such a flow rate that the molar ratio of the sum of While maintaining such a container atmosphere, an InAlAs layer (undoped InAlAs spacer layer 4) equivalent to 3 nm is formed.
[0038]
Then, disilane (Si ₂ H ₆ ), And trimethylindium, trimethylaluminum, arsine and disilane are supplied at a flow rate such that the molar ratio of the sum of arsine, which is a group V raw material, trimethylindium, which is a group III raw material, and trimethylaluminum, is approximately 250. While maintaining such a container atmosphere, an n-type doped InAlAs layer equivalent to 7 nm (n-type InAlAs carrier supply layer 5) is formed.
[0039]
Then, the supply of disilane into the reaction furnace was stopped, and trimethylindium, trimethylaluminum and arsine were changed to have a molar ratio of the total of the group V raw material arsine and the group III raw material trimethylindium and trimethylaluminum of about 100. Supply at a flow rate such that While maintaining such a container atmosphere, an InAlAs layer equivalent to 10 nm (undoped InAlAs Schottky contact layer 6) is formed.
[0040]
Finally, the supply of trimethylaluminum into the reactor is stopped, and at the same time, trimethylgallium and disilane are supplied, and trimethylindium, trimethylgallium, arsine, and disilane are converted into a group V material, arsine, and a group III material, trimethyl gallium. It is supplied at such a flow rate that the molar ratio of the sum of indium and trimethylaluminum becomes almost 100. While maintaining such a container atmosphere, an n-type doped InGaAs layer (n-type InGaAs ohmic contact layer 7) equivalent to 50 nm is formed, and after formation, the temperature of the substrate portion in the reaction furnace is changed from 640 ° C. to room temperature. Cool down to
[0041]
According to the method of manufacturing an epitaxial wafer as described above according to this embodiment, accumulation of carriers at the interface between the undoped InAlAs buffer layer and the semi-insulating InP substrate was suppressed, and a field effect transistor having good pinch-off characteristics was obtained.
[0042]
[Example 2]
The features of the present invention will be described below with reference to a growth example in which two samples having different growth sequences are compared.
[0043]
FIG. 3 is a diagram showing an InAlAs buffer layer grown on an InP substrate, which is a part of the following prototypes (Example 2 and Conventional Example), where 31 is a semi-insulating InP substrate, and 32 is an undoped InAlAs buffer layer. Is shown. An experiment was conducted to form this structure with two different growth sequences, and the results are described.
[0044]
(Conventional example)
First, the growth sequence of the first prototype (conventional example) is shown below, which is based on the conventional method. While supplying phosphine into the reaction vessel in which the InP substrate 31 is installed, the temperature of the substrate portion in the reaction vessel is raised from room temperature to 640 ° C. When the temperature of the substrate portion was stabilized at 640 ° C., the supply of phosphine was stopped, and trimethylindium, trimethylaluminum and arsine were added to the reaction vessel, and a group V material, arsine, and a group III material, trimethylindium and trimethyl. The aluminum is supplied at a flow rate such that the molar ratio of the sum of the aluminum is approximately 100. While maintaining the atmosphere in the container, an InAlAs layer (undoped InAlAs buffer layer 32) equivalent to 3 μm is formed.
[0045]
(Example 2)
Next, the growth sequence of the second prototype (Example 2) is shown below, which is according to the present invention. While supplying phosphine into the reaction vessel in which the InP substrate 31 is installed, the temperature of the substrate in the reaction vessel is raised from room temperature to 560 ° C. When the temperature of the substrate portion was stabilized at 560 ° C., the supply of phosphine was stopped, and trimethylindium, trimethylaluminum and arsine were added to the reaction vessel, and a group V source material, arsine, and a group III source material, trimethylindium and trimethylaluminum. Are supplied at a flow rate such that the molar ratio of the sum of With such an atmosphere in the container maintained, an InAlAs layer corresponding to 5 nm (a first InAlAs buffer layer in a portion near the interface with the InP substrate among the InAlAs buffer layers) is formed.
[0046]
Next, the supply of trimethylindium and trimethylaluminum is temporarily stopped, and the temperature of the substrate portion in the container is increased from 560 ° C. to 640 ° C. while arsine is supplied at an arbitrary flow rate into the reaction container. Observing that the temperature of the substrate portion was stabilized at 640 ° C., the reaction vessel was charged with trimethylindium, trimethylaluminum and arsine, and the molar ratio of the sum of the group V raw material arsine and the group III raw material trimethylindium and trimethylaluminum was changed. It is supplied at a flow rate of approximately 100. While keeping the atmosphere in the container, an InAlAs layer equivalent to 3 μm (a second InAlAs buffer layer which is an InAlAs buffer layer other than the first InAlAs buffer layer) is formed.
[0047]
The carrier concentration distribution in the vertical direction in the epitaxial wafer formed by these two types of growth sequences was measured by the CV method.
[0048]
FIG. 5 is based on the first growth sequence of the conventional example, and FIG. 4 is based on the second growth sequence of the second embodiment. The horizontal axis represents the depth (μm), and the vertical axis represents the carrier concentration, for example, 1. 1 × 10 at E + 14 ¹⁴ cm ^-3 Represents
[0049]
As shown in FIG. 5, a peak due to carrier accumulation exists at the interface between the InAlAs buffer layer and the InP substrate formed in the first growth sequence based on the conventional method. On the other hand, there was no peak due to carrier accumulation at the interface between the InAlAs buffer layer according to the present invention and the InP substrate in FIG.
[0050]
That is, an interface is produced by a method for manufacturing an epitaxial wafer for a field effect transistor including a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an InAlAs carrier supply layer at least partially n-doped according to the present invention. Carrier accumulation is suppressed, and a field-effect transistor having good pinch-off characteristics can be obtained.
[0051]
【The invention's effect】
As described above, according to the present invention, after a first InAlAs buffer layer having a thickness of 50 nm or less is formed on a semi-insulating InP substrate at a low temperature of 600 ° C. or less, the formation temperature is increased, Since the InAlAs buffer layer is formed with or without a change in the V / III ratio, which is the supply ratio of the group V source and the group III source required for its formation, the interface between the semi-insulating InP substrate and the InAlAs buffer layer is formed. And the carrier accumulation at the interface is suppressed, and an epitaxial wafer for a field effect transistor having good pinch-off characteristics can be obtained. Further, according to the lattice-matched HEMT epitaxial wafer of the present invention, good pinch-off characteristics can be obtained, and the withstand voltage of the buffer layer can be improved.
[Brief description of the drawings]
FIG. 1 is a view showing a configuration of an epitaxial wafer for a field effect transistor according to the present invention.
FIG. 2 is a diagram showing a formation temperature and a V / III ratio growth sequence of an undoped InAlAs buffer layer in the present invention.
FIG. 3 is a diagram showing a structure of an undoped InAlAs buffer layer formed on a semi-insulating InP substrate, for the purpose of explaining an example of the present invention and a conventional example.
FIG. 4 is a diagram showing a result of CV measurement of an undoped InAlAs buffer layer formed by a growth sequence in an example of the present invention.
FIG. 5 is a diagram showing a result of CV measurement of an undoped InAlAs buffer layer formed by a growth sequence in a conventional example.
FIG. 6 is a view showing a structure of a conventional epitaxial wafer for a field effect transistor.
[Explanation of symbols]
1 Semi-insulating InP substrate
2 Undoped InAlAs buffer layer
2a First InAlAs buffer layer
2b Second InAlAs buffer layer
3 Undoped InGaAs channel layer
4 Undoped InAlAs spacer layer
5 n-type InAlAs carrier supply layer (doped layer)
6 Undoped InAlAs Schottky contact layer
7 n-type InGaAs ohmic contact layer

Claims (6)

In a method for manufacturing an epitaxial wafer for a field effect transistor including a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an InAlAs carrier supply layer at least partially doped with n-type by MOVPE. ,
After forming a first InAlAs buffer layer having a thickness of 50 nm or less on a semi-insulating InP substrate at a low temperature of 600 ° C. or less,
Forming a second InAlAs buffer layer with or without a change in the V / III ratio, which is a supply ratio of the group V source and the group III source required for the formation, by increasing the formation temperature. Of manufacturing an epitaxial wafer for a field effect transistor. A method for manufacturing an epitaxial wafer for a field effect transistor by MOVPE including a semi-insulating InP substrate, an undoped InAlAs buffer layer, an undoped InGaAs channel layer, and an at least partially n-type doped InAlAs carrier supply layer, comprising:
Of the InAlAs buffer layer, the first InAlAs buffer layer in the vicinity of the interface with the InP substrate was formed at a temperature of 480 ° C. or more and 600 ° C. or less and V / III, which is a supply ratio of a group V material and a group III material required for formation. A first crystal growth process formed in an atmosphere having a ratio of 1 to 30;
Second crystal growth in which the second InAlAs buffer layer, which is the other InAlAs buffer layer portion, is formed in an atmosphere in which the temperature is higher than 600 ° C. and 700 ° C. or lower and the V / III ratio is higher than 30 and lower than 200. And a process for producing an epitaxial wafer for a field effect transistor. The method for producing an epitaxial wafer for a field effect transistor according to claim 2,
A method of manufacturing an epitaxial wafer for a field effect transistor, wherein a thickness of a first InAlAs buffer layer in a portion near an interface with an InP substrate in the InAlAs buffer layer is 50 nm or less. The method for manufacturing an epitaxial wafer for a field effect transistor according to claim 2 or 3,
The first crystal growth process for forming the first InAlAs buffer layer in the vicinity of the interface with the InP substrate is performed in an atmosphere at a temperature of 480 to 600 ° C. and a V / III ratio of 3 to 10, more preferably at a temperature of 3 to 10. Forming a first InAlAs buffer layer near the interface with the InP substrate, in an atmosphere having a temperature of 520 to 560 ° C. and a V / III ratio of 3 to 10. Manufacturing method. The method for producing an epitaxial wafer for a field effect transistor according to claim 2 or 3,
A second crystal growth process for forming a second InAlAs buffer layer other than a portion near the interface with the InP substrate is performed in an atmosphere in which the temperature is higher than 600 ° C. and 700 ° C. or lower and the V / III ratio is 30 to 200. More preferably, the method is carried out in an atmosphere at a temperature of 640 to 660 ° C. and a V / III ratio of 100 to 200 to form a second InAlAs buffer layer, the method for manufacturing an epitaxial wafer for a field effect transistor. An epitaxial wafer for a field-effect transistor formed by the method for manufacturing an epitaxial wafer for a field-effect transistor according to claim 1.

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