JP2004165469A - Semiconductor devices, wafer therefor and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower a resistance of a p-type semiconductor layer group in a semiconductor device with a p-type semiconductor layer group and an n-type semiconductor layer group laminated on a predetermined wafer so that the p-type semiconductor layer group is satisfactorily activated for a practical use. <P>SOLUTION: A group III nitride base layer including at least alminum and having a dislocation density of 1 X 10<SP>11</SP>/cm<SP>2</SP>or less with 200 seconds or less of a X-ray rocking curve half-value-width on a (002) surface is formed on a predetermined wafer material. The p-type semiconductor layer group comprising a first group III nitride including at least Ga is formed over the group III nitride base layer. The n-type semiconductor layer group comprising a second group III nitride including at least Ga is formed on the p-type semiconductor layer group after the activated processing of the p-type semiconductor layer group. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be preferably used as a semiconductor light emitting device, a method for manufacturing the same, and a substrate for the semiconductor device.
[0002]
2. Description of the Related Art A group III nitride film has been used as a semiconductor film constituting a semiconductor light emitting device. In recent years, a high-intensity light source particularly for green light to blue light, and further, ultraviolet light and white light have been used. Is also expected as a semiconductor film in a semiconductor light emitting device as a light source for use.
FIG. 1 is a configuration diagram showing an example of a conventional so-called PIN type semiconductor light emitting device.
In a semiconductor light emitting device 10 shown in FIG. 1, a buffer layer 2 made of GaN, a base layer 3 made of Si-doped n-GaN, a Si-doped n-AlGaN N-type conductive layer 4 made of InGaN, light emitting layer 5 having a multiple quantum well (MQW) structure made of InGaN, p-type clad layer 6 made of Mg-doped p-AlGaN, p-type conductive layer 7 made of Mg-doped p-GaN Are formed in this order. In the semiconductor light emitting device 10 shown in FIG.
The underlayer 3 and the n-type conductive layer 4 form an n-type semiconductor layer group, and the p-type cladding layer 6 and the p-type conductive layer 7 form a p-type semiconductor layer group.
[0005] A part of the n-type conductive layer 4 is exposed. An n-type electrode 8 such as Al / Ti is formed on the exposed part, and an Au / Ni or the like is formed on the p-type conductive layer 7. A p-type electrode 9 is formed.
[0006] Then, by applying a predetermined voltage between the n-type electrode 8 and the p-type electrode 9, recombination of carriers occurs in the light emitting layer 5, and light of a predetermined wavelength is emitted. The wavelength is determined by the structure and composition of the light emitting layer.
In order to put the semiconductor light emitting device 10 shown in FIG. 1 to practical use, the semiconductor light emitting device 10 is placed in an atmosphere containing no hydrogen, and then heated at a temperature of 400 ° C. or more to form a p-type cladding layer. The p-type semiconductor layer group consisting of the p-type semiconductor layer 6 and the p-type conductive layer 7 is subjected to an activation process, for example, by removing and removing a hydrogen element bonded to Mg added as a dopant, and setting the resistance value of the p-type semiconductor layer group to a predetermined value. (Japanese Patent No. 25407991).
[0008]
However, if the above-described relatively high-temperature activation treatment is performed after the semiconductor light emitting device 10 is integrally formed, the mass transfer of the p-type impurities in the semiconductor light emitting device 10 in particular is caused. Therefore, there is a problem that the conductivity cannot be controlled as designed. For example, Mg, which is a p-type impurity, may diffuse to the n-type semiconductor layer to cause a compensation effect, or the luminous efficiency may decrease due to impurity diffusion into the light emitting layer. Therefore, in the activation treatment, the activation treatment temperature has to be lowered at the expense of the activation efficiency to some extent. As a result, the hydrogen element cannot be sufficiently removed from the p-type semiconductor layer group, and in some cases, the resistance cannot be reduced to a value sufficient for practical use.
According to the present invention, in a semiconductor device in which a p-type semiconductor layer group and an n-type semiconductor layer group are stacked on a predetermined substrate, the p-type semiconductor layer group is sufficiently activated and is practically used. It is an object of the present invention to provide a semiconductor element having as low a resistance as possible and a semiconductor element substrate having the p-type semiconductor layer group sufficiently activated. Still another object is to provide a method for manufacturing the semiconductor device.
[0010]
In order to achieve the above object, the present invention provides a method for producing a semiconductor device, comprising the steps of: providing at least Al on a predetermined base material, having a dislocation density of 1 × 10 ¹¹ / cm ² or less; A group III nitride underlayer having an X-ray rocking curve half-width of 200 seconds or less, and a first group III nitride containing at least Ga formed on the group III nitride underlayer. A p-type semiconductor layer group processed and an n-type semiconductor layer group formed on the p-type semiconductor layer group and made of a second group III nitride containing at least Ga. The present invention relates to a semiconductor device.
[0011] Further, the present invention provides a method for manufacturing a semiconductor device according to the present invention, wherein at least Al is contained on a predetermined base material, the dislocation density is 1 × 10 ¹¹ / cm ² or less, and the half-width of the (002) plane X-ray rocking curve is 200 seconds or less. A group III nitride underlayer and a group of activated p-type semiconductor layers formed of a group III nitride containing at least Ga and formed above the group III nitride underlayer are essentially formed of the group III nitride underlayer. The present invention relates to a substrate for a semiconductor element, characterized by comprising
In the present invention, “essentially” includes an n-type semiconductor layer group such as a single layer or a multi-layer structure which contributes to conductivity between the underlayer and the p-type semiconductor layer group. No means. Therefore, a multi-layer structure such as a buffer layer or a strained superlattice for the purpose of improving crystallinity can be included between the layers.
[0013] Further, the present invention provides a method for manufacturing a semiconductor device, comprising: at least Al, a dislocation density of not more than 1 × 10 ¹¹ / cm ² , and a half-width of a (002) plane X-ray rocking curve of not more than 200 seconds. Forming a group III nitride underlayer;
Forming a p-type semiconductor layer group made of a first group III nitride containing at least Ga above the group III nitride underlayer;
Activating the p-type semiconductor layer group;
Forming an n-type semiconductor layer group made of a second group III nitride containing at least Ga on the p-type semiconductor layer group;
And a method for manufacturing a semiconductor device.
The present inventors have conducted intensive studies to achieve the above object. As a result, the Al-containing III-nitride underlayer of high crystal quality as described above is provided on a predetermined substrate, and the p-type semiconductor layer group and the n-type semiconductor layer group are Consist of things. Further, according to the manufacturing method of the present invention, in the conventional semiconductor device configuration as shown in FIG. 1, the stacking order of the p-type semiconductor layer group and the n-type semiconductor layer group is reversed, and before the n-type semiconductor layer group is stacked. It has been found that by activating only the p-type semiconductor layer group, the resistance of the p-type semiconductor layer group can be sufficiently reduced. Therefore, according to the present invention, it is possible to obtain a semiconductor device having a pn junction that can be put to practical use with an extremely simple process.
According to the present invention, not only the heat treatment at a high temperature as described above, but also the heat treatment at a sufficiently low temperature, the p-type semiconductor layer group is sufficiently activated to reduce the resistance, A semiconductor element having a pn junction that can be put to practical use can be obtained.
In the present invention, the semiconductor element substrate and the semiconductor element can have the same layer structure. Therefore, the same layer configuration can be conceptualized as a substrate for a semiconductor element, or can be conceptualized as a semiconductor element. However, even in the case of having the same layer configuration, the semiconductor element substrate and the semiconductor element can be differentiated by a difference in dimension. Specifically, a substrate for a semiconductor element is produced by forming various films on a wafer-shaped substrate, and a semiconductor element is usually produced by cutting the substrate for a semiconductor element into a predetermined size. I do. Therefore, when viewed in the vertical direction, even when the layer configuration is the same, the size when viewed in the horizontal direction differs.
[0017]
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments of the present invention.
FIG. 2 is a configuration diagram showing an example of the semiconductor device of the present invention. The semiconductor element 20 shown in FIG. 2 includes a base layer 13, a p-type conductive layer 14, a light-emitting layer 15, an n-type cladding layer 16, and an n-type conductive layer 17 on a substrate 11 in that order. A part of the p-type conductive layer 14 is exposed, and a p-type electrode 18 made of, for example, Au / Ni is formed on the exposed p-type conductive layer 14, and on the n-type conductive layer 17. An n-type electrode 19 made of, for example, Al / Ti is formed to constitute a so-called PIN type semiconductor light emitting device.
As described above, the semiconductor element shown in FIG. 2 can be regarded as a semiconductor element substrate by considering the difference in dimension and the like.
In FIG. 2, the p-type conductive layer 14 forms a p-type semiconductor layer group, and the n-type cladding layer 16 and the n-type conductive layer 17 form an n-type semiconductor layer group. Note that the n-type cladding layer 16 can be omitted as necessary.
According to the present invention, the underlayer 13 contains Al, has a dislocation density of 1 × 10 ¹¹ / cm ² or less, and has a half-width of 200 seconds or less in the X-ray rocking curve on the (002) plane. It must be made of group III nitride. Thus, by performing a heat treatment on the p-type conductive layer 14 in an atmosphere containing no hydrogen, for example, and performing an activation process, the hydrogen element bonded to the dopant in the p-type semiconductor layer 14 can be sufficiently reduced. It can be separated and removed, and the resistance can be reduced. As a result, the semiconductor element 20 that can be put to practical use can be easily provided.
The dislocation density is preferably 5 × 10 ¹⁰ / cm ² or less, more preferably 1 × 10 ¹⁰ / cm ² or less. The half width is preferably 100 seconds or less, and more preferably 60 seconds or less.
The surface roughness Ra is preferably 2 ° or less. This measurement is performed using an AFM in a range of 5 μm square.
As the Al content in the group III nitride constituting the underlayer 13 increases, the rate at which dislocations caused by the substrate 11 become entangled at the interface between the substrate 11 and the underlayer 13 and propagate into the underlayer 13 increases. Decrease. As a result, the dislocation density in the underlayer 13 is reduced, and the crystal quality of the underlayer 13 is further improved. For this reason, it is preferable that the group III nitride constituting the underlayer 13 contains as much Al as possible, specifically, it is preferable that the group III nitride contains Al in a proportion of 50 atomic% or more with respect to all group III elements. Further, it is preferable that all the group III elements are made of Al, and the underlying layer 13 is made of AlN.
The thickness of the underlayer 13 is preferably large, and more specifically, it is preferably formed to a thickness of 0.1 μm or more, more preferably 0.5 μm or more. The upper limit value of the thickness of the underlayer 13 is not particularly limited, and is appropriately selected and set in consideration of the occurrence of cracks and the use.
The underlayer 13 may contain, in addition to Al, a group III element such as Ga and In, and additional elements such as B, Si, Ge, Zn, Be and Mg. Further, not only elements intentionally added, but also trace elements inevitably taken in depending on film formation conditions and the like, and trace impurities contained in raw materials and reaction tube materials can be included.
The underlayer 13 can be formed using a known film forming means as long as the above requirements are satisfied. However, it can be easily obtained by using the MOCVD method and setting the film forming temperature to 1100 ° C. or higher. In addition, the film forming temperature of the present invention means a set temperature of the substrate 11. Note that the film forming temperature is preferably 1250 ° C. or less from the viewpoint of suppressing the surface roughness of the underlayer 13 and the like.
The p-type conductive layer 14 needs to be made of a first group III nitride containing at least Ga. Thus, the p-type conductive layer 14 can be sufficiently activated in the activation process described later, and the resistance can be reduced. In the present invention, the Ga content in the group III nitride constituting the p-type conductive layer 14 is preferably as large as possible, specifically, 50 atomic% or more, more preferably 70 atomic% or more, and particularly all of Preferably, the group III element is composed of Ga and composed of GaN.
The activation process is performed after forming the p-type conductive layer 14 and before forming the light emitting layer 15. Specifically, after the p-type conductive layer 14 is formed, a multilayer film structure in which the substrate 11, the base layer 13, and the p-type conductive layer 14 are laminated is manufactured, and the multilayer film structure does not contain hydrogen. The heat treatment is performed in an atmosphere, for example, in a vacuum, in a nitrogen gas, or in an atmosphere of an inert gas such as He, Ne, Ar, Kr, and Xe. The temperature at this time is set to 300 ° C to 1100 ° C. The processing time is, for example, 10 minutes to 1 hour. Note that the temperature is a set temperature of the substrate 11.
The n-type conductive layer 17 must also be made of a second group III nitride containing at least Ga, and preferably has a Ga content of at least 50 atomic% with respect to all group III elements. It is preferably at least 70 atomic%, particularly preferably GaN. Thereby, a good pn junction with the p-type conductive layer 14 can be formed.
The p-type conductive layer 14 contains a p-type dopant such as Zn, Be and Mg. Further, the n-type conductive layer 17 contains an n-type dopant such as B, Si, and Ge. Further, Al and In other than Ga can be included. Not only the intentionally added element but also a trace element inevitably taken in depending on the film forming conditions and the like, and a trace impurity contained in the raw material and the material of the reaction tube can be included.
The light emitting layer 15 and the n-type cladding layer 16 can be made of a group III nitride containing at least one of Al, Ga, and In. Then, the n-type cladding layer 16 contains an n-type dopant such as B, Si, and Ge. The light emitting layer 15 can be composed of a single nitride semiconductor layer, but can also be composed of a multilayer film such as a multiple quantum well structure.
The above-mentioned p-type conductive layer 14 to n-type conductive layer 17 can be formed by a known film forming method, and can be easily formed by MOCVD as described above. Furthermore, it can also be formed by the LPE method or the MBE method.
The substrate 11 is made of an oxide single crystal such as a sapphire single crystal, a ZnO single crystal, a LiAlO ₂ single crystal, a LiGaO ₂ single crystal, a MgAl ₂ O ₄ single crystal, a MgO single crystal, a Si single crystal, a SiC single crystal, or the like. substrate group IV or group IV-IV monocrystalline, GaAs single crystal, AlN single crystal, GaN single crystal, and group III-V single crystals, such as AlGaN single crystal, such as boride single crystal such as ZrB _2, known It can be composed of materials.
[0033]
【Example】
(Example)
In this example, a PIN semiconductor light emitting device 20 shown in FIG. 2 was manufactured. As a substrate 11, a C-plane sapphire single crystal having a diameter of 2 inches and a thickness of 500 μm was used and placed in an MOCVD apparatus. In the MOCVD apparatus, H ₂ , N ₂ , TMA (trimethylaluminum), TMG (trimethylgallium), Cp ₂ Mg, NH ₃ , and SiH ₄ are attached as gas systems. After the pressure was set to 100 Torr, the substrate 11 was heated to 1100 ° C. while flowing H ₂ at an average flow rate of 1 m / sec.
Thereafter, a predetermined amount of TMA and NH ₃ was supplied to grow an AlN layer as the underlayer 13 to a thickness of 1 μm. At this time, the supply amounts of TMA and NH ₃ were set such that the film formation rate was 0.3 μm / hr. When the dislocation density in this AlN layer was observed by TEM, it was 1 × 10 ¹⁰ / cm ² . Further, when the X-ray rocking curve of the (002) plane of AlN was measured, it was confirmed that the half-width was 60 seconds and the surface roughness (Ra) was 1.5 ° or less and had a good crystal quality. .
Next, after setting the substrate temperature to 1080 ° C., the pressure was set to normal pressure, TMG, NH ₃ , and Cp ₂ Mg were flowed at a total gas average flow rate of 1 m / sec, and Mg was formed as the p-type conductive layer 14. A doped p-GaN layer was grown 3 μm thick. The amount of the raw material supplied was set so that the film forming speed was 3 μm / hr. Note that Cp ₂ Mg was supplied such that the carrier concentration became 1.0 × 10 ¹⁸ / cm ³ .
Next, N ₂ gas was introduced into the MOCVD apparatus, and the inside of the apparatus was set in a nitrogen atmosphere. Next, the activation temperature of the p-GaN layer was performed by maintaining the substrate temperature at 600 ° C. and maintaining the substrate temperature for 20 minutes.
Next, after the sapphire substrate on which the AlN layer and the p-GaN layer are formed is transferred into another MOCVD apparatus, the substrate temperature is set to 700 ° C., and TMI, TMG, NH ₃ Was flowed at a total gas flow rate of 1 m / sec to form an i-InGaN layer as the light emitting layer 15 as an MQW structure. Thereafter, the TMI was switched to TMA, and SiH ₄ was supplied at a carrier concentration of 1 × 10 ¹⁸ / cm ² to grow an n-AlGaN layer as the n-type cladding layer 16 to a thickness of 20 nm. Thereafter, the TMA is stopped, the substrate temperature is raised to 1000 ° C., and then TMG, NH ₃ and SiH ₄ are supplied to form a Si-doped n-GaN layer as the n-type conductive layer 17 to a thickness of 0.2 μm. did.
Next, these layers are partially etched away to expose a part of the p-GaN layer constituting the p-type conductive layer 14, and the exposed portions are formed of a p-type layer of Au / Ni. An electrode 18 was formed. Further, an n-type electrode 19 made of Al / Ti was formed on the n-GaN layer constituting the n-type conductive layer 17.
When a voltage was applied between the Au / Ni electrode and the Al / Ti electrode to drive the device, and the luminous efficiency was examined, a value of 30 (lm / W) was obtained.
(Comparative Example 1)
A semiconductor light emitting device was manufactured in the same manner as in Example except that a GaN underlayer was formed at a low temperature of 600 ° C. to a thickness of 0.03 μm instead of the AlN underlayer. In this case, no current flowed in the semiconductor light emitting device, and no light was emitted.
(Comparative Example 2)
In this comparative example, a PIN semiconductor light emitting device shown in FIG. 1 was manufactured.
A sapphire single crystal substrate was used as the substrate 1 and was set in the same MOCVD apparatus as in the example. After the substrate 1 was heated to 400 ° C., TMG and NH ₃ were supplied to form a GaN layer as the buffer layer 2 to a thickness of 0.03 μm.
Thereafter, the supply of TMG and NH _{3 is} temporarily stopped, the substrate temperature is set to 1120 ° C., TMG, NH ₃ , and SiH ₄ are supplied, and the n-GaN layer as the underlayer 3 is formed. The film was formed to a thickness of 3 μm at a film formation rate of 3 μm / hr. Next, in the same manner as in the example, the layers from the n-type conductive layer 4 to the p-type conductive layer 7 were formed. After that, the obtained semiconductor light emitting device was placed in a nitrogen atmosphere containing no hydrogen, heated to 600 ° C., and held for 1 hour to perform an activation process.
Then, an Al / Ti n-type electrode 8 and an Au / Ni p-type electrode 9 are formed, and a voltage is applied between the Au / Ni electrode and the Al / Ti electrode to drive them, and the luminous efficiency thereof is examined. As a result, a value of 20 (lm / W) was obtained. In this comparative example, Mg impurities were detected from the n-GaN layer, and it is presumed that the impurities contributed to the decrease in the luminous efficiency.
Further, according to the present invention, a high crystal quality AlN underlayer is formed according to the present invention, and p-GaN, n-AlGaN and n-GaN are formed on the AlN underlayer. The semiconductor light-emitting device having the structure of the substrate / p-type semiconductor layer group / n-type semiconductor layer group has a low crystal quality GaN base film formed thereon, and is compared with the semiconductor light-emitting device having the above-described structure formed on the GaN base film. It can be seen that the resistance of the entire device is reduced and the luminous efficiency is improved.
Although the present invention has been described in detail with reference to the embodiments of the present invention by giving specific examples, the present invention is not limited to the above contents and does not depart from the scope of the present invention. All modifications and changes are possible as far as possible.
For example, the substrate may be subjected to a nitriding treatment, or a pretreatment of the substrate with a group III raw material may be performed. Further, it is also possible to continuously change the composition of the underlayer or change the film forming conditions in stages. Furthermore, for the purpose of further improving the crystallinity of the conductive layer and the light emitting layer, a multilayer laminated structure such as a buffer layer or a strained superlattice is formed between the underlayer and the conductive layer, such as a temperature, a flow rate, a pressure, a raw material supply amount, It can also be inserted by changing the growth conditions such as addition gas and the like.
In the above semiconductor light emitting device, the p-type semiconductor layer group is composed of only the p-type conductive layer. However, a p-type cladding layer is provided on this p-type conductive layer, and the p-type semiconductor layer group is formed. It may be composed of the p-type conductive layer and the p-type clad layer.
Further, in the embodiments of the present invention, a semiconductor light emitting element has been mainly described as a semiconductor element of the present invention. However, the present invention has a laminated structure of a substrate / p-type semiconductor layer group / n-type semiconductor layer group. It can be applied to other elements having. For example, an HBT element and a PIN type light receiving element can be cited. Also in this case, as the resistance of each element is reduced, characteristics such as element efficiency are improved.
Further, in the activation process for the p-type semiconductor layer group, the activation process is promoted by converting the atmosphere in which the activation process is to be performed to plasma or applying a high frequency to the atmosphere. You can also.
Further, in order to suppress impurity diffusion from the p-type semiconductor layer group to the n-type semiconductor layer group, a cap layer made of i-AlGaN may be provided at the interface between them.
[0051]
【The invention's effect】
As described above, according to the present invention, in a semiconductor device in which a p-type semiconductor layer group and an n-type semiconductor layer group are stacked on a predetermined substrate, the p-type semiconductor layer group is sufficiently activated. As a result, it is possible to provide a semiconductor element having a reduced resistance for practical use, and a semiconductor element substrate including the p-type semiconductor layer group which is sufficiently activated. Furthermore, a method for manufacturing the semiconductor device can be provided.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating an example of a conventional semiconductor light emitting device.
FIG. 2 is a configuration diagram illustrating an example of a semiconductor light emitting device of the present invention.
[Explanation of symbols]
1, 11 substrate, 2 buffer layer, 3, 13 underlayer, 4 n-type conductive layer, 5, 15 light-emitting layer, 6 p-type clad layer, 7 p-type conductive layer, 8 n-type electrode, 9 p-type electrode, 10 , 20 semiconductor light emitting device, 14 p-type conductive layer, 16 n-type clad layer, 17 n-type conductive layer, 18 p-type electrode, 19 n-type electrode

Claims (16)

A group III nitride underlayer that contains at least Al, has a dislocation density of 1 × 10 ¹¹ / cm ² or less, and has a half-width of an X-ray rocking curve of a (002) plane of 200 seconds or less on a predetermined base material; And a p-type semiconductor layer group formed of a group III nitride containing at least Ga and formed by activation treatment, which is formed above the group III nitride base layer. A substrate for a semiconductor device, characterized in that: 2. The semiconductor element substrate according to claim 1, wherein a Ga content in the group III nitride constituting the p-type semiconductor layer group is 50 atomic% or more based on all group III elements. 3. The semiconductor element substrate according to claim 1, wherein an Al content of all the group III elements in the group III nitride underlayer is 50 atomic% or more. 4. The substrate according to claim 3, wherein the group III nitride underlayer is made of AlN. The substrate for a semiconductor device according to claim 1, wherein the group III nitride underlayer is formed at a temperature of 1100 ° C. or higher by MOCVD. The semiconductor device according to any one of claims 1 to 5, further comprising an n-type semiconductor layer group made of a group III nitride containing at least Ga, above the p-type semiconductor layer group. substrate. The semiconductor device substrate according to claim 6, further comprising a light emitting layer between the p-type semiconductor layer group and the n-type semiconductor layer group. A group III nitride underlayer that contains at least Al, has a dislocation density of 1 × 10 ¹¹ / cm ² or less, and has a half-width of an X-ray rocking curve of a (002) plane of 200 seconds or less on a predetermined base material; A p-type semiconductor layer group formed of the first group-III nitride containing at least Ga and formed on the group-III nitride base layer and activated, and formed on the p-type semiconductor layer group And an n-type semiconductor layer group made of a second group III nitride containing at least Ga. 9. The semiconductor device according to claim 8, wherein the Ga content in the first group III nitride constituting the p-type semiconductor layer group is 50 atomic% or more based on all group III elements. 10. . The Ga content in the second group III nitride constituting the n-type semiconductor layer group is equal to or more than 50 atomic% with respect to all group III elements. Semiconductor element. The semiconductor device according to any one of claims 8 to 10, wherein an Al content of all the group III elements in the group III nitride underlayer is 50 atomic% or more. The semiconductor device according to claim 11, wherein the group III nitride underlayer is made of AlN. The light-emitting layer is provided between the p-type semiconductor layer group and the n-type semiconductor layer group, and the semiconductor element constitutes a semiconductor light-emitting element. Semiconductor element. 14. The semiconductor device according to claim 8, wherein the group III nitride underlayer is formed at a temperature of 1100 [deg.] C. or more by a MOCVD method. On a predetermined base material, a group III nitride underlayer containing at least Al, having a dislocation density of 1 × 10 ¹¹ / cm ² or less and an X-ray rocking curve half width of (002) plane of 200 seconds or less is used. Forming,
Forming a p-type semiconductor layer group made of a first group III nitride containing at least Ga above the group III nitride underlayer;
Activating the p-type semiconductor layer group;
Forming an n-type semiconductor layer group made of a second group III nitride containing at least Ga on the p-type semiconductor layer group;
A method for manufacturing a semiconductor device, comprising: The method of claim 15, wherein the group III nitride underlayer is formed at a temperature of 1100 ° C. or more by MOCVD.

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