JP2004165235A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device lessening unevenness of a distribution in a wafer face of a residual polarization amount by enlarging the residual polarization amount more than the conventional, and to provide its manufacturing method. <P>SOLUTION: The manufacturing method has a process for forming an interlayer insulating film 10 upward of a silicon substrate 1; a process for forming a lower side layer 11a on an interlayer insulating film 11; a process for exposing the lower side layer 11a to the atmosphere; a process for forming an upper side layer 11b on the lower side layer 11a thereafter, and making the upper side layer 11b and the lower side 11a a lower electrode conductive film 11; a process for forming a ferroelectric film 12 on the upper side layer 11b; a process for forming an upper electrode conductive layer 13 on the ferroelectric film 12; a process for forming a capacitor Q provided with a lower electrode 11c consisting of the lower electrode conductive film 11, a capacitor dielectric film 12a consisting of the ferroelectric film 12, and an upper electrode 13a consisting of the upper electrode conductive film 13. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the same.
[0002]
[Prior art]
Flash memories and ferroelectric memories (FeRAM) are known as nonvolatile memories that can store information even when the power is turned off.
[0003]
Among them, a flash memory stores information by accumulating electric charges in a floating gate of an insulated gate field effect transistor (IGFET). When writing information, a tunnel current flows through a gate insulating film. Need, and require a relatively high voltage.
[0004]
On the other hand, FeRAM has a ferroelectric capacitor, uses a ferroelectric film as the capacitor dielectric film, and generates a spontaneous polarization in the capacitor dielectric film by applying a write voltage between the upper electrode and the lower electrode. Let it. The spontaneous polarization remains even after the power is turned off due to the hysteresis characteristic of the ferroelectric substance, and information is read out by detecting its magnitude and polarity. Such a FeRAM operates at a lower voltage than a flash memory, and can perform high-speed writing with low power consumption.
[0005]
The characteristics of a ferroelectric capacitor largely depend on the crystallinity of a capacitor dielectric film, and the better the crystallinity, the better the characteristics. Therefore, as the uppermost layer of the lower electrode, a Pt film in which the orientation is aligned in one direction and the orientation is enhanced is adopted, and the crystallinity of the capacitor dielectric film is enhanced by the action of the Pt film. Since the polarization direction of the capacitor dielectric film having the perovskite structure is the (001) direction, it is preferable that the orientation is also aligned in the (001) direction. However, since it is actually difficult to form such a capacitor dielectric film, a Pt film having a uniform orientation in the (111) direction is formed, and the capacitor dielectric film thereon is also formed in the (111) direction. The orientation should be uniform.
[0006]
However, since the Pt film is easily peeled off when formed on the insulating film, a Ti film is formed under the Pt film to prevent the peeling. The Ti film has a function of aligning the orientation of the Pt film in addition to preventing peeling.
[0007]
Therefore, the lower electrode has a two-layered structure of a Ti film and a Pt film. The method for forming such a lower electrode and the processing after the formation are as follows.
[0008]
The first method is to form a Pt film continuously after forming a Ti film. ₂ The adhesion to the film is improved, and the increase in the resistance of the lower electrode can be suppressed (for example, see Patent Document 1).
[0009]
A second method is a method of performing a rapid heat treatment on the lower electrode after forming a lower electrode by forming a Ti film and a Pt film successively and before forming a ferroelectric film (for example, , Patent Document 2). According to this method, since the orientation of the lower electrode is aligned in the (111) direction, the orientation of the ferroelectric film thereon is also enhanced, and the spontaneous polarization of the capacitor is enhanced.
[0010]
A third method is to form a lower electrode made of a Ti film and a Pt film, form a PZT film thereon as a ferroelectric film, and then perform a heat treatment on the PZT film (for example, see Patent Reference 3). According to this method, a Pb-Pt-Ti-O reaction layer is formed at the interface between the PZT film and the Pt film, and a capacitor with less deterioration can be provided.
[0011]
[Patent Document 1]
JP-A-9-223779 (paragraph number 0062)
[Patent Document 2]
JP-A-2000-91511 (paragraph number 0032)
[Patent Document 3]
JP 2000-40779 A (Paragraph No. 0019)
[0012]
[Problems to be solved by the invention]
By the way, there are various indexes indicating the characteristics of the ferroelectric capacitor. Among them, the most important one is the remanent polarization Q _sw There is. Residual polarization Q _sw Is the amount of polarization remaining in the capacitor dielectric film when the power is turned off. The larger this value is, the easier it is to distinguish between "0" and "1".
[0013]
However, the first to third methods described above use the remanent polarization Q _sw Is not taken into account, the amount of remanent polarization Q _sw And the amount of remanent polarization Q _sw There is room for improvement in reducing the dispersion of the distribution in the wafer plane.
[0014]
The present invention has been made in view of the problems of the conventional example, and can increase the amount of remanent polarization compared to the related art, and reduce the variation in the distribution of the amount of remanent polarization in the wafer surface. And a method for manufacturing the same.
[0015]
[Means for Solving the Problems]
The above object is achieved by insulating a semiconductor substrate, an insulating film formed above the semiconductor substrate, a lower electrode in which a lower layer and an upper layer are sequentially stacked, a capacitor dielectric film, and an upper electrode. And a capacitor formed sequentially on the film, wherein a natural oxide film of the lower layer is formed on the surface of the lower layer of the lower electrode.
[0016]
A step of forming an insulating film above a semiconductor substrate; a step of forming a lower layer of a conductive film for a lower electrode on the insulating film; a step of exposing the lower layer to the atmosphere; Exposing the lower electrode to the atmosphere, forming an upper layer of the lower electrode conductive film on the lower layer, and forming the upper layer and the upper layer into a lower electrode conductive film. Forming a dielectric film, forming an upper electrode conductive film on the ferroelectric film, and patterning the lower electrode conductive film, the ferroelectric film, and the upper electrode conductive film. Forming a capacitor having a lower electrode made of the lower electrode conductive film, a capacitor dielectric film made of the ferroelectric film, and an upper electrode made of the upper electrode conductive film. The problem is solved by a method for manufacturing a semiconductor device.
[0017]
Next, the operation of the present invention will be described.
[0018]
According to the present invention, after exposing the lower layer of the lower electrode conductive film to the atmosphere, the upper layer of the lower electrode conductive film is formed on the lower layer. By adopting such a method, the amount of remanent polarization Q can be increased as compared with the related art while securing the strength of the orientation of the ferroelectric film required for the FeRAM. _sw And the amount of remanent polarization Q in the wafer plane _sw Is smaller than before. Further, the retention characteristic, the imprint characteristic, and the fatigue loss of the capacitor are improved as compared with the related art without deteriorating the leak current characteristic. Moreover, such advantages do not depend on the film formation temperature of the upper layer.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
1 to 23 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG. 24 is a plan view corresponding to FIG.
[0021]
First, steps required until a sectional structure shown in FIG.
[0022]
As shown in FIG. 1, an element isolation insulating film 2 is formed on a surface of an n-type or p-type silicon (semiconductor) substrate 1 by a LOCOS (Local Oxidation of Silicon) method. The element isolation insulating film 2 may employ an STI (Shallow Trench Isolation) method other than the LOCOS method.
[0023]
After forming such an element isolation insulating film 2, p-type impurities and n-type impurities are selectively introduced into predetermined active regions (transistor formation regions) in the memory cell region A and the peripheral circuit region B of the silicon substrate 1. Thus, a p-well 3a and an n-well 3b are formed. Although not shown in FIG. 1, a p-well (not shown) is also formed in the peripheral circuit region B to form a CMOS.
[0024]
Thereafter, the surface of the active region of the silicon substrate 1 is thermally oxidized to form a silicon oxide film as the gate insulating film 4.
[0025]
Next, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the silicon substrate 1, and an n-type impurity is ion-implanted on the p-well 3a and a p-type impurity is ion-implanted on the n-type well 3b. Reduce the resistance of the silicon film. After that, the silicon film is patterned into a predetermined shape by photolithography to form gate electrodes 5a to 5c.
[0026]
Two gate electrodes 5a and 5b are arranged substantially in parallel on one p-well 3a in the memory cell region A, and these gate electrodes 5a and 5b constitute a part of the word line WL.
[0027]
Next, in the memory cell region A, an n-type impurity is ion-implanted into the p-well 3a on both sides of the gate electrodes 5a and 5b to form an n-type impurity diffusion region 6a serving as a source / drain of the n-channel MOS transistor. . At the same time, an n-type impurity diffusion region is also formed in a p-well (not shown) of the peripheral circuit region B. Subsequently, in the peripheral circuit region B, a p-type impurity is ion-implanted into the n-well 3b on both sides of the gate electrode 5c to form a p-type impurity diffusion region 6b serving as a source / drain of the p-channel MOS transistor.
[0028]
Subsequently, after an insulating film is formed on the entire surface of the silicon substrate 1, the insulating film is etched back to leave the sidewall insulating film 7 only on both sides of the gate electrodes 5a to 5c. As the insulating film, for example, silicon oxide (SiO 2) is formed by a CVD method. ₂ ) Is formed.
[0029]
Further, using gate electrodes 5a-5c and side wall insulating film 7 as a mask, n-type impurity ions are again implanted into p-well 3a to make n-type non-diffusion region 6a an LDD structure, and n-well 3b By implanting p-type impurity ions into the inside again, p-type impurity diffusion region 6b also has an LDD structure.
[0030]
Note that the n-type impurity and the p-type impurity are separated by using a resist pattern.
[0031]
As described above, in the memory cell region A, an n-type MOSFET is constituted by the p-well 3a, the gate electrodes 5a and 5b, and the n-type impurity diffusion regions 6a on both sides thereof, and in the peripheral circuit region B, the n-type MOSFET 3b , Gate electrode 5c and p-type impurity diffusion regions 6b on both sides thereof constitute a p-type MOSFET.
[0032]
Next, after a refractory metal film, for example, a film of Ti or Co is formed on the entire surface, the refractory metal film is heated to form a refractory metal film on the surfaces of the n-type impurity diffusion region 6a and the p-type impurity diffusion region 6b. Metal silicide layers 8a and 8b are formed. After that, the unreacted refractory metal film is removed by wet etching.
[0033]
Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed as a cover film 9 on the entire surface of the silicon substrate 1 by a plasma CVD method. Further, silicon dioxide (SiO 2) is used as the first interlayer insulating film 10 by a plasma CVD method using a TEOS gas. ₂ ) Is grown on the cover film 9 to a thickness of about 1.0 μm.
[0034]
Subsequently, the first interlayer insulating film 10 is polished by a chemical mechanical polishing (CMP) method to planarize the surface.
[0035]
Next, steps required until a structure illustrated in FIG.
[0036]
First, the film forming temperature and the film forming time are set to 20 ° C. and 14 seconds, respectively, and a Ti layer is formed on the first interlayer insulating film 10 as a lower layer 11 a of the lower electrode conductive film by a DC sputtering method to a thickness of about 20 nm. Formed to a thickness of The film forming temperature of the lower layer 11a is not limited to 20 ° C., and may be a temperature of 0 ° C. to 300 ° C. Further, as the lower layer 11a, a layer made of any of Ti, Pt-Ti alloy, Ir-Ti alloy, and Ru-Ti alloy may be formed in addition to the Ti layer.
[0037]
After that, the silicon substrate 1 is taken out of the chamber used for forming the lower layer 11a, and the lower layer 11a is exposed to the atmosphere at room temperature (about 24 ° C.) for about 2 hours, and its surface is naturally oxidized or absorbed. As a result, a thin native oxide film of Ti is formed on the surface of the lower layer 11a. The time of exposure to the atmosphere is not limited to the above, and may be 5 minutes to 7 days. The temperature of the silicon substrate 1 at that time is not limited to the above, and may be 0 ° C to 100 ° C. The effect obtained by such exposure to the atmosphere will be described later in detail.
[0038]
Next, steps required until a structure shown in FIG.
[0039]
First, the film formation temperature and the film formation time are set to 100 ° C. and 112 seconds, respectively, and a Pt layer is formed on the lower layer 11a as the upper layer 11b of the lower electrode conductive film by a DC sputtering method to a thickness of about 175 nm. Formed. As a result, the lower electrode conductive film 11 composed of the lower layer 11a and the upper layer 11b is formed. Thus, by forming the Pt layer (upper layer 11b) on the Ti layer (lower layer 11a), the orientation of the Pt layer is aligned in the (111) direction by the action of the Ti layer, and the Pt layer is formed later. The orientation of the PZT film can be aligned in the (111) direction. Further, the lower layer 11a also plays a role of increasing the adhesion strength between the lower electrode conductive film 11 and the first interlayer insulating film 10.
[0040]
In addition, as the upper layer 11b, in addition to the Pt layer, a single-layer or multilayer structure including any of Pt, Ir, Ru, Pd, PtOx, IrOx, RuOx, and PdOx may be formed.
[0041]
Next, steps required until a structure illustrated in FIG. 4 is formed will be described.
[0042]
First, PLZT (lead lanthanum zirconate titanate; (Pb, La) (Zr, Ti) O ₃ ) Is formed to a thickness of 100 to 300 nm, for example, 240 nm on the conductive film 11 for the lower electrode, and this is used as the ferroelectric film 12. In some cases, PLZT may be slightly doped with calcium (Ca) or strontium (Sr). Also, instead of PLZT, PZT (Pb (Zr, Ti) O ₃ ), (Sr, Ti) O ₃ , (Ba, Sr) TiO ₃ Materials such as Bi ₄ Ti ₂ O ₁₂ The ferroelectric film 12 may be made of a Bi layer structure compound such as described above. Further, as a method of forming the ferroelectric film 12, there are a spin-on method, a sol-gel method, a MOD (Metal Organic Deposition) method, and a MOCVD method, in addition to the above-described sputtering method.
[0043]
Subsequently, the silicon substrate 1 is placed in a mixed gas atmosphere of argon and oxygen, and the ferroelectric film 12 is formed at a temperature of 600 ° C. or more, for example, at 725 ° C. for 20 seconds at a temperature increase rate of 125 ° C./sec. The PLZT film is crystallized by subjecting the PLZT film to RTA (Rapid Thermal Annealing). According to such a crystallization process, Pt constituting the upper layer 11b is densified, and the interdiffusion between Pt and O in the vicinity of the interface between the lower electrode conductive film 11 and the ferroelectric film 12 is suppressed. You can also.
[0044]
After such a ferroelectric film 12 is formed, iridium oxide (IrO 2) is formed thereon as a conductive film 13 for an upper electrode. ₂ ) A film is formed to a thickness of 100 to 300 nm, for example, 200 nm by a sputtering method. As the conductive film 13 for the upper electrode, a platinum film or a ruthenium strontium oxide (SRO) film may be formed by a sputtering method.
[0045]
Next, steps required until a structure shown in FIG.
[0046]
First, after forming a resist pattern (not shown) in the shape of an upper electrode on the conductive film 13 for the upper electrode, the conductive film 13 for the upper electrode is etched using the resist pattern as a mask. The conductive film 13 is used as the upper electrode 13a of the capacitor.
[0047]
Then, after removing the resist pattern, the ferroelectric film 12 is annealed in an oxygen atmosphere at a temperature of 650 ° C. for 60 minutes. This annealing is performed to recover damage that has entered the ferroelectric film 12 during sputtering and etching.
[0048]
Subsequently, in the memory cell region A, the ferroelectric film 12 is etched in a state where a resist pattern (not shown) is formed on the capacitor upper electrode 13a and its periphery, and the remaining ferroelectric film 12 is removed by the dielectric of the capacitor. Used as the body film 12a. After removing the resist pattern, the ferroelectric film 12 is annealed at 650 ° C. for 60 minutes in an oxygen atmosphere. This annealing is performed in order to degas the moisture and the like absorbed by the underlying film.
[0049]
Next, as shown in FIG. 6, on the upper electrode 13a, the dielectric film 12a, and the lower electrode conductive film 11, a PLZT film is formed as an encapsulation layer 14 to a thickness of 50 nm by a sputtering method at room temperature. . The encap layer 14 is formed to protect the dielectric film 12a, which is easily reduced, from hydrogen and to block the entry of hydrogen into the dielectric film 12a. Note that a PZT film, an alumina film, or a titanium oxide film may be formed as the encapsulation layer 14.
[0050]
Thereafter, the ferroelectric film 12 under the encap layer 14 is rapidly heat-treated in an oxygen atmosphere at 700 ° C. for 60 seconds at a temperature increase rate of 125 ° C./sec to improve the film quality.
[0051]
Next, a resist is applied on the encapsulation layer 14, which is exposed and developed to leave on and around the upper electrode 13a and the dielectric film 12a. Then, using the resist as a mask, the encapsulation layer 14 and the lower electrode conductive film 11 are etched, and the remaining lower electrode conductive film 11 is used as the lower electrode 11c of the capacitor (see FIG. 7). The etching of the encapsulation layer 14 and the lower electrode conductive film 11 is performed by dry etching using chlorine.
[0052]
After removing the resist pattern, the ferroelectric film 12 is annealed in an oxygen atmosphere at 650 ° C. for 60 minutes to recover from damage.
[0053]
Thereby, as shown in FIG. 7, a capacitor Q including the lower electrode 11c, the dielectric film 12a, and the upper electrode 13a is formed on the first interlayer insulating film 10.
[0054]
FIG. 24 shows a planar configuration excluding the insulating film in the memory cell region A. A plurality of upper electrodes 13a are formed on one rectangular dielectric film 12a. The lower electrode 11c below has a size extending to the side of the dielectric film 12a. FIG. 24 also illustrates contact holes, bit lines, and the like, which will be described later.
[0055]
Next, as shown in FIG. 8, a 1200 nm-thick SiO 2 film is formed on the capacitor Q and the first interlayer insulating film 10 as a second interlayer insulating film 15. ₂ After the film is formed by the CVD method, the surface of the second interlayer insulating film 15 is flattened by the CMP method. The second interlayer insulating film 15 is grown by using silane (SiH ₄ ) May be used or TEOS may be used. The surface of the second interlayer insulating film 15 is planarized until the thickness of the upper surface of the upper electrode 13a becomes 200 nm.
[0056]
Next, as shown in FIG. 9, a resist 16 is applied on the second interlayer insulating film 15, and is exposed and developed to form a resist 16 on the impurity diffusion layer 6a in the memory cell region A and a capacitor lower electrode 11c. The hole forming windows 16a to 16e are formed on the semiconductor device and on the impurity diffusion layer 6b in the peripheral circuit region B, respectively.
[0057]
Subsequently, the first and second interlayer insulating films 10 and 15 and the cover film 9 are dry-etched to form contact holes 15a to 15e on the impurity diffusion layer 6a in the memory cell region A and the capacitor lower electrode 11c. At the same time, contact holes 15d and 15e are also formed on impurity diffusion layer 6b in peripheral circuit region B. The first and second interlayer insulating films 10 and 15 and the cover film 9 are made of a CF-based gas such as CHF. ₃ To CF ₄ , Ar is added using a mixed gas.
[0058]
In this etching, since the etching rate of the PLZT encapsulation layer 14 covering the lower electrode 11c of the capacitor Q is smaller than that of the other insulating films, the shallow contact hole 15c formed on the lower electrode 11a The difference in the etching depth of the contact holes 15a, 15b, 15d, and 15e is absorbed by the encapsulation layer 14.
[0059]
Each of the contact holes 15a to 15e has a tapered shape in which the upper portion is wide and the lower portion is narrow, and the diameter of the contact holes 15a, 15b, 15d, and 15e above the impurity diffusion layers 6a and 6b at the center in the depth direction is about 0.1 mm. 5 μm.
[0060]
Next, after removing the resist 16, as shown in FIG. 10, RF pretreatment etching is performed on the second interlayer insulating film 15 and the inner surfaces of the contact holes 15 a to 15 e, and then a sputtering method is performed thereon. To form a titanium (Ti) film with a thickness of 20 nm and a titanium nitride (TiN) film with a thickness of 50 nm. Furthermore, tungsten fluoride gas (WF ₆ ), A tungsten film 18 is formed on the glue film 17 by a CVD method using a mixed gas of argon and hydrogen. In the initial stage of the growth of the tungsten film 18, silane (SiH ₄ ) Gas is also used. The tungsten film 18 has a thickness that completely fills each of the contact holes 15a to 15e, for example, about 500 nm on the second interlayer insulating film 15.
[0061]
Since each of the contact holes 15a to 15e has a tapered shape, it is difficult to form a cavity (also referred to as a void or a void) in the tungsten film 18 buried therein.
[0062]
Next, as shown in FIG. 11, the tungsten film 18 and the glue film 17 on the second interlayer insulating film 15 are removed by the CMP method, and are left only in the contact holes 15a to 15e. Thus, the tungsten film 18 and the glue film 17 in the contact holes 15a to 15e are used as plugs 18a to 18e. Here, if etch-back is used instead of the CMP method, different etching gases are required for etching the tungsten film 18 and for etching the glue film 17, respectively, so that the etching management is troublesome.
[0063]
In one p-well 3a of the memory cell region A, the first plug 18a on the n-type impurity diffusion region 6a sandwiched between the two gate electrodes 5a and 5b is connected to a bit line described later, The two second plugs 18b are connected to the upper electrode 13a of the capacitor Q via a wiring described later. Further, as shown in FIG. 24, the contact hole 15c above the lower electrode 11c and the plug 18c therein are formed in a portion protruding from the dielectric film 12a, but in the drawings after FIG. In order to facilitate understanding, it is drawn for the sake of convenience so as to extend over a plurality of plugs 18a and 18b on the impurity diffusion layer 6a in the memory cell region A.
[0064]
After that, in order to remove moisture adhering to the surface of the second interlayer insulating film 15 or permeating into the inside in a process such as a cleaning process after forming the contact holes 15a to 15e and a cleaning process after the CMP, a vacuum chamber is again formed. The second interlayer insulating film 15 is heated at a temperature of 390 ° C. to release water to the outside. After such a dehydration process, the second interlayer insulating film 15 is heated while heating ₂ Annealing for improving film quality by exposure to plasma is performed for, for example, 2 minutes.
[0065]
Subsequently, as shown in FIG. 12, a SiON film is formed to a thickness of, for example, 100 nm on the second interlayer insulating film 15 and the plugs 18a to 18e by a plasma CVD method. This SiON film is made of silane (SiH ₄ ) And N ₂ It is formed using a mixed gas of O and is used as an antioxidant film 19 for preventing oxidation of the plugs 18a to 18e.
[0066]
Next, as shown in FIG. 13, the encapsulation layer 14 and the second interlayer insulating film 15 are patterned by photolithography to form a contact hole 15f on the upper electrode 13a of the capacitor Q.
[0067]
Thereafter, the dielectric film 12a of the capacitor Q is annealed in an oxygen atmosphere at 550 ° C. for 60 minutes to improve the film quality of the dielectric film 12a. In this case, oxidation of the plugs 18a to 18e is prevented by the antioxidant film 19.
[0068]
Thereafter, as shown in FIG. 14, the SiON oxidation preventing film 19 is dry-etched using a CF-based gas. Then, each surface of the plugs 18a to 18e and the upper electrode 13a is etched by about 10 nm by RF etching to expose a clean surface.
[0069]
Next, as shown in FIG. 15, a four-layer conductive film containing aluminum is formed on the second interlayer insulating film 15, the plugs 18a to 18e, and the contact holes 15f of the capacitor Q by a sputtering method. The conductive films are, in order from the bottom, a 50-nm-thick titanium nitride film, a 500-nm-thick copper-containing (0.5%) aluminum film, a 5-nm-thick titanium film, and a 100-nm-thick titanium nitride film.
[0070]
Then, the conductive film is patterned by photolithography to form contact pads 20a and 20c and first-layer wirings 20b and 20d to 20f, as shown in FIG.
[0071]
Here, in the memory cell region A, a contact pad 20a is formed on the plug 18a between the two gate electrodes 5a and 5b on the p well 3a. The plug 18b between the element isolation insulating film 2 and the gate electrodes 5a, 5b is connected to the upper electrode 13a of the capacitor Q by a wiring 20b through a contact hole 15f. Further, another contact pad 20c is formed on the plug 18c on the lower electrode 11a of the capacitor Q in the arrangement shown in FIG.
[0072]
Note that the resist pattern used for the photolithography method is removed after forming the contact pads 20a, the wirings 20b, and the like.
[0073]
Next, as shown in FIG. 16, SiO 2 is formed by plasma CVD using TEOS as a source. ₂ A film is formed as a third interlayer insulating film 21 to a thickness of 2300 nm, and the second interlayer insulating film 21 covers the second interlayer insulating film 15, the contact pads 20a and 20c, the wiring 20b, and the like. Subsequently, the surface of the third interlayer insulating film 21 is planarized by the CMP method.
[0074]
Thereafter, the third interlayer insulating film 21 is heated at a temperature of 390 ° C. in a vacuum chamber to release water to the outside. After such a dehydration process, the third interlayer insulating film 21 is heated while ₂ Dehydration and film quality improvement are performed by exposure to O plasma.
Subsequently, as shown in FIG. 17, SiO 2 is formed by plasma CVD using TEOS. ₂ A protective insulating film 22 is formed on the third interlayer insulating film 21 to a thickness of 100 nm or more. When voids are formed in the third interlayer insulating film 21, the voids are closed by the protective insulating film 22. Thereafter, the protective insulating film 22 is dehydrated in a vacuum chamber at a temperature of 390 ° C. ₂ Dehydration and film quality improvement are performed by exposure to O plasma.
[0075]
Next, steps required until a structure as shown in FIG.
[0076]
First, the third interlayer insulating film 21 and the protective insulating film 22 are patterned by the photolithography method, so that the third interlayer insulating film 21 and the protective insulating film 22 are patterned on the contact pad 20a in the middle of the p well 3a in the memory cell region A and on the lower electrode 11a of the capacitor Q. Holes 22a to 22c are formed on the wiring 20c of FIG.
[0077]
Next, after performing RF pretreatment etching on the upper surface of the protective insulating film 22 and the inner surfaces of the holes 22a to 22c, a glue film 23 made of titanium nitride (TiN) having a thickness of 90 nm to 150 nm is formed by sputtering. Thereafter, a blanket tungsten film 24 is formed to have a thickness of, for example, 800 nm by the CVD method so as to fill the holes 22a to 22c. WF is used to grow the blanket tungsten film 24. ₆ , H ₂ The source gas containing is used. By the way, the reason why the thickness of the glue film 23 is set to 90 nm or more is that H used for forming a relatively thick tungsten film 24 is used. ₂ This is to alleviate the damage to the capacitor Q by penetrating into the protective insulating film 22. As described above, since the tungsten film 18 shown in FIG. 10 is formed thin to fill the small diameter contact holes 15a to 15f, the thickness of the TiN glue film 17 thereon is as thin as 50 nm. You may.
[0078]
Next, as shown in FIG. 19, the tungsten film 24 is etched back and left only in the holes 22a to 22c, and the tungsten film 24 in the holes 22a to 22c is used as second-layer plugs 25a to 25c. Thus, the TiN glue film 23 remains on the protective insulating film 22.
[0079]
Next, as shown in FIG. 20, a conductive film 26 having a three-layer structure is formed on the TiN glue film 23 and the plugs 25a to 25c by a sputtering method. The conductive film 26 is, in order from the bottom, a copper-containing (0.5%) aluminum film having a thickness of 500 nm, a titanium film having a thickness of 5 nm, and a titanium nitride film having a thickness of 100 nm.
[0080]
Then, the conductive film 26 is patterned by photolithography as shown in FIG. 21 to form a second-layer contact pad and a second-layer aluminum wiring. For example, in the memory cell region A, a bit line 26a connected via plugs 18a and 25a and a contact pad 20a is formed above the impurity diffusion layer 6a at the center of the p well 3a. Above 11c, a second layer wiring 26b connected via plugs 18c and 25b and contact pad 20c is formed, and a first layer aluminum wiring 20f in peripheral circuit region B is formed via plug 25c. A second-layer aluminum wiring 26c is formed to be connected. FIG. 24 shows a plan view of this state.
[0081]
Next, the steps as shown in FIGS. 17 to 21 are repeated to form a structure as shown in FIG. The process is as follows.
[0082]
First, SiO 2 was formed by plasma CVD using TEOS as a source. ₂ A film is formed as the fourth interlayer insulating film 27 to a thickness of 2300 nm, and the lower protective insulating film 22 and the wirings 26a to 26c are covered with the interlayer insulating film 27. Subsequently, the surface of the fourth interlayer insulating film 27 is planarized by the CMP method. Thereafter, the fourth interlayer insulating film 27 is heated at a temperature of 390 ° C. in a vacuum chamber to release water to the outside. After such a dehydration process, the fourth interlayer insulating film 27 is ₂ Exposure to O plasma improves film quality.
[0083]
Subsequently, SiO 2 is formed by plasma CVD using TEOS. ₂ The upper protective insulating film 28 is formed on the fourth interlayer insulating film 27 to a thickness of 100 nm or more. Thereafter, the protective insulating film 28 is dehydrated at a temperature of 390 ° C. in a vacuum chamber. ₂ Exposure to O plasma improves film quality. Further, the fourth interlayer insulating film 27 and the protective insulating film 28 are patterned by photolithography to form a hole 27a on the second-layer aluminum wiring 26b electrically connected to the lower electrode 11c of the capacitor Q. I do. The photolithography method uses a resist mask, but is removed after forming the hole 27a.
[0084]
Next, a glue film 29 made of titanium nitride (TiN) having a thickness of 90 nm to 150 nm is formed on the upper surface of the protective insulating film 28 and the inner surface of the hole 27a by a sputtering method, and then a blanket is formed so as to fill the hole 27a. A tungsten film is formed to a thickness of 800 nm by a CVD method. Further, the bracket tungsten film is etched back and left only in the hole 27a, and the bracket tungsten film in the hole 27a is used as a third-layer plug 30.
[0085]
Thus, the TiN glue film 29 remains on the protective insulating film 28.
[0086]
Thereafter, a conductive film having a two-layer structure is formed on the glue film 29 and the plug 30 by a sputtering method. The conductive film is, in order from the bottom, a copper-containing (0.5%) aluminum film having a thickness of 500 nm and a titanium nitride film having a thickness of 100 nm. Then, the conductive film is patterned by a photolithography method to form third-layer aluminum wirings 31a to 31c.
[0087]
Next, as shown in FIG. 23, SiO 2 is formed by a plasma CVD method using TEOS as a source. ₂ A protective insulating film 32 is formed to a thickness of 100 nm. Thereafter, the protective insulating film 32 is heated at a temperature of 390 ° C. in a vacuum chamber to release water to the outside. After such a dehydration treatment, the protective insulating film 32 is ₂ Exposure to O plasma improves dehydration and film quality.
[0088]
Subsequently, a silicon nitride film 33 is formed to a thickness of 350 nm on the protective insulating film 32 by a CVD method to prevent water from entering the protective insulating film 32.
[0089]
Thereafter, a polyimide film is applied to a thickness of 3 μm on the silicon nitride film 33 and baked at 230 ° C. for 30 minutes to form a cover film.
[0090]
Through the steps so far, the FeRAM is completed.
[0091]
As described above, in the present embodiment, after forming the Ti lower layer 11a of the lower electrode conductive film 11, it is once exposed to the air, and then the Pt upper layer 11b is formed. The effect obtained by such a method will be described below.
[0092]
FIG. 25 shows a conventional example in which a Pt upper layer 11b is continuously formed without exposing the Ti lower layer 11a to the air after forming the Ti lower layer 11a, and the Pt upper layer 11b and the PLZT ferroelectric film 12 in the present invention. 5 is a graph showing the results obtained by investigating the strength of each orientation of the above. An X-ray diffractometer (XRD) was used for the investigation. The strength of the (222) direction of the Pt upper layer 11b was measured, and the strength of the (111) direction of the PLZT ferroelectric film 12 was measured. In the series of graphs, those indicated by “discontinuous W / N1 to W / N3” indicate the present invention, and “W / N1 to W / N3” indicate wafer numbers. On the other hand, what is indicated by “continuous W / N1 to W / N3” indicates a conventional example in which a Ti lower layer 11a and a Pt upper layer 11b are continuously formed. This conventional example corresponds to the technique described in Japanese Patent Application Laid-Open No. 9-223779, in which the film forming conditions for the layers 11a and 11b are the same as in the present embodiment.
[0093]
As shown in FIG. 25, in the present embodiment, the strength of the orientation of the ferroelectric film 12 is slightly smaller than that of the conventional example, but 500,000 cps required for the FeRAM can be secured.
[0094]
FIG. 26 shows the residual polarization Q when a voltage of 3 V is applied to the capacitor Q. _sw 9 is a cumulative graph showing the results of examining at 71 points in the wafer plane. The cumulative probability is taken on the vertical axis of the graph. In the drawing, there are three series for the present invention and the conventional example, respectively, and each series corresponds to the three wafers in FIG. In this investigation, comparative examples different from the present invention and the conventional example were investigated. In this comparative example, after the Ti lower layer 11a was formed, it was oxidized by RTA in a mixed atmosphere of oxygen and argon, and the Pt upper layer 11b was formed again in vacuum. Note that, in the comparative example, the film forming conditions of each of the layers 11a and 11b are the same as in the present embodiment.
[0095]
As can be understood from FIG. 26, the remanent polarization Q _sw Is larger than that of the conventional example. Furthermore, when the Ti lower layer 11b is thermally oxidized as in the comparative example, the residual polarization Q _sw It is also understood that is reduced.
[0096]
FIG. 27 shows the residual polarization Q _sw 7 is a graph obtained by calculating an average value and a standard deviation within a wafer surface of FIG.
[0097]
As shown in FIG. 27, in the present invention, the amount of remanent polarization Q _sw Are the largest, and the standard deviation is the smallest among the three. _sw It can be understood that the distribution in the wafer surface becomes better. This is because, when the surface of the Ti lower layer 11b is naturally oxidized, Ti is hardly diffused into the ferroelectric film 12 when the PLZT ferroelectric film 12 is subjected to crystallization annealing, and the PLZT ferroelectric film 12 This is because the characteristics of the interface between the Pt upper layer 11b and the Pt upper layer 11b are improved.
[0098]
FIG. 34 shows the residual polarization Q _sw Is a graph of the distribution in the wafer plane. As shown therein, the standard deviation in the present invention falls in the range of 0.372 to 0.425, which is smaller than the conventional example (0.539 to 1.006).
[0099]
FIGS. 28A and 28B are cumulative graphs of the leak current density of the capacitor Q in the present invention, the conventional example, and the comparative example used in the investigation of FIG. In FIGS. 28A and 28B, a voltage having a magnitude of 6 V is applied to the capacitor Q, but the polarity of the voltage is opposite between FIGS. 28A and 28B. The leakage current density was measured at 71 points in the wafer plane.
[0100]
As understood from FIGS. 28A and 28B, in the comparative example in which the Ti lower layer 11a is thermally oxidized, the leak current density is increased by about 1 to 1.5 digits compared to the conventional example. On the other hand, when the Ti lower layer 11a is spontaneously oxidized as in the present invention, the characteristics of the leak current are almost the same as those of the conventional example, and do not increase as in the comparative example.
[0101]
FIG. 29 is a graph of Q2 (88) of each of the present invention, the conventional example, and the comparative example. Q2 (88) means that two capacitors Q are paired, a voltage of 3 V is applied, one of them is polarized in the plus direction, the other is polarized in the minus direction, and the power is turned off and the device is left at 150 ° C. for 88 hours. Indicates the amount of polarization remaining. This Q2 (88) is one index indicating the characteristics of the capacitor, and it is said that the larger the value, the better the retention characteristics of the capacitor.
[0102]
As shown in FIG. 29, Q2 (88) of the present invention is about 2-3 μC / cm higher than that of the conventional example. ² It can be understood that the retention characteristic is higher and the retention characteristic is improved. On the other hand, when the Ti lower layer 11a is thermally oxidized as in the comparative example, the retention characteristics are deteriorated as compared with the conventional example.
[0103]
FIG. 30 is a graph of Q3 (88) of each of the present invention, the conventional example, and the comparative example described above. Q3 (88) means that a voltage of 3 V is applied to two capacitors Q as a pair, one of them is in a positive polarization state, the other is in a negative polarization state, and the power is turned off and the apparatus is left at 150 ° C. for 88 hours. It indicates the amount of polarization when the polarity is reversed by applying a voltage of 3 V again. This Q3 (88) indicates the imprint characteristic of the capacitor, and indicates that the smaller the value is, the more the capacitor tends to have one polarity. Therefore, the larger the Q3 (88), the better the imprint characteristics of the capacitor.
[0104]
As shown in FIG. 30, in the present invention, Q3 (88) is about 4 μC / cm ² It is understood that the higher the value, the higher the imprint characteristics. It is also understood that the present invention has better imprint characteristics than the comparative example.
[0105]
FIG. 31 is a graph showing the fatigue loss of the ferroelectric film 12a of the PLZT capacitor in each of the present invention, the conventional example, and the comparative example. Fatique Loss is 2.88 × 10 at an acceleration voltage of 7V. ⁷ After writing data to the capacitor Q, the data is written at a voltage of 3 V, and then the residual polarization Q _sw Point to. Specifically, the Fatty Loss (%) is 100 × ｛(Q before acceleration) _sw )-(Q after acceleration _sw )｝ / (Q before acceleration _sw ), The smaller the value, the more difficult the capacitor is to deteriorate.
[0106]
As shown in FIG. 31, the Fatty Loss of the present invention is almost the same as the conventional example. On the other hand, in the comparative example in which the Ti lower layer 11a is thermally oxidized, it is understood that the Fatty Loss is larger than in the conventional example.
[0107]
FIG. 32 shows the amount of remanent polarization Q at 71 points in the wafer plane when the film forming temperature of the Pt upper layer 11b is varied. _sw 5 is a graph obtained by investigating the maximum value, the minimum value, the average value, and the standard deviation. This investigation was conducted on the above-mentioned conventional example in addition to the present invention.
[0108]
As shown in FIG. 32, in the present invention, regardless of the deposition temperature of the Pt upper layer 11b, the remanent polarization Q _sw Are high, and the standard deviation is small, so that the in-plane distribution is improved.
[0109]
According to the results of the above experiments, in the present invention, the remanent polarization Q is higher than that of the related art while securing the orientation strength (about 500,000 cps) of the ferroelectric film 12 necessary for the FeRAM. _sw Can be increased, and the amount of remanent polarization Q in the wafer plane can be increased. _sw Can be made smaller than before. Further, the retention characteristic, the imprint characteristic, and the fatigue loss of the capacitor can be improved as compared with the related art without deteriorating the leak current characteristic. Moreover, such advantages can be obtained irrespective of the film forming temperature of the Pt upper layer 11b.
[0110]
Next, a semiconductor manufacturing apparatus used for manufacturing the FeRAM will be considered.
[0111]
FIG. 33A is a configuration diagram of a semiconductor manufacturing apparatus according to a conventional example. In the conventional example, since the Ti lower layer 11a and the Pt upper layer 11b are formed continuously, it is necessary that the Ti chamber 102 and the Pt chamber 103 form a pair. Therefore, each of the chambers 102 and 103 has the same number. It is provided around the transfer chamber 101.
[0112]
However, since the film formation time of the Pt upper layer 11b is several times longer than that of the Ti lower layer 11a, when the Pt upper layer 11b is formed in the Pt chamber 103, the film formation in the Ti chamber 102 is not performed. The operation has already been completed, and the Ti chamber is in a standby state, so that the operation rate of the Ti chamber is reduced.
[0113]
On the other hand, in the present invention, since the Ti lower layer 11a is formed and then exposed to the atmosphere, it is not necessary to equalize the number of Ti chambers 102 and Pt chambers 103.
[0114]
Therefore, for example, as shown in FIG. 33B, by reducing the number of Pt chambers 103 to one and increasing the number of Ti chambers 102 to three, film formation is always performed in the three Ti chambers 102. As described above, when the formation of the Ti lower layer 11a is completed, the silicon substrate 1 is evacuated to a load lock or the like, so that the operation rate of the Ti chamber 102 can be increased to 1.5 times (= 3/2) the conventional rate. it can.
[0115]
Hereinafter, features of the present invention will be additionally described.
[0116]
(Supplementary Note 1) A semiconductor substrate,
An insulating film formed above the semiconductor substrate;
A lower electrode in which a lower layer and an upper layer are sequentially stacked, a capacitor dielectric film, and a capacitor formed by sequentially forming an upper electrode on the insulating film;
With
A semiconductor device, wherein a natural oxide film of the lower layer is formed on a surface of the lower layer of the lower electrode.
[0117]
(Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the lower layer is a layer made of any of Ti, Pt—Ti alloy, Ir—Ti alloy, and Ru—Ti alloy.
[0118]
(Supplementary Note 3) a step of forming an insulating film above the semiconductor substrate;
Forming a lower layer of the lower electrode conductive film on the insulating film;
Exposing the lower layer to the atmosphere;
Exposing the lower layer to the atmosphere, forming an upper layer of the lower electrode conductive film on the lower layer, and forming the upper layer and the upper layer as a lower electrode conductive film;
Forming a ferroelectric film on the upper layer;
Forming an upper electrode conductive film on the ferroelectric film;
The lower electrode conductive film, the ferroelectric film, and the upper electrode conductive film are patterned to form a lower electrode made of the lower electrode conductive film, and a capacitor dielectric film made of the ferroelectric film. Forming a capacitor having an upper electrode made of the upper electrode conductive film;
A method for manufacturing a semiconductor device, comprising:
[0119]
(Supplementary Note 4) The method for manufacturing a semiconductor device according to Supplementary Note 3, wherein the temperature of the semiconductor substrate in the step of exposing to the atmosphere is 0 ° C to 100 ° C.
[0120]
(Supplementary Note 5) The method of manufacturing a semiconductor device according to Supplementary Note 3 or 4, wherein the step of exposing to air is performed for 5 minutes to 7 days.
[0121]
(Supplementary Note 6) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 3 to 5, wherein the lower layer is formed at a temperature of 0 ° C to 300 ° C.
[0122]
(Supplementary Note 7) The lower layer according to any one of Supplementary notes 3 to 6, wherein the lower layer is a layer made of any of Ti, a Pt-Ti alloy, an Ir-Ti alloy, and a Ru-Ti alloy. Manufacturing method of a semiconductor device.
[0123]
(Supplementary Note 8) Any of the supplementary notes 3 to 7, wherein the upper layer has a single-layer or multilayer structure including any one of Pt, Ir, Ru, Pd, PtOx, IrOx, RuOx, and PdOx. 13. A method for manufacturing a semiconductor device according to
[0124]
(Supplementary Note 9) The ferroelectric film is made of (Sr, Ti) O ₃ , (Ba, Sr) TiO ₃ , Pb (Zr, Ti) O ₃ , (Pb, La) (Zr, Ti) O ₃ 9. The method for manufacturing a semiconductor device according to any one of Supplementary Notes 3 to 8, wherein the film is a film made of any one of the following compounds:
[0125]
【The invention's effect】
As described above, according to the present invention, the lower layer of the lower electrode conductive film is exposed to the air to be naturally oxidized, and then the upper layer of the lower electrode conductive film is formed on the lower layer. did.
[0126]
As a result, while maintaining the strength of the orientation of the ferroelectric film required for the FeRAM, the remanent polarization Q _sw Can be increased, and the amount of remanent polarization Q in the wafer surface can be increased. _sw Can be made smaller than before. Further, the retention characteristic, the imprint characteristic, and the fatigue loss of the capacitor can be improved as compared with the related art without deteriorating the leak current characteristic. Moreover, such advantages can be obtained irrespective of the film forming temperature of the upper layer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor manufacturing apparatus according to an embodiment of the present invention.
FIG. 2 is a sectional view (part 2) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 3 is a sectional view (part 3) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 4 is a sectional view (part 4) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 5 is a cross-sectional view (No. 5) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 6 is a sectional view (part 6) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 7 is a sectional view (part 7) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 8 is a cross-sectional view (No. 8) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 9 is a cross-sectional view (No. 9) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 10 is a sectional view (part 10) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 11 is a sectional view (No. 11) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 12 is a sectional view (part 12) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 13 is a sectional view (part 13) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 14 is a sectional view (part 14) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 15 is a sectional view (part 15) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 16 is a sectional view (16) showing the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 17 is a cross-sectional view (No. 17) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 18 is a sectional view (part 18) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 19 is a cross-sectional view (19) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 20 is a sectional view (part 20) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention;
FIG. 21 is a sectional view (part 21) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 22 is a sectional view (part 22) illustrating the method of manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 23 is a sectional view (part 23) illustrating the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 24 is a plan view showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 25 is a graph obtained by investigating the present invention and a conventional example regarding the orientation strength of the Pt upper layer and the PLZT ferroelectric film.
FIG. 26 is a diagram showing the amount of remanent polarization Q of a capacitor in each of the present invention, a conventional example, and a comparative example. _sw FIG.
FIG. 27 is a diagram illustrating the amount of remanent polarization Q of a capacitor in each of the present invention, a conventional example, and a comparative example. _sw 7 is a graph showing an average value and a standard deviation within a wafer.
28 (a) is a cumulative graph of the leakage current density of the capacitor in each of the present invention, the conventional example, and the comparative example, and FIG. 7 is a cumulative graph of the leak current density in the case where is reversed.
FIG. 29 is a graph of Q2 (88) of each of the present invention, the conventional example, and the comparative example.
FIG. 30 is a graph of Q3 (88) of each of the present invention, the conventional example, and the comparative example.
FIG. 31 is a graph showing fatigue loss of a ferroelectric film of a PLZT capacitor in each of the present invention, a conventional example, and a comparative example.
FIG. 32 shows the amount of remanent polarization Q in the wafer surface when the film forming temperature of the Pt upper layer is varied. _sw 5 is a graph obtained by investigating the maximum value, minimum value, average value, and standard deviation of the present invention and the conventional example.
FIG. 33 (a) is a configuration diagram of a semiconductor manufacturing device according to a conventional example, and FIG. 33 (b) is a configuration diagram of a semiconductor manufacturing device according to an embodiment of the present invention.
FIG. 34 is a graph showing the amount of remanent polarization Q based on the investigation result shown in FIG. 26; _sw Is a graph of the distribution in the wafer plane.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 2 ... Element isolation insulating film, 3a, 3b ... Well, 4 ... Gate insulating film, 5a-5c ... Gate electrode, 6a, 6b ... Impurity diffusion layer, 7 ... Side wall insulating film, 8a , 8b: refractory metal silicide film, 9: cover film, 10: interlayer insulating film, 11: conductive film for lower electrode, 11a: lower layer, 11b: upper layer, 11c: lower electrode, 12: ferroelectric film 12a: Dielectric film, 13: Upper electrode conductive film, 13a: Upper electrode, 14: Encap layer, 15: Interlayer insulating film, 15a to 15f: Contact hole, 16: Resist, 17: Glue film, 18 ... Tungsten layer, 18a to 18e plug, 19 antioxidant film, 20a, 20c contact pad, 20b, 20c to 20f wiring, 21 interlayer insulating film, 22 protective insulating film, 23 glue film, 24 Tungsten film, 25a to 25c plug, 26 conductive layer, 27 interlayer insulating film, 28 protective insulating film, 29 adhesion layer, 30 plug, 31a to 31f wiring, 32 protective insulating film, 33 silicon Nitride film, 34 cover film, 101 transfer chamber, 102 Ti chamber, 103 Pt chamber, A memory cell region, B peripheral circuit region, Q capacitor.

Claims (5)

A semiconductor substrate;
An insulating film formed above the semiconductor substrate;
A lower electrode formed by laminating a lower layer and an upper layer, a capacitor dielectric film, and a capacitor formed by sequentially forming an upper electrode on the insulating film;
With
A semiconductor device, wherein a natural oxide film of the lower layer is formed on a surface of the lower layer of the lower electrode. Forming an insulating film above the semiconductor substrate;
Forming a lower layer of the lower electrode conductive film on the insulating film;
Exposing the lower layer to the atmosphere;
Exposing the lower layer to the atmosphere, forming an upper layer of the lower electrode conductive film on the lower layer, and forming the upper layer and the upper layer as a lower electrode conductive film;
Forming a ferroelectric film on the upper layer;
Forming an upper electrode conductive film on the ferroelectric film;
The lower electrode conductive film, the ferroelectric film, and the upper electrode conductive film are patterned to form a lower electrode made of the lower electrode conductive film, and a capacitor dielectric film made of the ferroelectric film. Forming a capacitor having an upper electrode made of the upper electrode conductive film;
A method for manufacturing a semiconductor device, comprising: The method according to claim 2, wherein the temperature of the semiconductor substrate in the step of exposing to air is 0 ° C. to 100 ° C. 4. 4. The method according to claim 2, wherein the step of exposing to air is performed for 5 minutes to 7 days. 5. 5. The method according to claim 2, wherein the lower layer is formed at a temperature of 0 ° C. to 300 ° C. 6.

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