JP2004158676A - Method for manufacturing solid-state image sensing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a solid-state image sensing device capable of reducing white blemishes by preventing the residue of a resist film from remaining in an image sensing section in introducing impurities when forming an output section . <P>SOLUTION: In introducing the impurities when forming the output section 4, a mask layer 52 is formed in the image sensing section 2, and then a resist film 53 with a pattern for introducing the impurities to the output section 4 is formed. The impurities are introduced with the mask layer 52 and the resist film 53 serving as masks. Then, depending on circumstances, a cured layer is formed on the surface of the resist film 53 after the impurities have been introduced. When removing the resist film 53 formed in the output section 4, since the image sensing section 2 has been covered with the mask layer 52, the residue is prevented from attaching to the image sensing section 2 at this occasion. After the resist film 53 has been removed, the mask layer 52 covering the image sensing section 2 is removed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a solid-state imaging device, and more particularly, to a method of manufacturing a charge coupled device (CCD) solid-state imaging device.
[0002]
[Prior art]
A solid-state imaging device typified by a CCD includes an imaging unit having a light receiving unit for performing photoelectric conversion and a vertical transfer unit including a CCD register, and a horizontal unit including a CCD register for transferring signal charges transferred from the vertical transfer unit to an output unit. It comprises a transfer section and an output section for outputting the photoelectrically converted charges.
[0003]
The output section is constituted by a transistor. In forming the transistor, ions implanted into the source / drain regions and ions implanted for reducing the contact resistance are implanted at a high dose. For example, the dose is about 1 × 10 ¹⁵ / cm ² . At this time, a resist mask is used because of its ability to block implanted ions and its pattern size.
[0004]
When ions are implanted at a high dose of about 1 × 10 ¹⁵ / cm ² , the resist mask is changed in quality such as carbide by impact with the ions, and a hardened layer is formed on the surface.
[0005]
[Problems to be solved by the invention]
However, a resist mask having such a cured layer formed on the surface cannot be peeled off with a resist peeling solution or the like. For this reason, although the resist mask is decomposed and removed by the ashing process, a so-called popping phenomenon, in which the cured layer is popped by the heat (230 to 250 ° C.) during the ashing, occurs.
[0006]
The residue of the resist mask formed by the popping also remains on the imaging unit having a light receiving unit or the like that is easily affected by contamination or the like. As a result, a residue remains until the subsequent step, and there is a problem that white flaws are worsened by the influence of impurities contained in the residue.
[0007]
The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a residue of a resist film from remaining on an imaging unit in a step of introducing impurities when forming an output unit. An object of the present invention is to provide a method for manufacturing a solid-state imaging device capable of reducing white flaws.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing a solid-state imaging device having an output unit that detects a signal charge generated and transferred by an imaging unit and outputs the signal charge to the outside. The step of introducing an impurity when forming the output unit, the step of forming a mask layer in the imaging unit, and the step of forming a resist film having a pattern for the introduction of the impurity in the output unit, The method includes a step of introducing the impurity using the mask layer and the resist film as a mask, a step of removing the resist film, and a step of removing the mask layer.
[0009]
Before the step of forming a mask layer on the imaging unit, the method further includes the step of forming a stopper layer on the imaging unit and the output unit, the stopper layer being a stopper when removing the mask layer later, and removing the mask layer. After the step of performing, the method further includes a step of removing the stopper layer.
[0010]
In the step of forming the resist film, the resist film having a pattern for introducing the impurity is formed in a region serving as a source or a drain of a transistor included in the output unit.
[0011]
In the step of forming the mask layer, the mask layer made of an inorganic material is formed.
[0012]
In the method of manufacturing a solid-state imaging device according to the present invention, when introducing an impurity when forming an output section, a mask layer is formed on the imaging section and a resist film having a pattern for introducing the impurity into the output section. To form
Then, impurities are introduced using the mask layer and the resist film as a mask. At this time, a hardened layer may be formed on the surface of the resist film after the impurity is introduced.
When the resist film formed on the output unit is removed, the image capturing unit is covered with the mask layer, so that a residue from the removal of the resist film is prevented from attaching to the image capturing unit.
After removing the resist film, the mask layer covering the imaging unit is removed. At this time, even if a residue at the time of removing the resist film exists on the mask layer, it is removed together with the mask layer.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a method of manufacturing a solid-state imaging device according to the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a schematic configuration diagram illustrating an example of the solid-state imaging device according to the present embodiment.
The solid-state imaging device 1 according to the present embodiment includes an imaging unit 2, a horizontal transfer unit 3, and an output unit 4.
[0015]
The imaging unit 2 is configured by arranging a large number of pixels 8 each including a light receiving unit 5 that performs photoelectric conversion, a readout gate unit 6, and a vertical transfer unit 7 in a planar matrix.
Each pixel 8 is separated by a channel stopper (not shown) so as not to cause electrical interference.
[0016]
The light receiving unit 5 generates signal charges by performing photoelectric conversion in a region around the pn junction, and accumulates the signal charges for a certain period. The read gate unit 6 reads the signal charges accumulated in the light receiving unit 5 for a certain period to the vertical transfer unit 7 at a predetermined timing.
[0017]
The vertical transfer units 7 are shared for each column of the light receiving units 5 and are arranged in a predetermined number. A four-phase clock signal φV1, φV2, φV3, φV4 for driving the vertical transfer unit 7 is input to the imaging unit 2. Two-phase clock signals φH1 and φH2 for driving the horizontal transfer unit 3 are input.
[0018]
The horizontal transfer unit 3 and the vertical transfer unit 7 are formed on a substrate by insulating and separating a potential well of a minority carrier formed by introducing an impurity into a surface side of a semiconductor substrate with an insulating film therebetween. And a plurality of electrodes (transfer electrodes).
The above-mentioned clock signals φV1, φV2, φV3, φV4, φH1, φH2 are applied to the transfer electrodes 3, 7 with their phases shifted periodically.
[0019]
The transfer units 3 and 7 are controlled by a clock signal applied to the transfer electrode, and the potential distribution of the above-described potential well is sequentially changed, and the charges in the potential well are transferred in the phase shift direction of the clock signal, that is, a so-called shift. Functions as a register.
When the signal charges are transferred to the horizontal transfer unit 3 by the vertical transfer unit 7, the signal charges are transferred to the output unit 4 by the horizontal transfer unit 3.
[0020]
The output unit 4 converts the signal charge transferred by the horizontal transfer unit 3 into a voltage for each pixel, amplifies the voltage, and outputs it as a time-series imaging signal to the outside.
[0021]
FIG. 2 is a sectional view of the horizontal transfer unit and the output unit.
As shown in FIG. 2, a p-type well 11 is formed in a semiconductor substrate 10 such as an n-type silicon wafer, and an n-type transfer channel region 12 for transferring signal charges is formed in the p-type well 11. I have. A dielectric film 20 made of silicon oxide or the like is formed on the transfer channel region 12, and various electrodes are formed on the dielectric film 20.
[0022]
In the horizontal transfer section 3, first horizontal transfer electrodes 31 made of a first layer of polysilicon are repeatedly arranged at predetermined intervals in the transfer direction. On the surface of the first horizontal transfer electrode 31, an insulating film (not shown) is formed. On the insulating film in each space between the first horizontal transfer electrodes 31, a second horizontal transfer electrode 32 made of second layer polysilicon is arranged. Both ends of the second horizontal transfer electrode 32 are overlapped on the insulating film 20 at the end of the first horizontal transfer electrode 31.
Two horizontal transfer clocks φH1 and φH2 having different phases are alternately applied in units of the first and second horizontal transfer electrode pairs, and charge transfer in the horizontal transfer unit is performed.
[0023]
A relatively low concentration p-type impurity region 13 is formed in a surface portion of the transfer channel region 12 below the second horizontal transfer electrode 32. Due to the presence of the p-type impurity region 13, the transfer channel region portion that is pair-controlled in potential when the horizontal transfer clock φH1 or φH2 is applied, that is, the transfer channel region adjacent to the p-type impurity region 13 on the left side in FIG. The potential of the transfer channel region below the p-type impurity region 13 is lower than that of the portion. For this reason, the signal charges easily move in the transfer direction, and the transfer efficiency is improved.
[0024]
In the output unit 4, a relatively high concentration of n-type impurities is introduced into the horizontal transfer unit 3 side through the transfer channel region 12 in the depth direction, thereby forming a floating diffusion FD. The floating diffusion FD is integrated on the same semiconductor substrate and is connected to an input of a source follower amplifier 40 not shown in this cross-sectional view.
[0025]
The source follower amplifier 40 detects and amplifies a potential change due to the signal charge sent to the floating diffusion FD. The output of the source follower amplifier 40 is connected to an output terminal of the image signal, and a time-series image signal is sequentially output from this output terminal.
[0026]
A relatively high-concentration n-type impurity is introduced through the transfer channel region 12 in the depth direction at a position away from the floating diffusion FD, thereby forming a reset diffusion RD. Reset diffusion RD is held at a constant voltage VD.
[0027]
The dielectric film 20 extends on the transfer channel region 12 left between the reset diffusion RD and the floating diffusion FD, and the reset gate RG is formed on the dielectric film 20. The reset gate RG is made of a first or second layer of polysilicon. When the detection of the signal charge for one pixel is completed, the reset pulse φRG is applied to the reset gate RG, and the two diffusions FD and RD conduct. As a result, the signal charges in the floating diffusion FD are swept away by the reset diffusion RD.
The above-described imaging signal is generated by repeating the above-described detection and amplification of the signal charges and this reset operation for each pixel.
[0028]
As means for controlling the input of signal charges to the output unit, a horizontal output gate unit (HOG unit) is provided between the horizontal transfer unit 3 and the output unit 4. The horizontal output gate 33 of the HOG section is made of the second layer of polysilicon, and its end is overlapped with the end of the first horizontal transfer electrode 31 of the horizontal transfer section with an insulating film interposed. .
[0029]
The horizontal output clock φHOG is not applied to the horizontal output gate 33 when the output unit detects the charge amount or resets. At this time, the potential barrier in the transfer channel region 12 immediately below the horizontal output gate 33 is high, and the signal charge corresponding to the next pixel is accumulated at the end of the horizontal transfer portion.
When the reset operation is completed in the output section, the horizontal output clock φHOG is applied to the horizontal output gate 33, the height of the potential barrier in the HOG section is reduced, and the output is transferred to the floating diffusion FD.
[0030]
FIG. 3 is a circuit diagram showing an example of the configuration of the source follower amplifier.
As shown in FIG. 3, a three-stage source follower amplifier is formed in which one set of the driving transistor 41 and the constant current transistor 42 is a one-stage source follower amplifier.
[0031]
As shown in FIG. 3, MOS transistors such as a drive transistor 41 and a constant current transistor 42 are formed on the same chip as the horizontal transfer section 3 and the vertical transfer section 7 each composed of a CCD register, and drive the source follower amplifier. The transistor 41 has a structure in which the gate electrode is connected to the floating diffusion FD.
[0032]
Assuming that the amount of signal charge transferred to the floating diffusion FD is Q and the capacity of the floating diffusion FD is C, the voltage change amount ΔV of the floating diffusion FD is represented by ΔV = Q / C. This voltage change amount ΔV is obtained as an output voltage Vout via three-stage source follower amplifiers.
[0033]
FIG. 4 is a cross-sectional view of a transistor formed in an output unit of the solid-state imaging device according to the embodiment.
As shown in FIG. 4, a p-type well 11 is formed in a semiconductor substrate 10 such as an n-type silicon wafer, and a gate insulating film 43 is formed on the semiconductor substrate 10. Note that the gate insulating film 43 may be formed simultaneously with the dielectric film 20 shown in FIG.
[0034]
On the gate insulating film 43, a gate electrode 44 made of polysilicon or the like is formed. In the p-type well 11, an n-type high-concentration impurity region 45 serving as a source or a drain of the transistor is formed.
[0035]
The n-type high-concentration impurity region 45 is formed by implanting an n-type impurity at a higher dose than in the transfer channel region 12 shown in FIG. As shown in FIG. 5, a resist film 53 having a pattern having an opening in a region where the high concentration impurity region 45 is formed is formed, and is formed by ion-implanting an n-type impurity. Note that such a high-concentration impurity region 45 is not limited to a source or a drain of a transistor, and may be formed in a circuit constituting the output unit 4 in order to reduce contact resistance.
[0036]
Next, a step of forming a high-concentration impurity region in the output section will be described with reference to FIGS. In each figure, (a) is a cross-sectional view, and (b) is a plan view.
For simplification of the drawing, an example in which a high-concentration impurity region 45 as shown in the output section 4 is formed as shown in FIG. 6 will be described. Although not shown, when the high-concentration impurity region 45 is formed in the output unit 4, the transfer electrodes of the vertical transfer unit 7 and the horizontal transfer unit 3, the light receiving unit 5, and the like are already formed. In the output unit 4, the gate insulating film 43 and the gate electrode 44 shown in FIG.
[0037]
As shown in FIG. 7, an etching stopper film 51 is formed on the entire surface covering the imaging unit 2, the horizontal transfer unit 3, and the output unit 4 by, for example, forming a silicon nitride film by a CVD method. Here, the formed etching stopper film 51 has a thickness that does not affect the ion implantation, that is, a thickness that does not block the implanted ions. As will be described later, the etching stopper film 51 serves as a stopper when removing the mask layer. For example, when n-type impurity phosphorus is implanted at an implantation energy of 150 keV and a dose of 1 × 10 ¹⁵ / cm ² , the thickness of the etching stopper film 51 is about several nm.
[0038]
Next, as shown in FIG. 8, a mask layer 52 is formed on the entire surface covering the imaging unit 2, the horizontal transfer unit 3, and the output unit 4 by, for example, forming a silicon oxide film by a plasma CVD method. The thickness of the mask layer 52 is set to a thickness that can sufficiently prevent implanted ions. For example, when phosphorus as an n-type impurity is implanted at an implantation energy of 150 keV and a dose of 1 × 10 ¹⁵ / cm ² , the thickness of the mask layer 52 made of silicon oxide is about 100 nm.
[0039]
Next, as shown in FIG. 9, the mask layer 52 is etched into a pattern having an opening 52a in the output unit 4 and covering the imaging unit 2 and the horizontal transfer unit 3. This is performed by forming a resist pattern having a pattern opening to the output unit 4 by a lithography technique, and etching the mask layer 52 by RIE (Reactive Ion Etching) using the resist pattern as a mask.
[0040]
Next, as shown in FIG. 10, a resist film 53 having a pattern having an opening 53a in the high concentration impurity region formed in the output section 4 is formed. The formation of the resist film 53 is performed by a resist coating, exposure, and development process. At this time, a resist film 53 is formed only on the output section. However, the resist film 53 may be pattern-formed so as to partially overlap the mask layer 52 in order to prevent generation of a gap between the resist film 53 and the mask layer 52 due to positional rubbing.
[0041]
Next, as shown in FIG. 11, ion implantation is performed using the resist film 53 and the mask layer 52 as a mask to form a high-concentration impurity region 45 in the output unit 4. As described above, the high-concentration impurity region 45 is the source / drain region of the transistor in the output section, the contact region, or the like. For example, phosphorus as an n-type impurity is implanted at an implantation energy of 150 keV and a dose of 1 × 10 ¹⁵ / cm ² . Here, since the imaging unit 2 and the horizontal transfer unit 3 other than the output unit 4 are covered with the mask layer 52, no ions are implanted. Also, in the output section 4 as well, the area other than the area where the opening 53a is formed is covered with the resist film 53, so that no ions are implanted.
By the ion implantation in this step, a cured layer is formed on the surface of the resist film 53.
[0042]
Next, as shown in FIG. 12, the resist film 53 is removed by wet treatment with a resist stripper, ashing, or the like. When the resist film 53 is removed, even if the resist residue caused by the cured layer enters the imaging unit 2, the imaging unit 2 is covered with the mask layer 52. At this time, the residue is prevented from adhering.
[0043]
Next, as shown in FIG. 13, the mask layer 52 covering the imaging unit 2 and the horizontal transfer unit 3 other than the output unit 4 is removed. When the mask layer 52 is made of silicon oxide, the mask layer 52 is removed by wet etching using hydrofluoric acid. At this time, hydrofluoric acid can etch the mask layer 52 made of silicon oxide with a high selectivity with respect to the etching stopper film 51 made of silicon nitride. Accordingly, in the etching for removing the mask layer 52, the lower layer of the etching stopper film 51 is protected. At this time, even if a residue from the removal of the resist film exists on the mask layer, it is removed together with the mask layer 52.
[0044]
Finally, by removing the etching stopper film 51 covering the entire surface of the imaging unit 2, the horizontal transfer unit 3, and the output unit 4, a high-concentration impurity region 45 is formed in the output unit 4 as shown in FIG. . When the etching stopper film 51 is made of silicon nitride, the etching stopper film 51 is removed by wet etching using phosphoric acid.
[0045]
As described above, the ion implantation process for the high concentration impurity region 45 into the output unit 4 is completed. In the case where ions are further implanted into the output unit 4 at a high dose, the steps shown in FIGS. 7 to 13 are repeatedly performed.
[0046]
In the method of manufacturing the solid-state imaging device according to the above-described embodiment, when ion implantation is performed at a high dose into the output unit 4, two types of masks, that is, a resist film 53 made of an organic material and a mask layer 52 made of an inorganic material are used. Used.
That is, a mask layer 52 made of an inorganic material is formed in the imaging unit 2, and a resist film 53 having a pattern for ion implantation is formed in the output unit 4.
Then, high-concentration ions are implanted into a desired region of the output unit 4 using the mask layer 52 and the resist film 53 as a mask. At this time, a hardened layer is formed on the surface of the resist film 53 after the ion implantation.
When removing the resist film 53 formed on the output unit 4, since the imaging unit 2 is covered with the mask layer 52, it is possible to prevent a residue from removing the resist film 53 from attaching to the imaging unit 2. Is done.
Then, after removing the resist film 53, the mask layer 52 covering the imaging unit 2 is removed. At this time, even if a residue from the removal of the resist film 53 is present on the mask layer 52, it is removed together with the mask layer 52.
[0047]
As described above, according to the method for manufacturing the solid-state imaging device according to the present embodiment, even if it is difficult to remove the resist film 53 after ion implantation at a high dose into the output unit 4, Except for the above, the resist layer 53 is covered with the mask layer 52, so that the residue after the removal of the resist film 53 does not remain in the imaging unit 2 having the light receiving unit 5, the vertical transfer unit 7, or the horizontal transfer unit 3. Therefore, there is no influence of impurities contained in the residue of the resist, and white flaws can be reduced.
[0048]
In the present embodiment, the resist film 53 is also used in combination with the mask layer 52 made of an inorganic material alone without performing ion implantation for the following reason.
That is, since the output unit 4 other than the imaging unit 2 and the horizontal transfer unit 3 has a complicated circuit such as a MOS transistor, the pattern forming the high-concentration impurity region is very fine.
The resist film 53 processed by the lithography technique has higher processing accuracy than the mask layer 52 processed by etching such as RIE, and is therefore suitable for a fine pattern.
For the above reasons, in the present embodiment, a rough pattern that only needs to cover the imaging unit 2 and the horizontal transfer unit 3 other than the output unit 4 is formed by the mask layer 52, and the ion implantation is performed in a desired region in the output unit 4. A fine pattern for implantation is formed by the resist film 53.
[0049]
Since the output unit 4 is covered with the resist film 53, there is a possibility that a residue of the resist film 53 remains in the output unit 4. However, in a semiconductor device having a normal MOS transistor, since it is formed by repeatedly performing ion implantation at a higher dose, it is considered that there is almost no influence on the circuit of the output unit 4.
[0050]
In this embodiment, the etching stopper film 51 is formed below the mask layer 52 and the resist film 53. The etching stopper film 51 is left not only as a stopper for etching the mask layer 52 but also in the output section 4 so that the resist remaining on the etching stopper film 51 when the etching stopper film 51 is removed is removed. This also has the effect of also removing residues.
[0051]
The present invention is not limited to the description of the above embodiment.
For example, in the present invention, an example in which the mask layer 52 is formed of silicon oxide and the etching stopper film 51 is formed of silicon nitride has been described, but the present invention is not limited to this. For example, the mask layer 52 may be formed of silicon nitride or polysilicon. In this case, various materials can be applied to the etching stopper film 51 in consideration of the etching selectivity with the mask layer 52. Further, the film formation method may be formed by thermal CVD in addition to plasma CVD.
[0052]
Further, in the present embodiment, the CCD solid-state imaging device of the interline transfer (IT) system has been described as an example, but the transfer system is not limited. For example, a frame transfer (FT) system or a frame interline transfer (FIT) The system may be used.
[0053]
In the present embodiment, an example of the circuit of the output unit 4 has been described. However, any circuit configuration including a transistor may be used. Further, the output unit 4 may be formed by a floating gate amplifier instead of the floating diffusion amplifier.
In addition, various changes can be made without departing from the spirit of the present invention.
[0054]
【The invention's effect】
According to the present invention, it is possible to prevent a residue of a resist film from remaining on an imaging unit in a step of introducing impurities when forming an output unit, and to manufacture a solid-state imaging device with reduced white spots. Can be.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram illustrating an example of a solid-state imaging device according to an embodiment.
FIG. 2 is a cross-sectional view of a horizontal transfer unit and an output unit.
FIG. 3 is a circuit diagram illustrating an example of a configuration of a source follower amplifier.
FIG. 4 is a cross-sectional view of a transistor formed in an output unit of the solid-state imaging device according to the embodiment.
5 is a view showing an ion implantation step for forming source / drain regions of the transistor shown in FIG. 4;
FIG. 6 is a diagram for explaining a step of forming a high-concentration impurity region in an output unit.
FIG. 7 is a view after forming an etching stopper film in a step of forming a high-concentration impurity region in an output section.
FIG. 8 is a view after a mask layer is deposited in a step of forming a high-concentration impurity region in an output section.
FIG. 9 is a view after processing of a mask layer in a step of forming a high-concentration impurity region in an output portion.
FIG. 10 is a view after a resist film is formed in a step of forming a high-concentration impurity region in an output portion.
FIG. 11 is a view after ion implantation in a step of forming a high-concentration impurity region in an output section.
FIG. 12 is a view after removing a resist film in a step of forming a high-concentration impurity region in an output section.
FIG. 13 is a view after removing a mask layer in a step of forming a high-concentration impurity region in an output section.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Imaging part, 3 ... Horizontal transfer part, 4 ... Output part, 5 ... Light receiving part, 6 ... Readout gate part, 7 ... Vertical transfer part, 8 ... Pixel, 10 ... Semiconductor substrate, 11 ... p-type well, 12 transfer channel region, 13 p-type impurity region, 20 dielectric film, 31 first horizontal transfer electrode, 32 second horizontal transfer electrode, 33 horizontal output gate, 40 source follower amplifier 41, a driving transistor, 42, a constant current transistor, 43, a gate insulating film, 44, a gate electrode, 45, a high concentration impurity region, 51, an etching stopper film, 52, a mask layer, 52a, an opening, 53, a resist film, 53a: opening, FD: floating diffusion, RD: reset diffusion, RG: reset gate, φH1, φH2: horizontal transfer clock, φHOG: horizontal output clock φRG ... reset the clock.

Claims (4)

A method for manufacturing a solid-state imaging device having an output unit that detects a signal charge generated and transferred by an imaging unit and outputs the signal charge to an external device,
The step of introducing an impurity when forming the output unit,
Forming a mask layer on the imaging unit;
Forming a resist film having a pattern for introducing the impurity in the output unit;
Introducing the impurity using the mask layer and the resist film as a mask;
Removing the resist film;
Removing the mask layer. Before the step of forming a mask layer in the imaging unit, further comprising a step of forming a stopper layer serving as a stopper when removing the mask layer later in the imaging unit and the output unit,
2. The method according to claim 1, further comprising a step of removing the stopper layer after the step of removing the mask layer. 2. The manufacturing of the solid-state imaging device according to claim 1, wherein, in the step of forming the resist film, the resist film having a pattern for introducing the impurity is formed in a region serving as a source or a drain of a transistor constituting the output unit. Method. 2. The method according to claim 1, wherein in the step of forming the mask layer, the mask layer made of an inorganic material is formed.

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