JP2004158522A - Thin film high frequency circuit and its manufacturing method - Google Patents

Thin film high frequency circuit and its manufacturing method Download PDF

Info

Publication number
JP2004158522A
JP2004158522A JP2002320778A JP2002320778A JP2004158522A JP 2004158522 A JP2004158522 A JP 2004158522A JP 2002320778 A JP2002320778 A JP 2002320778A JP 2002320778 A JP2002320778 A JP 2002320778A JP 2004158522 A JP2004158522 A JP 2004158522A
Authority
JP
Japan
Prior art keywords
film
layer
plating seed
conductor
seed layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002320778A
Other languages
Japanese (ja)
Other versions
JP3880505B2 (en
Inventor
Kiyoshi Sato
清 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP2002320778A priority Critical patent/JP3880505B2/en
Publication of JP2004158522A publication Critical patent/JP2004158522A/en
Application granted granted Critical
Publication of JP3880505B2 publication Critical patent/JP3880505B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a thin film high frequency circuit having excellent high frequency characteristics while adhesive properties of a protective film with a conductor layer are preferably secured, and to provide a method for manufacturing the same. <P>SOLUTION: The thin film high frequency circuit 1 includes a Cu conductive layer 30 formed via a first plating seed layer 20, a second plating seed layer 40 formed on the layer 30, an Au bonding pad layer 50 formed in a specific range of the layer 40, and the protective film 60 made of an insulating resin material. In the circuit 1, the layer 20 is made of a first nonmagnetic adhesive film 21 and a Cu conductor film 22. The layer 40 is formed of a second nonmagnetic adhesive film 41 existing over the entirety on the layer 30, and an Au conductor film 42 interposed between the film 41 and the layer 50. The film 60 is formed directly on the film 41 without intermediary of the film 42 on the non-forming region of the layer 50. It is preferred to form the first and second films 21, 41 of a nonmagnetic material made of one selected from the group consisting of Cr, Ti, Mo, Ta, NiCr and NiCu. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の技術分野】
本発明は、ワイヤーボンディング方式を用いた薄膜高周波回路及びその製造方法に関する。
【０００２】
【従来技術およびその問題点】
薄膜微細加工技術を用いて形成される薄膜回路では、回路基板上に実装された回路素子と薄膜形成されたボンディングパッド層（電極）とを導通接続する際に、ワイヤーボンディング方式を用いることができる。ワイヤーボンディング方式において、ボンディングパッド層はＡｕで構成される。
【０００３】
薄膜回路中の導電層及びボンディングパッド層は従来、例えば、次のように形成されている。先ず、絶縁性基板の上にメッキシード膜を形成し、導電層の非形成領域をレジストで覆う。次に、レジストで覆われていないメッキシード膜の上に、導電層となるＣｕ導体膜と、このＣｕ導体膜の酸化防止層及びＡｕのメッキシード層となるＮｉ導体膜と、ボンディングパッド層となるＡｕ導体膜とを連続してメッキにより形成する。続いて、レジストを除去し、該除去部分から露出したメッキシード膜をエッチング等により除去し、Ａｕ導体膜のボンディングパッド層非形成領域を絶縁性樹脂からなる保護膜によって覆う。以上により、回路基板表面には保護膜とボンディングパッド層のみが露出し、Ａｕからなるボンディングパッド層が特定範囲に形成される。
【０００４】
しかしながら、上記工程ではＡｕ導体膜の上に保護膜が直接形成されており、Ａｕは単層では保護膜と密着しづらいため、高温又は高湿環境下において保護膜が剥離してしまう問題があった。さらに近年では、携帯電話や小型モバイル等に代表される通信機器の高周波化に伴い、これら通信機器に搭載される薄膜回路も高周波化が進められており、この高周波化が進むにつれて、薄膜回路の導体中に含まれる磁性材料が図１１に示すようにインダクタのＱ値を低下させてしまうことが問題になってきている。図１１の例では、導体（Ｃｕ）中に磁性材料（Ｎｉ）を含む場合のＱ値が、導体（Ｃｕ）のみの場合のＱ値に対して約１／２程度まで低下していることが分かる。
【０００５】
そこで最近では、以下に述べる第１〜第３の改善策が提案されている。
第１の改善策では、上記工程においてＣｕ導体膜とＮｉ導体膜（第１Ｎｉ導体膜）までを連続形成したらレジストを除去し、ボンディングパッド層の非形成領域を第２レジストで覆う。そして、第２レジストから露出した第１Ｎｉ導体膜の上に第２Ｎｉ導体膜とＡｕ導体膜を連続してメッキにより形成した後、第２レジストを除去して、該除去部分から露出した第１Ｎｉ導体膜の上に保護膜を形成する。この工程によれば、保護膜の密着不良は改善される。しかしながら、導体中にＮｉ導体膜が含まれているので、該Ｎｉ導体膜によりＱ値が低下してしまう。
【０００６】
第２の改善策では、上記第１の改善策と同様、Ｃｕ導体膜とＮｉ導体膜（第１Ｎｉ導体膜）までを連続形成したらレジストを除去する。次に、Ｔｉ／Ａｕからなる第２メッキシード膜を全面的に形成し、ボンディングパッド層の非形成領域を第２レジストで覆う。続いて、第２レジストで覆われていない第２メッキシード膜の上にＡｕ導体膜をメッキにより形成する。そして、第２レジストを除去し、該除去部分から露出した第１、第２メッキシード膜及びＮｉ導体膜をエッチング等により除去し、ボンディングパッド層の非形成領域を保護膜で覆う。この工程によれば、Ｎｉ導体膜の形成範囲が最小限に抑えられるので、高周波特性を改善することができる。しかしながら、第１メッキシード膜のエッチング量に対してＮｉ導体膜及び第２メッキシード膜の合計エッチング量が多く、ボンディングパッド層の周辺ではＣｕ導体膜が露出してしまう。Ｃｕは単層では保護膜と密着しづらいため、保護膜がＣｕ導体膜上に直接形成されると、保護膜の密着性を確保できない。なお、保護膜の密着性を確保すべく、Ｃｕ導体膜を露出させないように第１メッキシード膜とＮｉ導体膜及び第２メッキシード膜との膜厚を調整すると、Ｃｕ導体膜上にＮｉ導体膜が残ってしまうので、該Ｎｉ導体膜によりＱ値が低下してしまう。
【０００７】
第３の改善策では、上記第２の改善策においてＣｕ導体膜を形成した後、Ｎｉ導体膜を形成せずにレジストを除去し、Ｔｉ／Ａｕからなる第２メッキシード膜を全面的に形成する。そして、第２の改善策と同様に、保護膜を形成するまでの工程を行なう。この工程によれば、導体中にＮｉ導体膜が含まれていないので、導体中の磁性材料によってＱ値が低下することはない。しかしながら、第２メッキシード膜のエッチング量に対して第１及び第２メッキシード膜の合計エッチング量が多いため、ボンディングパッド層の周辺にはＣｕ導体膜が露出してしまい、保護膜の密着を確保することがやはり難しい。
【０００８】
以上のように第１〜第３改善策では、保護層の密着を良好に確保しようとするとＮｉ導体膜によるＱ値の低下を抑制できず、また、Ｎｉ導体膜を排除してＱ値を高くしようとすると保護層の密着を確保することができなかった。
【０００９】
【特許文献】
特開平第５−１５２７０６号公報
特開平第９−１７７９２号公報
【００１０】
【発明の目的】
本発明は、上記事情に鑑み、保護膜と導体層の密着性を良好に確保しつつ、高周波特性の優れた薄膜高周波回路及びその製造方法を得ることを目的とする。
【００１１】
【発明の概要】
本発明は、磁性材料を用いずに導体（導電層、メッキシード層及びボンディングパッド層を含む）を形成することによって高周波特性の改善を図ると共に、保護膜の直下位置に該保護膜との密着しやすい非磁性接着膜を設けることで保護層の密着性を良好に確保するものである。
【００１２】
すなわち、本発明は、絶縁性基板上に第１メッキシード層を介して形成されたＣｕ導電層；このＣｕ導電層の上に形成された第２メッキシード層；この第２メッキシード層上の特定範囲に形成されたＡｕボンディングパッド層；及び絶縁性樹脂材料からなる保護膜を有する薄膜高周波回路において、上記第１メッキシード層は、第１非磁性接着膜とＣｕ導体膜の積層体により形成され、上記第２メッキシード層は、Ｃｕ導電層上の全体に存在する第２非磁性接着膜と、この第２非磁性接着膜と上記Ａｕボンディングパッド層との間に存在するＡｕ導体膜とにより形成され、上記保護膜は、Ａｕボンディングパッド層の非形成領域に、上記Ａｕ導体膜を介在させることなく上記第２非磁性接着膜上に直接形成されていることを特徴としている。
【００１３】
上記薄膜高周波回路において、Ａｕボンディングパッド層が複数形成されている場合は、各Ａｕボンディングパッド層を電気的に独立させるため、隣接するＡｕボンディングパッド層の間に、保護膜が絶縁性基板まで達して形成されていることが好ましい。
【００１４】
第１及び第２非磁性接着膜は、Ｃｒ、Ｔｉ、Ｍｏ、Ｔａ、ＮｉＣｒ、ＮｉＣｕのいずれかからなる非磁性材料によって形成されていることが好ましい。上記非磁性材料によれば、保護膜との密着が良好であり、また、Ｃｕ又はＡｕのメッキシード層として及びＣｕ導電層の酸化防止層としての機能を発揮することができる。
【００１５】
上記第１及び第２メッキシード層において、Ｃｕ導体膜とＡｕ導体膜の膜厚はほぼ同一であり、第２非磁性接着膜の膜厚は、第１非磁性接着膜の膜厚よりも厚く、且つ、Ａｕボンディングパッド層の非形成領域のほうが該Ａｕボンディングパッド層の形成領域よりも薄くなっている。
【００１６】
また本発明の薄膜高周波回路の製造方法によれば、絶縁性基板上に、第１の非磁性接着膜とＣｕ導体膜とを積層して第１メッキシード層を形成する工程；この第１メッキシード層の特定範囲に、ＣｕからなるＣｕ導電層をメッキにより形成する工程；このＣｕ導電層上に、上記第１の非磁性接着膜よりも厚い第２の非磁性接着膜と、上記Ｃｕ導体膜と同一膜厚のＡｕ導体膜とを積層して第２メッキシード層を形成する工程；この第２メッキシード層の特定範囲に、ＡｕからなるＡｕボンディングパッド層をメッキにより形成する工程；上記Ｃｕ導電層の非形成領域の第１メッキシード層及び上記Ａｕボンディングパッド層の非形成領域の前記第２メッキシード層を露出させる工程；エッチングにより、上記露出させた第１メッキシード層をすべて除去して該除去部分に前記絶縁性基板を露出させると共に、上記露出させた第２メッキシード層のＡｕ導体膜すべてと第２の非磁性接着膜の一部を除去して該第２の非磁性接着膜を露出させる工程；及び露出させた第２の非磁性接着膜及び絶縁性基板上に、絶縁性樹脂材料からなる保護膜を形成する工程；を有することを特徴としている。
【００１７】
上記製造方法によれば、ＡｕとＣｕのエッチングレートがほぼ等しいことから、露出している第１のメッキシード層を全て除去する際に同時に、第２メッキシード層の露出部分（Ａｕボンディングパッド層の非形成領域）も除去されるが、除去されるのはＡｕ導体膜すべてと第２非磁性接着膜の一部だけである。すなわち、Ｃｕ導電層の上には第２非磁性接着膜が残り、Ｃｕ導電層が露出してしまうことがない。これにより、Ａｕ導体膜を介在させることなく第２非磁性接着膜上に保護膜が直接形成され、第２非磁性接着膜を介して保護膜の密着性を良好に確保することができ、高温又は高湿環境下であっても保護膜がはがれにくくなる。また上記製造方法によれば、導体（第１及び第２メッキシード層、Ｃｕ導電層及びＡｕボンディングパッド層）に磁性材料が含まれていないので、インダクタＱ値の高い薄膜高周波回路を得ることができる。上記製造方法によって形成された薄膜高周波回路では、第２非磁性接着膜の厚さは、Ａｕボンディングパッド層の非形成領域のほうが形成領域よりも薄くなる。
【００１８】
上記製造方法において、第１及び第２の非磁性接着膜はＣｒ、Ｔｉ、Ｍｏ、Ｔａ、ＮｉＣｒ、ＮｉＣｕのいずれかからなる非磁性材料によって形成することが好ましい。第１及び第２の非磁性接着膜を形成する非磁性材料は、第２非磁性接着膜のエッチングレートが第１非磁性接着膜のエッチングレート以下となるように選択する必要がある。
【００１９】
上記Ｃｕ導電層を形成する工程では、第１メッキシード層の上にＣｕ導電層の形成領域を画定する導体用レジストを形成し、この導体用レジストに覆われていない第１メッキシード層の上にＣｕをメッキにより形成し、これをＣｕ導電層とすることが実際的である。そして第２メッキシード層を形成する工程では、導体用レジストを残したまま、Ｃｕ導電層の上に第２非磁性接着膜とＡｕ導体膜を積層し、後に前記導体用レジストをリフトオフにより除去すればよい。
【００２０】
【発明の実施の形態】
図１は、本発明による薄膜高周波回路の一実施形態を示す平面図である。本薄膜高周波回路１は、薄膜微細加工技術を用いて形成された、微細配線や薄膜抵抗、薄膜コンデンサ、薄膜インダクタ、Ａｕボンディングパッド層（薄膜電極）等を基板上に備えている。図１に示されるように、薄膜高周波回路１の基板表面にはＡｕボンディングパッド層５０のみが露出し、Ａｕボンディングパッド層５０以外の領域は絶縁性樹脂材料からなる保護膜６０によって覆われている。
【００２１】
薄膜高周波回路１には、ワイヤーボンディングにより、各種の実装部品が導通接続される。図１に示す実施形態ではトランジスタＴｒが実装されていて、このトランジスタＴｒの端子５は、ワイヤーＷを介してＡｕボンディングパッド層５０に導通接続されている。
【００２２】
図２は、上記Ａｕボンディングパッド層５０を図１のＩＩ−ＩＩ線に沿って切断したときの断面図である。薄膜高周波回路１は、絶縁性基板１０上に第１メッキシード層２０を介して形成されたＣｕ導電層３０を有している。Ｃｕ導電層３０は、詳細は図示されていないが、各インダクタやコンデンサを接続するリード、コンデンサ及びインダクタを構成する導体膜である。第１メッキシード層２０は、Ｃｕ導電層３０をメッキにより形成するためのシード層であり、Ｃｕ導電層３０の形成領域のみに形成されている。この第１メッキシード層２０は、第１非磁性接着膜２１と、この第１非磁性接着膜２１よりも厚いＣｕ導体膜２２とによる２層構造をなしている。
【００２３】
Ｃｕ導電層３０上には、第２メッキシード層４０が形成されている。第２メッキシード層４０は、Ｃｕ導電層３０上の全体に存在する第２非磁性接着膜４１と、この第２非磁性接着膜４１と上記Ａｕボンディングパッド層５０との間に介在するＡｕ導体膜４２とにより形成されている。上記保護膜６０は、Ａｕボンディングパッド層５０の非形成領域４０Ｂに、Ａｕ導体膜４２を介在させることなく第２非磁性接着膜４１上に直接形成されている。保護膜６０は、隣接するＡｕボンディングパッド層５０の間では、絶縁性基板１０まで達して形成されている。保護膜６０の表面高さは、図示実施形態ではＡｕボンディングパッド層５０の表面高さとほぼ同等となっているが、Ａｕボンディングパッド層５０より高くても低くてもよい。
【００２４】
上記第１メッキシード層２０と第２メッキシード層４０において、Ｃｕ導体膜２２とＡｕ導体膜４２はほぼ同一膜厚を有し、第２非磁性接着膜４１が第１非磁性接着膜２１よりも厚くなっている。また、第２非磁性接着膜４１の膜厚は、Ａｕボンディングパッド層５０の形成領域４０Ａと非形成領域４０Ｂで異なり、非形成領域４０Ｂのほうが形成領域４０Ａよりも薄くなっている。
【００２５】
第１非磁性接着膜２１及び第２非磁性接着膜４２は、Ｃｒ、Ｔｉ、Ｍｏ、Ｔａ、ＮｉＣｒ、ＮｉＣｕのいずれかからなる非磁性材料によって形成されていることが好ましい。これらの非磁性材料を用いれば、第１非磁性接着膜２１及び第２非磁性接着膜４１がＣｕ導電層３０及びＡｕボンディングパッド層５０のメッキシード層として機能し、また、第２非磁性接着膜４１を介してＣｕ導電層３０と保護膜６０を密着させることができる。さらに、第２非磁性接着膜４１によってＣｕ導電層３０の酸化を防止することができる。
【００２６】
次に、図３〜図１０を参照し、図１に示す薄膜高周波回路の製造方法の一実施形態について説明する。図３〜図１０は、薄膜高周波回路の製造方法の各工程において、図１のＩＩ−ＩＩ線に沿う断面状態を示している。
【００２７】
先ず、図３に示すように、絶縁性基板１０の上に全面的に、第１非磁性接着膜２１とＣｕ導体膜２２を連続成膜し、第１メッキシード層２０を形成する。成膜にはスパッタ、蒸着、イオンビームデポジション法等の成膜を用いる。このとき本実施形態では、第１非磁性接着膜２１を例えば膜厚１５ｎｍで形成し、Ｃｕ導体膜２２を例えば膜厚６０ｎｍで形成する。絶縁性基板１０には、アルミナ基板、ＬＴＣＣ基板、ガラス基板、ガラスエポキシ基板等を用いることができる。
【００２８】
第１非磁性接着膜２１は、Ｃｒ、Ｔｉ、Ｍｏ、Ｔａ、ＮｉＣｒ、ＮｉＣｕからなる非磁性材料によって形成されていることが好ましい。
【００２９】
次に、図４に示すように、第１メッキシード層２０の上に、Ｃｕ導体層の形成領域を定める導体用レジストＲ１を形成した後、この導体用レジストＲ１に覆われていない第１メッキシード層２０の上に、ＣｕからなるＣｕ導体層３０を電解メッキにより形成する。
【００３０】
続いて、図５に示すように、導体用レジストＲ１を残したまま、Ｃｕ導体層３０の上に、第１非磁性接着膜２１よりも厚い第２非磁性接着膜４１と、Ｃｕ導体膜２１と同一膜厚のＡｕ導体膜４２とを連続成膜して、第２メッキシード層４０を形成する。成膜にはスパッタ、蒸着、イオンビームデポジション法等の成膜を用いる。本実施形態では、第２非磁性接着膜４１の膜厚を５０ｎｍ、Ａｕ導体膜４２の膜厚を６０ｎｍとしてある。
【００３１】
第２非磁性接着膜４１は、第１非磁性接着膜２１と同様、Ｃｒ、Ｔｉ、Ｍｏ、Ｔａ、ＮｉＣｒ、ＮｉＣｕのいずれかからなる非磁性材料によって形成されていることが好ましい。本実施形態では、第２非磁性接着膜４１のエッチングレートが第１非磁性接着膜２１のエッチングレート以下となるように、第１及び第２非磁性接着膜２１、４１を形成する非磁性材料を選択する。
【００３２】
第２メッキシード層４０を形成したら、図６に示すように、導体用レジストＲ１をリフトオフにより除去して、該除去部分から第１メッキシード層２０を露出させる。そして、図７に示すように、露出させた第１メッキシード層２０及び第２メッキシード層４０の上に、Ａｕボンディングパッド層５０の形成領域４０Ａを定めるパッド用レジストＲ２を形成する。メッキシード層４０において、パッド用レジストＲ２に覆われていない範囲がＡｕボンディングパッド層５０の形成領域４０Ａとなり、パッド用レジストＲ２に覆われた範囲がＡｕボンディングパッド層５０の非形成領域４０Ｂとなる。
【００３３】
続いて、図８に示すように、パッド用レジストＲ２に覆われていない第２メッキシード層４０の上に、ＡｕからなるＡｕボンディングパッド層５０を電解メッキにより形成する。Ａｕボンディングパッド層５０を形成したら、図９に示すようにパッド用レジストＲ２を除去し、該除去部分から第２メッキシード層４０（Ａｕボンディングパッド層５０の非形成領域４０Ｂ）及び第１メッキシード層２０を露出させる。
【００３４】
続いて、図１０に示すように、露出している第１メッキシード層２０をイオンミリング法、逆スパッタ法、ＲＩＥ法等のエッチングによりすべて除去して、該除去部分から絶縁性基板１０を露出させる。エッチングは、露出している第１メッキシード層２０がすべて除去された時点で終了させる。このエッチング工程では、露出している第２メッキシード層４０（４０Ｂ）も削られるが、第２メッキシード層４０のＡｕ導体膜４２と第１メッキシード層２０のＣｕ導体膜２２が同一膜厚でエッチングレートもほぼ等しく、且つ、第２非磁性接着膜４１が第１非磁性接着膜２１よりも厚く形成されているので、エッチング終了時に、Ａｕボンディングパッド層５０の非形成領域４０Ｂには第２非磁性接着膜４１が残る。
【００３５】
続いて、露出している第２非磁性接着膜４１及び絶縁性基板１０の上に、絶縁性樹脂材料からなる保護膜６０を形成する。以上により、図１及び図２に示される薄膜高周波回路１が得られる。
【００３６】
以上の本実施形態では、ＣｕとＡｕのエッチングレートがほぼ等しいことから第１メッキシード層２０のＣｕ導体膜２２と第２メッキシード層４０のＡｕ導体膜４２を同一膜厚で成膜し、さらに第２非磁性接着膜４１のエッチングレートを第１非磁性接着膜２１のエッチングレート以下とし且つ第２非磁性接着膜４１を第１非磁性接着膜２１よりも厚い膜厚で成膜してあるので、露出している第１メッキシード層２０が全て除去されたときにエッチングを終了すると、Ｃｕ導電層３０の上には第２非磁性接着膜４１のみが残る。よって、Ｃｕ導電層３０が露出することなく、また、Ａｕ導体膜４２が介在しないので、第２非磁性接着膜４１を介してＣｕ導電層３０と保護膜６０を良好に密着させることができる。
【００３７】
また本実施形態では、第１メッキシード層２０及び第２メッキシード層４０に磁性材料が含まれていないので、Ｃｕ導電層３０によって構成されるインダクタのＱ値がメッキシード層に磁性材料が含まれている場合よりも高くなり、高周波特性を改善することができる。
【００３８】
【発明の効果】
以上のように本発明によれば、第１メッキシード層が第１非磁性接着膜とＣｕ導体膜により形成され、第２メッキシード層が第２非磁性接着膜とＡｕ導体膜とに形成されているので、導体（第１及び第２メッキシード層、Ｃｕ導電層、Ａｕボンディングパッド層）にが磁性材料が含まれず、インダクタＱ値の高い高周波特性に優れた薄膜高周波回路を得ることができる。さらに本発明によれば、Ａｕ導体膜を介在させることなく且つＣｕ導電層が露出することなく、第２非磁性接着膜の上に保護膜が直接形成されているので、第２非磁性接着膜を介して保護膜と導体層を良好に密着させることが可能である。
【図面の簡単な説明】
【図１】本発明による薄膜高周波回路の一実施形態を示す平面図である。
【図２】図１のＩＩ−ＩＩ線に沿う断面図である。
【図３】図１に示す薄膜高周波回路の製造方法の一工程を示す断面図である。
【図４】図３に示す工程の次に行なわれる一工程の断面図である。
【図５】図４に示す工程の次に行なわれる一工程の断面図である。
【図６】図５に示す工程の次に行なわれる一工程の断面図である。
【図７】図６に示す工程の次に行なわれる一工程の断面図である。
【図８】図７に示す工程の次に行なわれる一工程の断面図である。
【図９】図８に示す工程の次に行なわれる一工程の断面図である。
【図１０】図９に示す工程の次に行なわれる一工程の断面図である。
【図１１】薄膜高周波回路内の導体が非磁性材料のみで形成される場合と磁性材料を含んで形成される場合のインダクタＱ値を比較して示すグラフである。
【符号の説明】
１ 薄膜高周波回路
５ トランジスタの端子
１０ 絶縁性基板
２０ 第１メッキシード層
２１ 第１非磁性接着膜
２２ Ｃｕ導体膜
３０ Ｃｕ導電層
４０ 第２メッキシード層
４０Ａ Ａｕボンディングパッド層の形成領域
４０Ｂ Ａｕボンディングパッド層の非形成領域
４１ 第２非磁性接着膜
４２ Ａｕ導体膜
５０ Ａｕボンディングパッド層
６０ 保護膜
Ｒ１ 導体用レジスト
Ｒ２ パッド用レジスト
Ｔｒ トランジスタ
Ｗ ワイヤー[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a thin film high-frequency circuit using a wire bonding method and a method for manufacturing the same.
[0002]
[Prior art and its problems]
In a thin film circuit formed using a thin film microfabrication technique, a wire bonding method can be used to electrically connect a circuit element mounted on a circuit board and a bonding pad layer (electrode) formed in a thin film. . In the wire bonding method, the bonding pad layer is made of Au.
[0003]
Conventionally, a conductive layer and a bonding pad layer in a thin film circuit are conventionally formed, for example, as follows. First, a plating seed film is formed on an insulating substrate, and a region where a conductive layer is not formed is covered with a resist. Next, on the plating seed film not covered with the resist, a Cu conductor film serving as a conductive layer, an Ni conductor film serving as an antioxidant layer of the Cu conductor film and a plating seed layer of Au, and a bonding pad layer are formed. The Au conductor film is continuously formed by plating. Subsequently, the resist is removed, the plating seed film exposed from the removed portion is removed by etching or the like, and the region where the bonding pad layer is not formed on the Au conductor film is covered with a protective film made of an insulating resin. As described above, only the protective film and the bonding pad layer are exposed on the circuit board surface, and the bonding pad layer made of Au is formed in a specific range.
[0004]
However, in the above process, the protective film is formed directly on the Au conductor film, and Au is not easily adhered to the protective film in a single layer, so that there is a problem that the protective film peels off under a high temperature or high humidity environment. Was. Further, in recent years, with the increase in the frequency of communication devices represented by mobile phones and small mobile devices, the frequency of thin film circuits mounted on these communication devices has been increasing. There is a problem that the magnetic material contained in the conductor lowers the Q value of the inductor as shown in FIG. In the example of FIG. 11, the Q value when the magnetic material (Ni) is included in the conductor (Cu) is reduced to about 約 of the Q value when only the conductor (Cu) is included. I understand.
[0005]
Therefore, recently, the following first to third improvement measures have been proposed.
In the first improvement measure, when the Cu conductor film and the Ni conductor film (first Ni conductor film) are continuously formed in the above process, the resist is removed, and the non-formation region of the bonding pad layer is covered with the second resist. Then, after the second Ni conductor film and the Au conductor film are continuously formed on the first Ni conductor film exposed from the second resist by plating, the second resist is removed, and the first Ni conductor exposed from the removed portion is removed. A protective film is formed on the film. According to this step, poor adhesion of the protective film is improved. However, since the Ni conductor film is included in the conductor, the Q value is reduced by the Ni conductor film.
[0006]
In the second improvement, similarly to the first improvement, the resist is removed after the Cu conductor film and the Ni conductor film (first Ni conductor film) are continuously formed. Next, a second plating seed film made of Ti / Au is formed on the entire surface, and a region where the bonding pad layer is not formed is covered with a second resist. Subsequently, an Au conductor film is formed by plating on the second plating seed film that is not covered with the second resist. Then, the second resist is removed, the first and second plating seed films and the Ni conductor film exposed from the removed portions are removed by etching or the like, and the non-formed region of the bonding pad layer is covered with a protective film. According to this step, the formation range of the Ni conductor film can be minimized, so that high-frequency characteristics can be improved. However, the total etching amount of the Ni conductor film and the second plating seed film is larger than the etching amount of the first plating seed film, and the Cu conductor film is exposed around the bonding pad layer. Since Cu is difficult to adhere to the protective film in a single layer, if the protective film is formed directly on the Cu conductor film, the adhesion of the protective film cannot be ensured. When the thicknesses of the first plating seed film, the Ni conductor film, and the second plating seed film are adjusted so as not to expose the Cu conductor film in order to secure the adhesion of the protective film, the Ni conductor is formed on the Cu conductor film. Since the film remains, the Q value is reduced by the Ni conductor film.
[0007]
In the third improvement, after the Cu conductor film is formed in the second improvement, the resist is removed without forming the Ni conductor film, and the second plating seed film made of Ti / Au is formed entirely. I do. Then, similarly to the second improvement measure, the steps up to the formation of the protective film are performed. According to this step, since the conductor does not include the Ni conductor film, the Q value does not decrease due to the magnetic material in the conductor. However, since the total etching amount of the first and second plating seed films is larger than the etching amount of the second plating seed film, the Cu conductor film is exposed around the bonding pad layer, and the adhesion of the protective film is reduced. It is still difficult to secure.
[0008]
As described above, in the first to third improvement measures, it is not possible to suppress a decrease in the Q value due to the Ni conductor film when trying to ensure good adhesion of the protective layer, and to increase the Q value by eliminating the Ni conductor film. Attempts could not ensure the adhesion of the protective layer.
[0009]
[Patent Document]
JP-A-5-152706 JP-A-9-17792
[Object of the invention]
In view of the above circumstances, an object of the present invention is to obtain a thin-film high-frequency circuit having excellent high-frequency characteristics while ensuring good adhesion between a protective film and a conductor layer, and a method for manufacturing the same.
[0011]
Summary of the Invention
The present invention aims to improve high-frequency characteristics by forming a conductor (including a conductive layer, a plating seed layer, and a bonding pad layer) without using a magnetic material, and to adhere to the protective film immediately below the protective film. By providing a non-magnetic adhesive film which is easy to perform, good adhesion of the protective layer is ensured.
[0012]
That is, the present invention provides a Cu conductive layer formed on an insulating substrate via a first plating seed layer; a second plating seed layer formed on the Cu conductive layer; In a thin film high-frequency circuit having an Au bonding pad layer formed in a specific range; and a protective film made of an insulating resin material, the first plating seed layer is formed by a laminate of a first non-magnetic adhesive film and a Cu conductor film. The second plating seed layer includes a second non-magnetic adhesive film existing entirely on the Cu conductive layer, and an Au conductor film existing between the second non-magnetic adhesive film and the Au bonding pad layer. Wherein the protective film is formed directly on the second non-magnetic adhesive film in a region where the Au bonding pad layer is not formed, without the Au conductor film interposed therebetween.
[0013]
In the thin-film high-frequency circuit described above, when a plurality of Au bonding pad layers are formed, the protective film extends to the insulating substrate between the adjacent Au bonding pad layers in order to make each Au bonding pad layer electrically independent. It is preferable that it is formed.
[0014]
The first and second non-magnetic adhesive films are preferably formed of a non-magnetic material made of any of Cr, Ti, Mo, Ta, NiCr, and NiCu. According to the non-magnetic material, adhesion to the protective film is good, and the non-magnetic material can function as a plating seed layer of Cu or Au and as an antioxidant layer of the Cu conductive layer.
[0015]
In the first and second plating seed layers, the thickness of the Cu conductor film and the thickness of the Au conductor film are substantially the same, and the thickness of the second nonmagnetic adhesive film is larger than the thickness of the first nonmagnetic adhesive film. The region where the Au bonding pad layer is not formed is thinner than the region where the Au bonding pad layer is formed.
[0016]
According to the method of manufacturing a thin film high-frequency circuit of the present invention, a step of forming a first plating seed layer by laminating a first nonmagnetic adhesive film and a Cu conductor film on an insulating substrate; Forming a Cu conductive layer made of Cu in a specific range of the seed layer by plating; a second non-magnetic adhesive film thicker than the first non-magnetic adhesive film on the Cu conductive layer; Forming a second plating seed layer by laminating the film and an Au conductor film having the same thickness; forming an Au bonding pad layer made of Au in a specific area of the second plating seed layer by plating; Exposing the first plating seed layer in the region where the Cu conductive layer is not formed and the second plating seed layer in the region where the Au bonding pad layer is not formed; removing the exposed first plating seed layer by etching; To remove the insulative substrate in the removed portion, and to remove all of the exposed Au conductor film of the second plating seed layer and a part of the second non-magnetic adhesive film to remove the second plating seed layer. Exposing the non-magnetic adhesive film; and forming a protective film made of an insulating resin material on the exposed second non-magnetic adhesive film and the insulating substrate.
[0017]
According to the above-described manufacturing method, since the etching rates of Au and Cu are substantially equal to each other, when all of the exposed first plating seed layer is removed, the exposed portion of the second plating seed layer (the Au bonding pad layer) is simultaneously removed. Is removed, but only the entire Au conductor film and a part of the second nonmagnetic adhesive film are removed. That is, the second nonmagnetic adhesive film remains on the Cu conductive layer, and the Cu conductive layer is not exposed. Thus, the protective film is directly formed on the second non-magnetic adhesive film without the Au conductor film interposed therebetween, and good adhesion of the protective film can be secured via the second non-magnetic adhesive film. Alternatively, the protective film does not easily peel off even in a high humidity environment. Further, according to the above-described manufacturing method, since the conductor (the first and second plating seed layers, the Cu conductive layer, and the Au bonding pad layer) does not include a magnetic material, a thin film high-frequency circuit having a high inductor Q value can be obtained. it can. In the thin film high-frequency circuit formed by the above manufacturing method, the thickness of the second nonmagnetic adhesive film is smaller in the non-formation region of the Au bonding pad layer than in the formation region.
[0018]
In the above manufacturing method, the first and second nonmagnetic adhesive films are preferably formed of a nonmagnetic material made of any of Cr, Ti, Mo, Ta, NiCr, and NiCu. The non-magnetic material forming the first and second non-magnetic adhesive films must be selected so that the etching rate of the second non-magnetic adhesive film is lower than the etching rate of the first non-magnetic adhesive film.
[0019]
In the step of forming the Cu conductive layer, a conductor resist that defines a region where the Cu conductive layer is to be formed is formed on the first plating seed layer, and a resist is formed on the first plating seed layer that is not covered with the conductor resist. It is practical to form Cu by plating and use this as a Cu conductive layer. In the step of forming the second plating seed layer, the second nonmagnetic adhesive film and the Au conductor film are laminated on the Cu conductive layer while leaving the conductor resist, and the conductor resist is removed by lift-off later. Just fine.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a plan view showing an embodiment of the thin-film high-frequency circuit according to the present invention. The thin-film high-frequency circuit 1 includes a fine wiring, a thin-film resistor, a thin-film capacitor, a thin-film inductor, an Au bonding pad layer (thin-film electrode), and the like formed on a substrate by using a thin-film fine processing technique. As shown in FIG. 1, only the Au bonding pad layer 50 is exposed on the substrate surface of the thin-film high-frequency circuit 1, and a region other than the Au bonding pad layer 50 is covered with a protective film 60 made of an insulating resin material. .
[0021]
Various mounting components are conductively connected to the thin-film high-frequency circuit 1 by wire bonding. In the embodiment shown in FIG. 1, a transistor Tr is mounted, and a terminal 5 of the transistor Tr is conductively connected to an Au bonding pad layer 50 via a wire W.
[0022]
FIG. 2 is a sectional view when the Au bonding pad layer 50 is cut along the line II-II in FIG. The thin-film high-frequency circuit 1 has a Cu conductive layer 30 formed on an insulating substrate 10 with a first plating seed layer 20 interposed therebetween. Although not shown in detail, the Cu conductive layer 30 is a lead for connecting each inductor or capacitor, a capacitor, and a conductor film forming the inductor. The first plating seed layer 20 is a seed layer for forming the Cu conductive layer 30 by plating, and is formed only in the region where the Cu conductive layer 30 is formed. The first plating seed layer 20 has a two-layer structure including a first non-magnetic adhesive film 21 and a Cu conductor film 22 thicker than the first non-magnetic adhesive film 21.
[0023]
On the Cu conductive layer 30, a second plating seed layer 40 is formed. The second plating seed layer 40 includes a second nonmagnetic adhesive film 41 existing entirely on the Cu conductive layer 30 and an Au conductor interposed between the second nonmagnetic adhesive film 41 and the Au bonding pad layer 50. The film 42 is formed. The protective film 60 is formed directly on the second non-magnetic adhesive film 41 in the non-formation region 40B of the Au bonding pad layer 50 without the Au conductor film 42 interposed therebetween. The protective film 60 is formed to reach the insulating substrate 10 between the adjacent Au bonding pad layers 50. In the illustrated embodiment, the surface height of the protective film 60 is substantially equal to the surface height of the Au bonding pad layer 50, but may be higher or lower than the Au bonding pad layer 50.
[0024]
In the first plating seed layer 20 and the second plating seed layer 40, the Cu conductor film 22 and the Au conductor film 42 have substantially the same film thickness, and the second non-magnetic adhesive film 41 is smaller than the first non-magnetic adhesive film 21. Is also thicker. The thickness of the second nonmagnetic adhesive film 41 differs between the formation region 40A of the Au bonding pad layer 50 and the non-formation region 40B, and the non-formation region 40B is thinner than the formation region 40A.
[0025]
The first nonmagnetic adhesive film 21 and the second nonmagnetic adhesive film 42 are preferably formed of a nonmagnetic material made of any of Cr, Ti, Mo, Ta, NiCr, and NiCu. If these nonmagnetic materials are used, the first nonmagnetic adhesive film 21 and the second nonmagnetic adhesive film 41 function as plating seed layers for the Cu conductive layer 30 and the Au bonding pad layer 50, and the second nonmagnetic adhesive film The Cu conductive layer 30 and the protective film 60 can be adhered through the film 41. Further, the oxidation of the Cu conductive layer 30 can be prevented by the second nonmagnetic adhesive film 41.
[0026]
Next, an embodiment of a method for manufacturing the thin-film high-frequency circuit shown in FIG. 1 will be described with reference to FIGS. 3 to 10 show cross-sectional states along the line II-II in FIG. 1 in each step of the method of manufacturing the thin-film high-frequency circuit.
[0027]
First, as shown in FIG. 3, a first nonmagnetic adhesive film 21 and a Cu conductor film 22 are continuously formed on the entire surface of an insulating substrate 10 to form a first plating seed layer 20. Film formation such as sputtering, vapor deposition, or ion beam deposition is used for film formation. At this time, in the present embodiment, the first nonmagnetic adhesive film 21 is formed with a thickness of, for example, 15 nm, and the Cu conductor film 22 is formed with a thickness of, for example, 60 nm. As the insulating substrate 10, an alumina substrate, an LTCC substrate, a glass substrate, a glass epoxy substrate, or the like can be used.
[0028]
The first non-magnetic adhesive film 21 is preferably formed of a non-magnetic material made of Cr, Ti, Mo, Ta, NiCr, NiCu.
[0029]
Next, as shown in FIG. 4, a conductor resist R1 that defines a region where the Cu conductor layer is to be formed is formed on the first plating seed layer 20, and then the first plating that is not covered with the conductor resist R1 is formed. A Cu conductor layer 30 made of Cu is formed on the seed layer 20 by electrolytic plating.
[0030]
Subsequently, as shown in FIG. 5, the second non-magnetic adhesive film 41 thicker than the first non-magnetic adhesive film 21 and the Cu conductor film 21 are formed on the Cu conductor layer 30 while leaving the conductor resist R1. A second plating seed layer 40 is formed by continuously forming an Au conductor film 42 having the same thickness as that of the second plating seed layer 40. Film formation such as sputtering, vapor deposition, or ion beam deposition is used for film formation. In the present embodiment, the thickness of the second nonmagnetic adhesive film 41 is 50 nm, and the thickness of the Au conductor film 42 is 60 nm.
[0031]
Like the first non-magnetic adhesive film 21, the second non-magnetic adhesive film 41 is preferably formed of a non-magnetic material made of any of Cr, Ti, Mo, Ta, NiCr, and NiCu. In the present embodiment, the non-magnetic material for forming the first and second non-magnetic adhesive films 21 and 41 is such that the etching rate of the second non-magnetic adhesive film 41 is equal to or less than the etching rate of the first non-magnetic adhesive film 21. Select
[0032]
After forming the second plating seed layer 40, as shown in FIG. 6, the conductor resist R1 is removed by lift-off, and the first plating seed layer 20 is exposed from the removed portion. Then, as shown in FIG. 7, a pad resist R2 for defining the formation region 40A of the Au bonding pad layer 50 is formed on the exposed first plating seed layer 20 and second plating seed layer 40. In the plating seed layer 40, the area not covered by the pad resist R2 is the formation area 40A of the Au bonding pad layer 50, and the area covered by the pad resist R2 is the non-formation area 40B of the Au bonding pad layer 50. .
[0033]
Subsequently, as shown in FIG. 8, an Au bonding pad layer 50 made of Au is formed by electrolytic plating on the second plating seed layer 40 not covered with the pad resist R2. After forming the Au bonding pad layer 50, the pad resist R2 is removed as shown in FIG. 9, and the second plating seed layer 40 (the non-formation region 40B of the Au bonding pad layer 50) and the first plating seed are removed from the removed portion. The layer 20 is exposed.
[0034]
Subsequently, as shown in FIG. 10, the exposed first plating seed layer 20 is entirely removed by etching such as ion milling, reverse sputtering, or RIE, and the insulating substrate 10 is exposed from the removed portion. Let it. The etching is terminated when all the exposed first plating seed layers 20 are removed. In this etching step, the exposed second plating seed layer 40 (40B) is also shaved, but the Au conductor film 42 of the second plating seed layer 40 and the Cu conductor film 22 of the first plating seed layer 20 have the same thickness. And the second non-magnetic adhesive film 41 is formed thicker than the first non-magnetic adhesive film 21, so that the non-forming region 40B of the Au bonding pad layer 50 is 2 The non-magnetic adhesive film 41 remains.
[0035]
Subsequently, a protective film 60 made of an insulating resin material is formed on the exposed second non-magnetic adhesive film 41 and the insulating substrate 10. As described above, the thin-film high-frequency circuit 1 shown in FIGS. 1 and 2 is obtained.
[0036]
In the present embodiment described above, since the etching rates of Cu and Au are substantially equal, the Cu conductor film 22 of the first plating seed layer 20 and the Au conductor film 42 of the second plating seed layer 40 are formed to have the same thickness. Further, the etching rate of the second non-magnetic adhesive film 41 is set to be equal to or less than the etching rate of the first non-magnetic adhesive film 21, and the second non-magnetic adhesive film 41 is formed to be thicker than the first non-magnetic adhesive film 21. Therefore, when the etching is completed when all the exposed first plating seed layers 20 are removed, only the second nonmagnetic adhesive film 41 remains on the Cu conductive layer 30. Therefore, since the Cu conductive layer 30 is not exposed and the Au conductive film 42 is not interposed, the Cu conductive layer 30 and the protective film 60 can be satisfactorily adhered via the second non-magnetic adhesive film 41.
[0037]
Further, in the present embodiment, since the first plating seed layer 20 and the second plating seed layer 40 do not contain a magnetic material, the Q value of the inductor formed by the Cu conductive layer 30 indicates that the plating seed layer contains a magnetic material. Higher than in the case where it is used, and the high frequency characteristics can be improved.
[0038]
【The invention's effect】
As described above, according to the present invention, the first plating seed layer is formed by the first non-magnetic adhesive film and the Cu conductor film, and the second plating seed layer is formed by the second non-magnetic adhesion film and the Au conductor film. Since the conductors (the first and second plating seed layers, the Cu conductive layer, and the Au bonding pad layer) do not contain a magnetic material, a thin film high frequency circuit having a high inductor Q value and excellent high frequency characteristics can be obtained. . Further, according to the present invention, since the protective film is directly formed on the second non-magnetic adhesive film without interposing the Au conductive film and exposing the Cu conductive layer, the second non-magnetic adhesive film is formed. Thus, the protective film and the conductor layer can be satisfactorily brought into close contact with each other.
[Brief description of the drawings]
FIG. 1 is a plan view showing an embodiment of a thin-film high-frequency circuit according to the present invention.
FIG. 2 is a sectional view taken along the line II-II in FIG.
FIG. 3 is a sectional view showing one step of a method for manufacturing the thin-film high-frequency circuit shown in FIG.
FIG. 4 is a sectional view of a step performed after the step shown in FIG. 3;
FIG. 5 is a sectional view of a step performed after the step shown in FIG. 4;
FIG. 6 is a sectional view of a step performed after the step shown in FIG. 5;
FIG. 7 is a sectional view of a step performed after the step shown in FIG. 6;
FIG. 8 is a cross-sectional view of a step performed after the step shown in FIG. 7;
FIG. 9 is a cross-sectional view of a step performed after the step shown in FIG. 8;
FIG. 10 is a sectional view of a step performed after the step shown in FIG. 9;
FIG. 11 is a graph showing a comparison between inductor Q values when a conductor in a thin film high-frequency circuit is formed only of a non-magnetic material and when a conductor is formed including a magnetic material.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 thin-film high-frequency circuit 5 terminal of transistor 10 insulating substrate 20 first plating seed layer 21 first nonmagnetic adhesive film 22 Cu conductor film 30 Cu conductive layer 40 second plating seed layer 40A Au bonding pad layer formation region 40B Au bonding Pad layer non-forming region 41 Second nonmagnetic adhesive film 42 Au conductor film 50 Au bonding pad layer 60 Protective film R1 Conductor resist R2 Pad resist Tr Transistor W Wire

Claims (8)

絶縁性基板上に第１メッキシード層を介して形成されたＣｕ導電層；このＣｕ導電層の上に形成された第２メッキシード層；この第２メッキシード層上の特定範囲に形成されたＡｕボンディングパッド層；及び絶縁性樹脂材料からなる保護膜を有する薄膜高周波回路において、
前記第１メッキシード層は、第１非磁性接着膜とＣｕ導体膜の積層体により形成され、
前記第２メッキシード層は、前記Ｃｕ導電層上の全体に存在する第２非磁性接着膜と、この第２非磁性接着膜と前記Ａｕボンディングパッド層との間に介在するＡｕ導体膜とにより形成され、
前記保護膜は、前記Ａｕボンディングパッド層の非形成領域に、前記Ａｕ導体膜を介在させることなく前記第２非磁性接着膜上に直接形成されていることを特徴とする薄膜高周波回路。A Cu conductive layer formed on the insulating substrate via the first plating seed layer; a second plating seed layer formed on the Cu conductive layer; formed in a specific area on the second plating seed layer In a thin film high-frequency circuit having an Au bonding pad layer; and a protective film made of an insulating resin material,
The first plating seed layer is formed by a laminate of a first non-magnetic adhesive film and a Cu conductor film,
The second plating seed layer is formed by a second non-magnetic adhesive film existing entirely on the Cu conductive layer and an Au conductive film interposed between the second non-magnetic adhesive film and the Au bonding pad layer. Formed,
The thin-film high-frequency circuit according to claim 1, wherein the protective film is formed directly on the second non-magnetic adhesive film in a region where the Au bonding pad layer is not formed, without interposing the Au conductor film. 請求項１記載の薄膜高周波回路において、前記Ａｕボンディングパッド層は複数形成されていて、隣接するＡｕボンディングパッド層の間には、前記保護膜が前記絶縁性基板まで達して形成されている薄膜高周波回路。2. The thin-film high-frequency circuit according to claim 1, wherein a plurality of said Au bonding pad layers are formed, and said protective film is formed between adjacent Au bonding pad layers to reach said insulating substrate. circuit. 請求項１または２記載の薄膜高周波回路において、前記第１及び第２非磁性接着膜がＣｒ、Ｔｉ、Ｍｏ、Ｔａ、ＮｉＣｒ、ＮｉＣｕのいずれかからなる非磁性材料によって形成されている薄膜高周波回路。3. The thin-film high-frequency circuit according to claim 1, wherein said first and second non-magnetic adhesive films are formed of a non-magnetic material made of any of Cr, Ti, Mo, Ta, NiCr, and NiCu. . 請求項１ないし３のいずれか一項に記載の薄膜高周波回路において、前記Ｃｕ導体膜と前記Ａｕ導体膜の膜厚はほぼ同一であり、前記第２非磁性接着膜の膜厚は、前記第１非磁性接着膜の膜厚よりも厚く、且つ、前記Ａｕボンディングパッド層の非形成領域のほうが該Ａｕボンディングパッド層の形成領域よりも薄くなっている薄膜高周波回路。4. The thin film high-frequency circuit according to claim 1, wherein the thickness of the Cu conductor film and the thickness of the Au conductor film are substantially the same, and the thickness of the second nonmagnetic adhesive film is the thickness of the second nonmagnetic adhesive film. 5. (1) A thin-film high-frequency circuit in which the thickness of the non-magnetic adhesive film is larger than the thickness of the Au bonding pad layer and the thickness of the non-forming region of the Au bonding pad layer is smaller than that of the Au bonding pad layer. 絶縁性基板上に、第１の非磁性接着膜とＣｕ導体膜とを積層して第１メッキシード層を形成する工程；
この第１メッキシード層の特定範囲に、ＣｕからなるＣｕ導電層をメッキにより形成する工程；
このＣｕ導電層上に、前記第１の非磁性接着膜よりも厚い第２の非磁性接着膜と、前記Ｃｕ導体膜と同一膜厚のＡｕ導体膜とを積層して第２メッキシード層を形成する工程；
この第２メッキシード層の特定範囲に、ＡｕからなるＡｕボンディングパッド層をメッキにより形成する工程；
前記Ｃｕ導電層の非形成領域の第１メッキシード層及び前記Ａｕボンディングパッド層の非形成領域の前記第２メッキシード層を露出させる工程；
エッチングにより、前記露出させた第１メッキシード層をすべて除去して該除去部分に前記絶縁性基板を露出させると共に、前記露出させた第２メッキシード層のＡｕ導体膜すべてと第２の非磁性接着膜の一部を除去して該第２の非磁性接着膜を露出させる工程；及び
露出させた第２の非磁性接着膜及び絶縁性基板上に、絶縁性樹脂材料からなる保護膜を形成する工程；
を有することを特徴とする薄膜高周波回路の製造方法。Forming a first plating seed layer by laminating a first nonmagnetic adhesive film and a Cu conductor film on an insulating substrate;
Forming a Cu conductive layer made of Cu in a specific range of the first plating seed layer by plating;
On this Cu conductive layer, a second non-magnetic adhesive film thicker than the first non-magnetic adhesive film and an Au conductive film having the same thickness as the Cu conductive film are laminated to form a second plating seed layer. Forming step;
Forming an Au bonding pad layer made of Au in a specific area of the second plating seed layer by plating;
Exposing the first plating seed layer in a region where the Cu conductive layer is not formed and the second plating seed layer in a region where the Au bonding pad layer is not formed;
By etching, the exposed first plating seed layer is entirely removed to expose the insulating substrate at the removed portion, and the exposed Au conductor film of the second plating seed layer and the second nonmagnetic layer are all removed. Removing a part of the adhesive film to expose the second non-magnetic adhesive film; and forming a protective film made of an insulating resin material on the exposed second non-magnetic adhesive film and the insulating substrate. Performing the step;
A method for manufacturing a thin-film high-frequency circuit, comprising: 請求項５記載の薄膜高周波回路の製造方法において、Ｃｒ、Ｔｉ、Ｍｏ、Ｔａ、ＮｉＣｒ、ＮｉＣｕのいずれかからなる非磁性材料によって、前記第１及び第２の非磁性接着膜を形成する薄膜高周波回路の製造方法。6. The method according to claim 5, wherein the first and second non-magnetic adhesive films are formed of a non-magnetic material made of any of Cr, Ti, Mo, Ta, NiCr, and NiCu. Circuit manufacturing method. 請求項６記載の薄膜高周波回路の製造方法において、前記第２非磁性接着膜を、そのエッチングレートが前記第１非磁性接着膜のエッチングレート以下となる非磁性材料で形成する薄膜高周波回路の製造方法。7. The method according to claim 6, wherein the second non-magnetic adhesive film is formed of a non-magnetic material whose etching rate is equal to or lower than the etching rate of the first non-magnetic adhesive film. Method. 請求項５ないし７のいずれか一項に記載の薄膜高周波回路の製造方法において、前記Ｃｕ導電層を形成する工程では、前記第１メッキシード層の上に前記Ｃｕ導電層の形成領域を画定する導体用レジストを形成し、この導体用レジストに覆われていない前記第１メッキシード層の上に前記Ｃｕ導電層をメッキにより形成し、
前記第２メッキシード層を形成する工程では、前記導体用レジストを残したまま、前記Ｃｕ導電層の上に前記第２非磁性接着膜と前記Ａｕ導体膜を積層し、後に前記導体用レジストをリフトオフにより除去する薄膜高周波回路の製造方法。8. The method of manufacturing a thin-film high-frequency circuit according to claim 5, wherein, in the step of forming the Cu conductive layer, a region where the Cu conductive layer is formed is defined on the first plating seed layer. 9. Forming a conductor resist, forming the Cu conductive layer by plating on the first plating seed layer not covered with the conductor resist,
In the step of forming the second plating seed layer, the second nonmagnetic adhesive film and the Au conductor film are laminated on the Cu conductive layer while leaving the conductor resist, and the conductor resist is later A method for manufacturing a thin film high-frequency circuit that is removed by lift-off.
JP2002320778A 2002-11-05 2002-11-05 Thin film high frequency circuit and manufacturing method thereof Expired - Fee Related JP3880505B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002320778A JP3880505B2 (en) 2002-11-05 2002-11-05 Thin film high frequency circuit and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002320778A JP3880505B2 (en) 2002-11-05 2002-11-05 Thin film high frequency circuit and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2004158522A true JP2004158522A (en) 2004-06-03
JP3880505B2 JP3880505B2 (en) 2007-02-14

Family

ID=32801523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002320778A Expired - Fee Related JP3880505B2 (en) 2002-11-05 2002-11-05 Thin film high frequency circuit and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3880505B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8574729B2 (en) * 2008-04-23 2013-11-05 Tdk Corporation Magnetic structure including two ferromagnetically coupled magnetic layers and method of manufacturing same
CN104754867A (en) * 2013-12-30 2015-07-01 深南电路有限公司 Thick copper circuit board and processing method thereof and interlayer interconnection structure achievement method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8574729B2 (en) * 2008-04-23 2013-11-05 Tdk Corporation Magnetic structure including two ferromagnetically coupled magnetic layers and method of manufacturing same
CN104754867A (en) * 2013-12-30 2015-07-01 深南电路有限公司 Thick copper circuit board and processing method thereof and interlayer interconnection structure achievement method
CN104754867B (en) * 2013-12-30 2017-12-29 深南电路有限公司 The implementation method of heavy copper circuit board and its processing method and interlayer interconnection structure

Also Published As

Publication number Publication date
JP3880505B2 (en) 2007-02-14

Similar Documents

Publication Publication Date Title
CN107039144B (en) Inductor component
US5450263A (en) Thin film inductors, inductor network and integration with other passive and active devices
US7453343B2 (en) Thin-film type common-mode choke coil
JP5873323B2 (en) Method for fabricating a semiconductor device package
US8058951B2 (en) Sheet-like composite electronic component and method for manufacturing same
US10312002B2 (en) Chip component and production method therefor
WO2005010899A1 (en) Coil part and manufacturing method thereof
JPH11126976A (en) Laminated structure body of printed circuit board
JP4916715B2 (en) Electronic components
US20030034173A1 (en) Bump-attached wiring circuit board and method for manufacturing same
US7368324B2 (en) Method of manufacturing self-supporting contacting structures
JP2982193B2 (en) Manufacturing method of high frequency coil
EP1983532B1 (en) Capacitor and manufacturing method thereof
KR20050071330A (en) Over-current protective device and manufacturing method thereof
JP3880505B2 (en) Thin film high frequency circuit and manufacturing method thereof
JP2006287063A (en) Electronic part
JP2005044952A (en) Common mode choke coil and manufacturing method thereof, and common mode choke coil array
US7342804B2 (en) Ball grid array resistor capacitor network
JP2003124591A (en) Electronic circuit board and its manufacturing method as well as copper-plating liquid for suppressing migration
JPH10199886A (en) Semiconductor device and manufacture thereof
JPH09270355A (en) Electronic part and manufacture thereof
JPH09270329A (en) Electronic part and manufacturing method thereof
JP2022153684A (en) Coil component and manufacturing method thereof
JP2001006936A (en) Electronic component
JP2004266205A (en) Multilayer substrate with built-in resistor, electronic component utilizing substrate, and manufacturing method of multilayer substrate with built-in resistor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050509

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061026

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061031

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061107

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees