JP2004158518A - Active matrix substrate and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix substrate which effectively shades the light rays incident on a semiconductor layer, is restrained from decreasing a numerical aperture, and used for an active matrix display device. <P>SOLUTION: The semiconductor device region of the active matrix substrate is equipped with a first insulating layer 3a formed on a substrate 1a, a semiconductor layer 4a formed on the first insulating layer 3a, a first electrode layer 5a formed on the semiconductor layer 4a through the intermediary of an insulating film 5b, a second insulating layer 6a covering the first electrode layer 5a and the semiconductor layer 4a, a first shading layer 8a covering, at least, a part of the semiconductor layer 4a and formed on the first insulating layer 3a and the second insulating layer 6a, a third insulating layer 9a formed on the first shading layer 8a, and a second electrode layer 11a formed on the third insulating layer 9a. An insulating laminated film containing the first insulating layer 3a and the second insulating layer 6a is formed on the peripheral part of the semiconductor layer 4a, the insulating laminated film is equipped with grooves 7a adjacent to the peripheral edges of the semiconductor layer 4a, the bottom of the groove 7a is located lower than the second insulating layer 6a, and the first shading layer 8a is extended from above the semiconductor layer 4a to the bottoms of the grooves 7a. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device and an active matrix substrate used for the display device, and more particularly to a structure for shielding a semiconductor layer of a semiconductor element of the active matrix substrate from light.
[0002]
[Prior art]
In recent years, liquid crystal display devices have been widely used because of their advantages such as light weight, thinness, and low power consumption. In particular, an active matrix type liquid crystal display device is provided with a switching element for each pixel, so that high definition and high quality display can be performed.
[0003]
Note that in this specification, among the substrates constituting the active matrix liquid crystal display device, the substrate on which the switching element is formed is referred to as an “active matrix substrate”. An active matrix type liquid crystal display device typically includes an active matrix substrate, a counter substrate, and a liquid crystal layer provided therebetween. A voltage is applied to the liquid crystal layer by a pixel electrode formed on the active matrix substrate and a counter electrode (common electrode) formed on the counter substrate, thereby changing the alignment state of the liquid crystal layer and polarizing light passing through the liquid crystal layer. The display is performed by controlling the state. Note that there is an IPS mode liquid crystal display device including a pixel electrode (display signal electrode) and a counter electrode on an active matrix substrate.
[0004]
At present, a TFT (thin film transistor) using an amorphous silicon thin film is widely used as a switching element of an active matrix type liquid crystal display device. Recently, TFTs using a polysilicon thin film formed by heat-treating an amorphous silicon thin film at a temperature of about 600 ° C. or higher, or by recrystallization by irradiation with an excimer laser or the like have been used. The polysilicon thin film has higher mobility than the amorphous silicon thin film, and forms not only a TFT provided for each pixel (TFT for a pixel) but also a TFT of a drive circuit for driving a pixel (TFT for a drive circuit). Therefore, there is an advantage that the driving circuit TFT can be integrally formed on the active matrix substrate.
[0005]
Since a liquid crystal display device is not a self-luminous display device, some kind of lighting device (light source) is required. For example, in the case of a transmissive liquid crystal display device, an illumination device (such as a backlight) is arranged behind the liquid crystal panel, and display is performed by light incident on the liquid crystal panel. Alternatively, in a projector (projection display device) or the like, a light source such as a metal halide lamp is used, and a lens system and a liquid crystal display panel are combined for projection display. In the case of the reflection type, display is performed by reflecting external incident light with a reflection electrode (or a reflection layer). Further, recently, a transmissive / reflective type liquid crystal display device (also referred to as a “semi-transmissive type”) having a transparent electrode and a reflective electrode for each pixel is used as a display device of a mobile phone or the like. .
[0006]
When semiconductors such as amorphous silicon and polysilicon are irradiated with light and light absorption occurs, electrons are excited in the conduction band and holes are excited in the valence band to generate electron-hole pairs, so-called photoelectric effect (internal photoelectric effect). Effect) occurs. Therefore, when light is applied to a semiconductor layer (including a channel region, a source region, and a drain region) of a TFT, a photocurrent due to an electron-hole pair is generated, and a leak current when the TFT is off increases. This causes problems such as deterioration of the display contrast ratio and the like.
[0007]
In the case of a transmissive (including semi-transmissive) liquid crystal display device, not only is the TFT exposed to direct light from the backlight, but also indirect incident light from directions other than the backlight can reach the TFT. There is. In the case of a projector or the like, light that has once passed through the liquid crystal display device may return to the TFT due to reflection on a lens system or the like. In order to prevent such incident light from reaching the TFT, a light-blocking layer for blocking light is disposed above and below the TFT to reduce leakage current. In the reflective liquid crystal display device, if the reflective electrode is arranged so as to cover the TFT, it is possible to prevent external light from directly reaching the semiconductor layer of the TFT.
[0008]
In recent years, transmission-type liquid crystal display devices have been developed with various light-shielding structures in order to suppress not only light incident perpendicularly to the active matrix substrate but also light leakage current due to light incident on the semiconductor layer of the TFT from an oblique direction. Has been proposed.
[0009]
For example, Patent Document 1 discloses a light shielding structure as shown in FIG. In the configuration shown in FIG. 6, the light-shielding layer 62 is arranged below the semiconductor layer 64 via the insulating layer 63, and the metal electrode layer 67 covering the semiconductor layer 64 is further provided on the insulating layers 63 and 65 via the insulating layer 65. It extends into the provided groove 66.
[0010]
Patent Document 2 discloses a light-shielding structure as shown in FIG. In the configuration shown in FIG. 7A, a light-shielding layer 72 is provided under a semiconductor layer 74 with an insulating layer 73 interposed therebetween, and a conductive material (here, a gate electrode material) is provided on a side wall of a dummy contact hole 76 formed in the insulating layer 73. Is formed. That is, in the illustrated example, after the semiconductor layer 74 and the gate insulating layer 75 are formed on the insulating layer 73, the dummy contact hole is formed in the insulating layer 73 before the gate electrode (not shown) is formed on the gate insulating layer 75. In a step of forming a gate electrode layer (including a gate electrode and a gate wiring), a layer having a light shielding property is formed on the side wall of the dummy contact hole. Note that Patent Document 2 also discloses a method in which a light-shielding film provided on a side wall of the dummy contact hole 76 uses a source electrode layer (including a source electrode and a source wiring).
[0011]
[Patent Document 1]
JP-A-2000-91581
[Patent Document 2]
JP 2000-356787 A
[0012]
[Problems to be solved by the invention]
However, the above conventional example has the following problems.
[0013]
In the configuration disclosed in Patent Document 1, as shown in FIG. 6A, a groove 66 penetrating the insulating layer 65 and the insulating layer 63 below the metal electrode layer 67 is formed. Usually, it is considered that the thickness of the insulating layer 65 below the metal electrode layer 67 usually needs to be about 0.5 μm to 1.5 μm. This is to obtain sufficient insulation between the gate electrode layer formed on the semiconductor layer 64 and the metal electrode layer 67 and to prevent an increase in the wiring capacitance of the metal electrode layer 67. The thickness of the insulating layer 63 is about 0.5 μm to 1 μm in order to obtain sufficient insulation between the semiconductor layer 64 and the light shielding layer 62. Therefore, the depth of the groove 66 penetrating the insulating layers 63 and 65 is 1 μm to 2.5 μm.
[0014]
When the metal electrode layer 67 is patterned at the bottom of the groove 66 having a depth of 1 μm or more (the portion where the surface of the transparent substrate 61 is exposed), the metal electrode layer 67 is not left as shown in FIG. The sidewall 70 may remain on the side wall of the side groove. Further, when a metal material (for example, Al) is deposited by a sputtering method or the like, the coverage of the metal material is deteriorated at the bottom of the groove 67 having a large aspect ratio (ratio of the groove depth to the groove width). As shown in FIG. 6 (c), the thickness of the metal material is reduced at the bottom of the groove 67. This tendency becomes more pronounced as the aspect ratio increases. Therefore, in order to form the metal material on the side wall of the groove 66 with good coverage by a sputtering method or the like, it is necessary to widen the width of the groove 66 so that the aspect ratio becomes about 0.5 to 1, and if so, 70 is formed at a distance of 1 μm to 2 μm or more from the side wall of the metal electrode layer 67. The sidewall 70 formed at such a position causes a reduction in the pixel aperture ratio.
[0015]
Among the configurations disclosed in Patent Document 2, as shown in FIG. 7A, when a configuration in which a light shielding layer is formed in a dummy contact hole 76 using a gate electrode layer is employed, a semiconductor other than a channel region is formed. Since the gate electrode layer cannot be left on the layer 74, no light-blocking layer is formed between the semiconductor layer 74 and the data line 77, and light incident obliquely from above reaches the semiconductor layer 74. There's a problem. In particular, in a TFT having an LDD (Lightly Doped Drain) structure having a low-concentration impurity region adjacent to a channel region in order to reduce a leakage current, the LDD portion has a large photoelectric conversion effect; In this case, there is a problem that the light leakage current increases. By forming the wide black matrix 78 on the insulating layer 77, incident light obliquely from above can be effectively blocked, but there is a problem that the aperture ratio is reduced.
[0016]
Further, a configuration in which the light-shielding layer 80 is formed in the dummy contact hole 75 by using the source electrode layer 77 disclosed in Patent Document 2 is adopted, and the depth of the dummy contact hole (groove) 75 is about 1 μm or more. If the width of the groove 75 is made small (for example, about 0.5 μm), when the source electrode material is deposited by the sputtering method or the like as described above, as shown schematically in FIG. Since the light-shielding layer 80 is formed near the entrance of the groove 75 and the electrode material is not supplied near the bottom of the groove 75 and a cavity is formed, it is expected that the electrode material will not be deposited on the side wall at the bottom of the groove 75. You. Therefore, similarly to the configuration described in Patent Document 1 described above, in order to form an electrode material with good coverage in a deep groove of 1 μm or more, it is necessary to increase the width of the groove 75 to about 1 μm to 2 μm or more. As a result, the aperture ratio is reduced.
[0017]
Here, the problem of the light shielding structure in the conventional active matrix type display device has been described by taking the liquid crystal display device as an example. However, the above problem is not limited to the liquid crystal display device. This is also a problem for display devices.
[0018]
The present invention has been made in view of the above points, and has an active matrix display device that effectively blocks light incident on a semiconductor layer of a switching element and suppresses a decrease in aperture ratio, and an active matrix display device used in the active matrix display device. It is intended to provide a matrix substrate.
[0019]
[Means for Solving the Problems]
An active matrix substrate according to the present invention is an active matrix substrate having a plurality of semiconductor elements formed on a substrate, wherein a semiconductor element portion on which each of the plurality of semiconductor elements is formed has a first element formed on the substrate. An insulating layer, a semiconductor layer formed on the first insulating layer, a first electrode layer formed on the semiconductor layer via an insulating film, and a second covering the first electrode layer and the semiconductor layer. An insulating layer, a first light-shielding layer formed on the first and second insulating layers and covering at least a part of the semiconductor layer, a third insulating layer formed on the first light-shielding layer, A second electrode layer formed on a third insulating layer, wherein an insulating laminated film including the first and second insulating layers is formed at a peripheral portion of the semiconductor layer; The laminated film has a groove near the periphery of the semiconductor layer, Is located below the second insulating layer, and the first light-shielding layer extends from above the semiconductor layer to the bottom of the groove, whereby the object is achieved. .
[0020]
In a preferred embodiment, the semiconductor device further includes a second light-shielding layer between the substrate and the first insulating layer below the semiconductor layer, and the second light-shielding layer has at least a part of a peripheral portion overlapping the groove. Are arranged as follows.
[0021]
The groove may penetrate the insulating laminated film, and the first light-shielding layer may contact the second light-shielding layer in the groove. Alternatively, the bottom of the groove may be formed in the first insulating layer and may not be in contact with the second light shielding layer.
[0022]
In a preferred embodiment, the semiconductor device further includes a fourth insulating layer formed on the second electrode layer, and a third light shielding layer formed on the fourth insulating layer, wherein the third light shielding layer is formed of the semiconductor. It is arranged to overlap at least a part of the layer.
[0023]
In a preferred embodiment, the first electrode layer is a gate electrode layer, and the second electrode layer includes a source electrode and a drain electrode.
[0024]
The one light-shielding layer has a source-side light-shielding portion and a drain-side light-shielding portion divided into two on the gate, and the source-side light-shielding portion and the drain-side light-shielding partially overlap the gate electrode. It may be arranged as follows.
[0025]
The first light-shielding layer may have conductivity, and the source-side light-shielding portion and the source electrode and / or the drain-side light-shielding portion and the drain electrode may be electrically connected to each other.
[0026]
In a preferred embodiment, each of the plurality of semiconductor elements has an LDD structure.
[0027]
The semiconductor layer has a source-side high-concentration region / source-side low-concentration region / channel region / drain-side low-concentration region / drain-side high-concentration region, and the first light-shielding layer includes the source-side low-concentration region / the channel Preferably, the trench covers at least the region / the low-concentration region on the drain side, and the groove is formed near the low-concentration region on the source side / the channel region / the low-concentration region on the drain side.
[0028]
The first light-shielding layer, and / or the second light-shielding layer, and / or the third light-shielding layer may be formed of at least one conductive film. That is, the light-shielding layer may have a single-layer structure including a single conductive film or a multilayer structure including a plurality of conductive films.
[0029]
The at least one conductive film is made of polysilicon, Ta, Ti, W, Mo, Cr, Ni, MoSi. ₂ , TaSi ₂ , WSi ₂ , CoSi ₂ , NiSi ₂ , PtSi, Pd ₂ S, HfN, ZrN, TiN, TaN, NbN, TiC, TaC and TiB ₂ Is preferably formed from at least one material selected from the group consisting of:
[0030]
It is preferable that the semiconductor layer is formed of amorphous silicon, polycrystalline silicon, or single crystal silicon.
[0031]
A display device according to the present invention includes any one of the active matrix substrates described above and a display medium layer.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the configuration of the display device according to the embodiment of the present invention will be described with reference to the drawings. Here, an active matrix liquid crystal display device including a MIS (Metal Insulator Semiconductor) field effect transistor (TFT) as a switching element will be described as an example, but the present invention is not limited to this.
[0033]
FIG. 1 is a cross-sectional view schematically showing a portion (semiconductor element portion) of an active matrix substrate according to an embodiment of the present invention on which a semiconductor element is formed.
[0034]
The semiconductor element portion of the active matrix substrate includes a first insulating layer 3a formed on the substrate 1a, a semiconductor layer 4a formed on the first insulating layer 3a, and a first electrode formed on the semiconductor layer 4a. A layer 5a, a second insulating layer 6a covering the first electrode layer 5a and the semiconductor layer 4a, and a first light-shielding layer formed on the first insulating layer 3a and the second insulating layer 6a and covering at least a part of the semiconductor layer 4a. It has a layer 8a, a third insulating layer 9a formed on the first light shielding layer 8a, and a second electrode layer 11a formed on the third insulating layer 9a. An insulating laminated film including a first insulating layer 3a and a second insulating layer 6a is formed at a peripheral portion of the semiconductor layer 4a, and the insulating laminated film has a groove 7a near a peripheral edge of the semiconductor layer 4a. The bottom of the groove 7a is located below the second insulating layer 6a, and the first light shielding layer 8a extends from above the semiconductor layer 4a to the bottom of the groove 7a.
[0035]
The active matrix substrate further includes a second light-shielding layer 2a between the substrate 1a below the semiconductor layer 4a and the first insulating layer 3a, and the second light-shielding layer 2a has at least a part of a peripheral edge formed by a groove. 7a. The active matrix substrate includes a fourth insulating layer 12a formed on the second electrode layer 11a, and a third light shielding layer 13a formed on the fourth insulating layer 12a. Are arranged so as to overlap at least a part of the semiconductor layer 11a. Depending on the arrangement of the active matrix substrate and the configuration of the display device, one or both of the second light-shielding layer 2a and the third light-shielding layer 13a may be omitted.
[0036]
Since the active matrix substrate according to the embodiment of the present invention has the above-described configuration, the first light-shielding layer (also referred to as “intermediate light-shielding layer”) may be closer to the semiconductor layer 4a than the above-described conventional configuration. .) 8a can be arranged, so that the aperture ratio is hardly reduced, the light LA incident from the upper oblique direction can be blocked, and the first light shielding layer 8a formed on the side wall of the groove 7a allows the light LA to enter from the lower oblique direction. Light LB can also be shielded. Here, as shown in FIG. 1, the first light-shielding layer 8a is preferably formed so as to cover both side surfaces of the groove 7a, but if it extends at least to the bottom of the groove 7a, it is practically possible. In some cases, a sufficient light-shielding effect can be obtained.
[0037]
The TFT illustrated here is of a top gate type, and the first electrode layer 5a is a gate electrode layer (an electrode layer including a gate electrode and a gate wiring and formed in the same step) and a second electrode layer 5a. The layer 11a is a source electrode layer including a source electrode and a drain electrode (an electrode layer including a source electrode, a source wiring, and a drain electrode and formed in the same step). Note that the first electrode layer 5a shown in FIG. 1 is a gate electrode, and the second electrode layer 11a is a source wiring. An insulating layer (gate insulating layer) 5b is provided between the first electrode layer (gate electrode) 5a and the semiconductor layer 4a.
[0038]
Typically, the thickness of the second insulating layer 6a can be 0.1 μm to 0.3 μm, so that the depth of the groove 7a is about 0.6 μm to 1.3 μm, which is about half of the conventional depth. Therefore, the first light-shielding layer 8a can be formed with good coverage even if the width of the groove 7a is also reduced accordingly. As a result, a decrease in the aperture ratio can be suppressed as much as possible.
[0039]
Here, the bottom of the groove 7a is formed in the first insulating layer 3a, and the first light-shielding layer 8a and the second light-shielding layer 2a are not in contact with each other. A configuration in which the first light-shielding layer 8a penetrates the insulating layer 3a and contacts the second light-shielding layer 2a in the groove 7a may be employed. When a configuration in which the first light-shielding layer 8a and the second light-shielding layer 2a are not in contact with each other is employed, the degree of freedom of the voltage applied to the first light-shielding layer 8a and the second light-shielding layer 2a can be increased. Conversely, if the first light-shielding layer 8a is configured to be in contact with the second light-shielding layer 2a in the groove 7a, light incident on the semiconductor layer 4a can be further reduced. Which configuration is adopted is appropriately selected according to the application and the like.
[0040]
Further, as specifically described later, the first light-shielding layer 8a may be divided into two on the gate electrode 5a into a source-side light-shielding portion and a drain-side light-shielding portion. With this configuration, a voltage can be independently applied to the source side and the drain side. For example, by applying a voltage independently to at least one of the source-side light-shielding portion and the drain-side light-shielding portion, the first light-shielding layer can be applied. An increase in capacity due to the formation of 8a can be suppressed. At this time, it is preferable from the viewpoint of light-shielding properties that the source-side light-shielding portion and the drain-side light-shielding portion are arranged so as to partially overlap the gate electrode.
[0041]
In order to reduce the leakage current of the TFT, an LDD (Lightly Doped Drain) structure may be employed. At this time, the first light-shielding layer 8a covers at least the source-side low-concentration region / channel region / drain-side low-concentration region, and the groove 7a is formed near the source-side low-concentration region / channel region / drain-side low-concentration region. Is preferred. When light is irradiated to these regions of the semiconductor layer 4a, a leak current is significantly increased. Therefore, it is preferable to shield these regions from light.
[0042]
When the first light-shielding layer 8a, the second light-shielding layer 2a, and the third light-shielding layer 13a are formed of a material having conductivity, as will be described later, there is an advantage that the potential of each layer can be controlled and a common material for forming the conductive layer. However, a material having no conductivity may be used.
[0043]
Preferred materials having conductivity used for forming the light-shielding layer include metals such as Ta, Ti, W, Mo, Cr and Ni, semiconductors such as polysilicon, and MoSi. ₂ , TaSi ₂ , WSi ₂ , CoSi ₂ , NiSi ₂ And metal silicide such as PtSi, and Pd ₂ S, HfN, ZrN, TiN, TAN, NbN, TiC, TaC and TiB ₂ And the like. The light shielding layer may have a single-layer structure or a multilayer structure. The above materials are easy to form a film and have excellent light-shielding properties. The semiconductor layer is formed using a general-purpose semiconductor material such as amorphous silicon, polycrystalline silicon, and single crystal silicon.
[0044]
The active matrix substrate shown in FIG. 1 is suitably used for a liquid crystal display device. Typically, a backlight (or light source) is disposed below the substrate 1 in FIG. 1, but the present invention is not limited to this. 1 may be arranged on the observer side (or the projection optical system side).
[0045]
(Embodiment 1)
As shown in FIG. 2A, a light-shielding layer serving as a lower light-shielding layer (second light-shielding layer) of a TFT is deposited on a transparent substrate 1 such as glass or quartz by a CVD method or a sputtering method. After the etching step, the lower light-shielding layer 2 is formed. As the light-shielding layer, a metal film (Ta, Ti, W, Mo, Cr, Ni) or a single-layer film of polysilicon, MoSi ₂ , TaSi ₂ , WSi ₂ , CoSi ₂ , NiSi ₂ , PtSi, Pd ₂ S, HfN, ZrN, TiN, TaN, NbN, TiC, TaC, TiB ₂ A material having a light-shielding effect, such as a material obtained by combining them, or a combination thereof is used.
[0046]
Next, as shown in FIG. ₂ An insulating layer 3 such as a film is deposited. The thickness is about 200 nm to 1000 nm, for example, about 500 nm. Although light from below the semiconductor layer can be blocked by forming the lower light-shielding layer 2, the lower light-shielding layer is not necessarily formed if the influence of the increase in leakage current due to light from below the semiconductor layer is not significant. No need.
[0047]
Next, as shown in FIG. 2C, an active layer (semiconductor layer) 4 of the transistor is formed on the insulating layer 3. The active layer is formed from a semiconductor such as Si, Ge, GaAs, GaP, CdS, and CdSe, and may be in the form of amorphous, polycrystalline, single crystal, or the like. For example, in the case of polycrystalline silicon, generally, after depositing an amorphous silicon thin film on the insulating layer 3 to a thickness of about 50 nm to 200 nm by CVD or the like, the polycrystalline silicon is subjected to heat treatment at a high temperature or laser light irradiation. Allow to crystallize. Thereafter, patterning is performed by a photolithography step and an etching step to form an active layer 4 having a predetermined shape. Thereafter, impurity ions may be implanted for controlling the threshold voltage.
[0048]
As shown in FIG. 2D, a gate insulating layer 5 is formed on the active layer 4 to a thickness of about 50 to 200 nm, for example, 100 nm. The gate insulating layer 5 is formed by deposition by CVD, oxidation, or both. Subsequently, a gate electrode 6 is formed on the gate insulating layer 5.
[0049]
Next, as shown in FIG. 2E, using the gate electrode 6 as a mask, an N-type low concentration impurity (phosphorus, arsenic, etc.) ¹² ~ 1 × 10 ¹⁴ cm ^-2 A low dose impurity region 7 and 8 is formed by implanting ions into the active layer 4 by ion implantation at a moderate dose. The portion below the gate electrode 6 becomes the channel region 9.
[0050]
Next, as shown in FIG. 2F, after forming a mask 10 with a photoresist, an N-type high-concentration impurity (phosphorus, arsenic, etc.) ^Fifteen ~ 5 × 10 ^Fifteen cm ^-2 Then, a source-side high-concentration impurity region 11 and a drain-side high-concentration impurity region 12 are formed outside the low-concentration impurity regions 7 and 8. By forming the low-concentration impurity regions 7 and 8 between the channel region 9 and the source-side high-concentration impurity regions 11 and the drain-side high-concentration impurity regions 12 to form an LDD structure, the electric field strength between the channel and the drain is reduced. As a result, the effect of reducing the leak current can be obtained. The step of forming the low-concentration impurity region is not necessarily performed.
[0051]
Subsequently, as shown in FIG. 2G, after removing the mask 10, an interlayer insulating layer 13 is deposited to a thickness of about 100 to 300 nm by CVD or the like. Thereafter, a groove 14 (shown by a broken line) is formed in a portion of the interlayer insulating layer 13 above the lower light shielding layer 2. When the intermediate light-shielding layer has the same potential as the lower light-shielding layer 2, the groove 14 is formed to a depth reaching the lower light-shielding layer 2. Here, the case where the groove 14 that does not reach the lower light shielding layer 2 is formed will be described. If a configuration is adopted in which the groove 14 (that is, the intermediate light-shielding layer 15 (see FIG. 3C) formed so as to fill the groove 14) does not reach the lower light-shielding layer 2, the potential of the intermediate light-shielding layer 15 is reduced. And can be set independently.
[0052]
FIG. 3A is a cross-sectional view taken along line AA ′ of FIG. Here, the trench 14 is formed so as to surround the low-concentration impurity regions 7 and 8 of the semiconductor layer 4. The depth of the groove 14 is formed so as not to reach the lower light shielding layer 2.
[0053]
The width of the groove 14 is set so that the aspect ratio is in the range of 0.5 to 1 so that the intermediate light-shielding layer 15 formed later sufficiently covers the side wall of the groove 14. For example, when the thickness of the insulating layer 3 is 500 nm, the thickness of the gate insulating layer 5 is 100 nm, and the thickness of the interlayer insulating layer 13 is 200 nm, the width of the groove 14 is set to 0.5 μm to 1 μm.
[0054]
FIG. 3B is a view of FIG. 2G and FIG. 3A viewed from above. The trench 14 is formed along the semiconductor layer 4 and includes a boundary portion between the source-side high-concentration impurity region 11 and the low-concentration impurity region 7, a low-concentration impurity region 7, a boundary portion between the low-concentration impurity region 7 and the channel region 9, a channel region. 9 and the low-concentration impurity region 8, the low-concentration impurity region 8, and the boundary between the low-concentration impurity region 8 and the drain-side high-concentration impurity region 12.
[0055]
Subsequently, as shown in FIG. 3C, a light-shielding layer serving as the intermediate light-shielding layer 15 is deposited by a CVD method, a sputtering method, or the like, and is subjected to a photolithography step and an etching step, so that the intermediate light-shielding layer (first light-shielding layer) is obtained. 15 are formed. As the light-shielding layer, a metal film (Ta, Ti, W, Mo, Cr, Ni) or a single-layer film of polysilicon, MoSi ₂ , TaSi ₂ , WSi ₂ , CoSi ₂ , NiSi ₂ , PtSi, Pd ₂ S, HfN, ZrN, TiN, TAN, NbN, TiC, TaC, TiB ₂ A material having a light-shielding effect, such as a material obtained by combining them, or a combination thereof is used.
[0056]
The light-shielding layer 15 includes at least a boundary portion between the source-side high-concentration impurity region 11 and the low-concentration impurity region 7, a low-concentration impurity region 7, a boundary portion between the low-concentration impurity region 7 and the channel region 9, and a channel region 9 and the low-concentration impurity region. 8, the low-concentration impurity region 8, and the boundary between the low-concentration impurity region 8 and the drain-side high-concentration impurity region 12 are preferably formed. When light is irradiated to these regions, the light leakage current increases significantly. Therefore, it is preferable to shield at least these regions.
[0057]
Further, since the intermediate light-shielding layer 15 is formed in an L-shape along the step of the gate electrode (gate electrode layer) 6, the distance between the intermediate light-shielding layer 15 and the semiconductor layer 4 in a portion where there is no gate electrode layer is reduced. Since the light does not spread, light incident from an oblique direction can be effectively blocked.
[0058]
FIG. 3D shows a cross section AA ′ of FIG. Since the groove 14 is arranged on the lower light-shielding layer 2 and the intermediate light-shielding layer 15 is formed with good coverage on the inner wall of the groove 14, light from obliquely below can be effectively shielded.
[0059]
Next, as shown in FIG. 4A, an insulating layer is deposited on the entire surface, for example, to a thickness of about 600 nm, and an interlayer insulating layer 16 is formed. Subsequently, a contact hole 17 for taking out an electrode is opened on the source-side high-concentration impurity region 11 and the drain-side high-concentration impurity region 12, and a source electrode 18 and a drain electrode 19 made of a metal material such as Al are formed. The source electrode 18 and the drain electrode 19 are formed in the same step together with a source wiring (not shown), and may be collectively referred to as a source electrode layer or a data electrode layer.
[0060]
Note that the interlayer insulating layer 16 may be formed by BPSG (borophosphosilicate glass) and then heat-treated at a high temperature of about 850 ° C. to 950 ° C., or may be planarized by a CMP (Chemical Mechanical Planarization) process or the like.
[0061]
Next, as shown in FIG. 4B, a nitride film 20 is deposited on the entire surface, a passivation film is formed, and a hydrogenation process is performed. Subsequently, the SiO ₂ After depositing an interlayer insulating layer such as, for example, the interlayer insulating layer 21 is formed by flattening by etch back or CMP.
[0062]
Next, as shown in FIG. 4C, a light-shielding layer to be an upper light-shielding layer (third light-shielding layer) 22 of the transistor is deposited by a CVD method, a sputtering method, or the like, and is patterned to form the upper light-shielding layer 22. Form. As the light-shielding layer, a metal film (Ta, Ti, W, Mo, Cr, Ni) or a single-layer film of polysilicon, MoSi ₂ , TaSi ₂ , WSi ₂ , CoSi ₂ , NiSi ₂ , PtSi, Pd ₂ S, HfN, ZrN, TiN, TAN, NbN, TiC, TaC, TiB ₂ A material having a light-shielding effect, such as a material obtained by combining them, or a combination thereof is used. Note that if the intermediate light-blocking layer 15 blocks light from above the semiconductor layer 4 sufficiently, the upper light-blocking layer may or may not be formed.
[0063]
Thereafter, although not shown, after forming an insulating layer, a contact hole is formed in the insulating layer, and a pixel electrode electrically connected to the drain electrode 19 is formed using a transparent conductive material such as ITO.
[0064]
FIG. 4D shows an AA ′ section of FIG. 4C. Since the intermediate light-blocking layer 15 blocks the light LA entering obliquely from above and the light LB entering obliquely from below, the light does not reach the low-concentration impurity region 7 of the active layer 4, so that the occurrence of light leakage current can be suppressed.
[0065]
(Embodiment 2)
FIG. 5 is a schematic sectional view of a semiconductor element portion of an active matrix substrate according to another embodiment of the present invention.
[0066]
After forming the interlayer insulating layer 13 in the same manner as in the active matrix substrate of the first embodiment, contact holes 31 and 32 are formed on the source-side high-concentration impurity region 11 and the drain-side high-concentration impurity region 12, respectively. An intermediate light shielding layer is formed. Here, when the intermediate light-shielding layer is patterned, the intermediate light-shielding layer 33 is divided into two parts on the gate electrode 6 to form an intermediate light-shielding part 33 on the source electrode side and an intermediate light-shielding part 34 on the drain electrode side.
[0067]
Thereafter, the source electrode 18 is electrically connected to the intermediate light-shielding layer 33 on the source electrode side, and the drain electrode 19 is electrically connected to the intermediate light-shielding layer 34 on the drain electrode side.
[0068]
When such a configuration is adopted, a degree of freedom to apply a voltage to the source-side intermediate light-shielding portion 33 and the drain-side intermediate light-shielding portion 34 independently can be obtained.
[0069]
Note that even if the potentials of the source-side intermediate light-shielding portion 33 and the drain-side intermediate light-shielding portion 34 are not fixed to the source potential and the drain potential but are fixed to different potentials without forming the contact holes 31 and 32. Good or not fixed. Of course, only one of the source-side intermediate light-shielding portion 33 and the drain-side intermediate light-shielding portion 34 may be fixed at the source potential or the drain potential.
[0070]
Using the active matrix substrates of Embodiments 1 and 2, a liquid crystal panel can be manufactured according to a known manufacturing method. The obtained liquid crystal panel is suitably used for a direct-view transmission-type liquid crystal display device and a projection-type liquid crystal display device. In particular, as exemplified in the embodiment, by providing the intermediate light-shielding layer together with the upper and lower light-shielding layers, a liquid crystal panel having extremely excellent light-shielding performance can be obtained, which is suitable for a projection display device in which strong light is irradiated. Used.
[0071]
【The invention's effect】
According to the present invention, there is provided an active matrix display device that effectively blocks light incident on a semiconductor layer of a switching element and suppresses a decrease in aperture ratio, and an active matrix substrate used therein.
[0072]
INDUSTRIAL APPLICABILITY The present invention is suitably applied to a transmissive liquid crystal display device, a transmissive / reflective liquid crystal display device, and a non-self-luminous display device such as a projection liquid crystal display device and an electrophoretic display device.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a semiconductor element portion of an active matrix substrate according to an embodiment of the present invention.
FIGS. 2A to 2G are schematic views for explaining a manufacturing process of a semiconductor element portion of an active matrix substrate according to Embodiment 1 of the present invention.
FIGS. 3A to 3D are schematic views for explaining another manufacturing process of the semiconductor element portion of the active matrix substrate according to the first embodiment of the present invention.
FIGS. 4A to 4D are schematic views for explaining another manufacturing process of the semiconductor element portion of the active matrix substrate according to the first embodiment of the present invention.
FIG. 5 is a sectional view schematically showing a semiconductor element portion of an active matrix substrate according to a second embodiment of the present invention.
FIGS. 6A to 6C are cross-sectional views schematically showing a semiconductor element portion of a conventional active matrix substrate.
FIGS. 7A and 7B are cross-sectional views schematically showing a semiconductor element portion of another conventional active matrix substrate.
[Explanation of symbols]
1a Substrate
2a Second light shielding layer (lower light shielding layer)
3a first insulating layer
4a Semiconductor layer
5a first electrode layer
5b Insulating layer (gate insulating layer)
6a Second insulating layer
7a groove
8a First light-shielding layer (intermediate light-shielding layer)
9a Third insulating layer
11a Second electrode layer
12a fourth insulating layer
13a Third light-shielding layer (upper light-shielding layer)
1 Transparent substrate
2 Lower shading layer
3 insulating layer
4 Active layer
5 Gate insulating layer
6 Gate electrode
7, 8 Low concentration impurity region (LDD)
9 Channel area
10. Mask formed from photoresist
11 Source area
12 Drain region
13 Interlayer insulation layer
14 grooves
15 Intermediate shading layer
16 Interlayer insulation layer
17 Contact hole
18 Source electrode
19 Drain electrode
20 nitride film
21 Interlayer insulation layer
22 Upper shading layer
31, 32 Contact hole
33 Intermediate shading layer on source electrode side
34 Intermediate shading layer on drain electrode side
61 Transparent substrate
62 Shading layer
63 insulating layer
64 semiconductor layer
65 Insulation layer
66 grooves
67 Metal electrode layer
70 Sidewall
71 Transparent substrate
72 Shading layer
73 insulating layer
74 Semiconductor layer
75 Dummy contact hole
76 Dummy contact hole
77 insulating layer
78 data line
79 Black Matrix

Claims (14)

An active matrix substrate in which a plurality of semiconductor elements are formed on a substrate, and a semiconductor element portion in which each of the plurality of semiconductor elements is formed,
A first insulating layer formed on the substrate,
A semiconductor layer formed on the first insulating layer;
A first electrode layer formed on the semiconductor layer via an insulating film;
A second insulating layer covering the first electrode layer and the semiconductor layer;
A first light-blocking layer formed on the first and second insulating layers and covering at least a part of the semiconductor layer;
A third insulating layer formed on the first light shielding layer;
A second electrode layer formed on the third insulating layer,
An insulating laminated film including the first and second insulating layers is formed at a peripheral portion of the semiconductor layer, and the insulating laminated film has a groove near a peripheral edge of the semiconductor layer, An active matrix substrate, wherein the bottom of the active matrix substrate is located below the second insulating layer, and the first light shielding layer extends from above the semiconductor layer to the bottom of the groove. The semiconductor device further includes a second light-shielding layer between the substrate and the first insulating layer below the semiconductor layer, and the second light-shielding layer is disposed so that at least a part of a peripheral portion overlaps the groove. The active matrix substrate according to claim 1. 3. The active matrix substrate according to claim 2, wherein the groove penetrates the insulating laminated film, and the first light shielding layer is in contact with the second light shielding layer in the groove. 4. The active matrix substrate according to claim 2, wherein a bottom of the groove is formed in the first insulating layer. A fourth insulating layer formed on the second electrode layer; and a third light-shielding layer formed on the fourth insulating layer, wherein the third light-shielding layer is at least part of the semiconductor layer. The active matrix substrate according to claim 1, wherein the active matrix substrate is arranged to overlap. The active matrix substrate according to claim 1, wherein the first electrode layer is a gate electrode layer, and the second electrode layer includes a source electrode and a drain electrode. The one light-shielding layer has a source-side light-shielding portion and a drain-side light-shielding portion divided into two on the gate, and the source-side light-shielding portion and the drain-side light-shielding partially overlap the gate electrode. The active matrix substrate according to claim 6, wherein the active matrix substrate is arranged as follows. The said 1st light shielding layer has electroconductivity, The said source side light shielding part and the said source electrode, and / or the said drain side light shielding part and the said drain electrode are electrically connected with each other. The active matrix substrate according to the above. 9. The active matrix substrate according to claim 1, wherein each of the plurality of semiconductor elements has an LDD structure. The semiconductor layer has a source-side high-concentration region / source-side low-concentration region / channel region / drain-side low-concentration region / drain-side high-concentration region, and the first light-shielding layer includes the source-side low-concentration region / the channel The active matrix substrate according to claim 9, wherein at least the region / the drain-side low-concentration region is covered, and the groove is formed near the source-side low-concentration region / the channel region / the drain-side low-concentration region. . The active matrix according to any one of claims 1 to 10, wherein the first light-shielding layer and / or the second light-shielding layer and / or the third light-shielding layer are formed of at least one conductive film. substrate. The at least one conductive film is made of polysilicon, Ta, Ti, W, Mo, Cr, Ni, MoSi ₂ , TaSi ₂ , WSi ₂ , CoSi ₂ , NiSi ₂ , PtSi, Pd ₂ S, HfN, ZrN, TiN. , TaN, NbN, TiC, and is formed from at least one material selected from the group consisting of TaC and TiB _2, the active matrix substrate according to claim 11. The active matrix substrate according to claim 1, wherein the semiconductor layer is formed of amorphous silicon, polycrystalline silicon, or single crystal silicon. A display device comprising the active matrix substrate according to claim 1 and a display medium layer.

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