JP2004158052A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory, by which data are read out without problem even when a leak current is in existence. <P>SOLUTION: The nonvolatile semiconductor memory has: a plurality of nonvolatile memory cells; bit lines to which the plurality of memory cells are connected; a plurality of word lines connected to the plurality of memory cells; and a sense amplifier circuit for detecting a 1st current flowing in the bit lines with the state inactivating any of the plurality of word lines, and for detecting a 2nd current flowing in the bit lines with the state selectively activating one of the plurality of word lines, to discriminate the data by the large/small relation between a sum of values of the 1st current and a prescribed offset and a 2nd current value. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device that performs data determination by comparing currents at the time of reading.
[Prior art]
In a flash memory, a plurality of cells in a predetermined group of areas (sectors) are collectively erased. Therefore, the threshold values of a plurality of cells in the same sector do not become the same threshold value after erasing, and a certain degree of distribution is obtained. Will have. Depending on the erased state, the threshold of some cells may be 0 or less (over-erased state). When an over-erased cell exists on the bit line selected in the read operation, even if the word line of the over-erased cell is not selected, a current flows through the over-erased cell because the threshold value is 0 or less. For this reason, the current of the actually selected cell cannot be correctly detected, and there is a possibility that data reading is erroneously performed.
[0002]
In the conventional reading method, the threshold value of the reference cell is set between the threshold value of the erasing cell and the threshold value of the writing cell, and the same word line potential is applied to the reference cell and the reading cell. Compare the flowing current. When the current of the read cell is larger than the current of the reference cell, the erase data is “1”. When the current of the read cell is smaller than the current of the reference cell, the data is determined as the write data “0”. At this time, the higher the potential of the selected word line, the larger the amount of current flowing through the read cell and the reference cell.
[0003]
FIG. 1 is a diagram showing a relationship between a read cell current and a reference cell current.
[0004]
As shown in FIG. 1, when the leak current of the over-erased cell is added to the current of the read cell, the current value to be compared with the current of the reference cell increases by the leak current. Therefore, when the potential of the selected word line is low (in the example of FIG. 1, 3.4 V or less), even if the read target cell is a write cell, the leak current is larger than the current flowing through the reference cell, and the erase operation is performed. It is determined as data “1”.
[0005]
However, as described above, the higher the potential of the selected word line, the greater the amount of current flowing through the read cell and the reference cell. Therefore, if the potential of the selected word line is increased (3.4 V or more in the example of FIG. 1), the write operation is performed. The sum of the cell current and the leak current is always smaller than the current flowing through the reference cell, and can be correctly recognized as write data “0”. The potential of the selected word line for correctly determining data increases as the leak current increases.
[0006]
However, if the leak current is larger than the difference between the write cell current and the reference cell current, reading cannot be performed regardless of the word line potential. Therefore, in the write operation, the threshold value of the write cell needs to be set sufficiently large.
[0007]
There is a related art that provides a nonvolatile semiconductor memory device which does not need to include a reference cell for data reading and whose data reading characteristics are not affected by the magnitude of a power supply voltage (Patent Document 1).
[0008]
[Patent Document 1]
JP-A-11-39884 [Problems to be solved by the invention]
As described above, in the conventional read method, the condition of the threshold value of the write cell that can be read normally becomes strict due to the influence of the leak current caused by the over-erased non-selected cells. In order to eliminate the erroneous determination due to the influence of the leak current, it is necessary to raise the selected word line at the time of reading to a high potential. Therefore, a circuit (a booster) for boosting the word line is specially required. I will. This leads to an increase in the circuit scale and an increase in cost.
[0009]
In view of the above, it is an object of the present invention to provide a nonvolatile semiconductor memory device that can read data without any problem even when a leak current exists.
[0010]
It is another object of the present invention to provide a nonvolatile semiconductor memory device which does not require a booster circuit for boosting the potential of a selected word line at the time of reading.
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to the present invention includes a plurality of nonvolatile memory cells, a bit line connected to the plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, The first current flowing through the bit line is detected in a state where none of the word lines are activated, and the second current flowing through the bit line is detected while one of the plurality of word lines is selectively activated. And a sense amplifier circuit for determining data based on the magnitude relationship between the sum of the first current value and the predetermined offset value and the second current value.
[0011]
In the above-described nonvolatile semiconductor memory device, since the two values to be compared both include the leak current, the leak current is canceled regardless of the magnitude of the leak current, and the data can be reliably determined. Further, since a reference cell is not required for reading and generating a reference potential, the circuit scale can be reduced and cost can be reduced. Further, since there is no need to boost the potential of the selected word line at the time of reading, a boosting circuit dedicated to the read word is not required, and the circuit size can be reduced and cost can be reduced.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0012]
FIG. 2 is a diagram for explaining a read operation according to the present invention.
[0013]
In the present invention, the reference cell is not used in the data determination at the time of reading. Therefore, the reference current is not shown in FIG. Instead of the current flowing through the reference cell, in the present invention, a current obtained by adding an offset to the leak current flowing through the overerased cell is used as the current to be compared. . In the example of FIG. 2, the leak current is 10 μA, and “leak current + offset” obtained by adding an offset to the leak current is a constant current larger than 10 μA.
[0014]
If the sum of the current of the cell to be read and the leak current is larger than “leak current + offset”, data is determined as erase data “1”. When the read target is an erased cell, the sum of the current of the read target cell and the leak current becomes larger than “leak current + offset” on the right side of the drawing in FIG. Therefore, the word line voltage needs to be 2.3 V or more corresponding to the point A.
[0015]
If the sum of the current of the cell to be read and the leak current is smaller than “leak current + offset”, the data is determined as write data “0”. When the read target is a write cell, the sum of the current of the read target cell and the leak current becomes smaller than “leak current + offset” on the left side of the drawing from point B in the drawing. Therefore, the word line voltage needs to be 4.3 V or less corresponding to the point B.
[0016]
Therefore, in the example of FIG. 1, by setting the word line potential between 2.3 V and 4.3 V, normal data reading can be performed regardless of the presence of a leak current. Therefore, for example, the word line potential may be set to 3.0 V, and if the external power supply voltage is 3.0 V, a conventional booster circuit for boosting the word line becomes unnecessary.
[0017]
FIG. 3 is a diagram showing an example of the configuration of the nonvolatile semiconductor memory device according to the present invention.
[0018]
3 includes a control circuit 11, an input / output buffer 12, an address buffer 13, a row decoder 14, a column decoder 15, a cell array 16, a cascode / sense amplifier 17, a write / erase circuit 18, and a command register. 19 inclusive.
[0019]
The control circuit 11 receives a command signal from the outside via the command register 19 and receives an address signal from the outside via the address buffer 13. Further, the control circuit 11 receives control signals such as a write enable signal and a chip enable signal and a data signal from outside. The control circuit 11 operates as a state machine based on these signals, and controls the operation of each unit of the nonvolatile semiconductor memory device 10.
[0020]
The input / output buffer 12 receives a data signal from the outside, and supplies the received data to the cascode / sense amplifier 17. The address buffer 13 receives and latches an externally supplied address signal, and supplies the received address signal to the row decoder 14, the column decoder 15, and the control circuit 11. The row decoder 14 decodes the address supplied from the address buffer 13 and activates a word line provided in the cell array 16 according to the decoding result. The column decoder 15 decodes the address supplied from the address buffer 13, selectively reads the data of the bit line of the cell array 16 based on the decoding result, and supplies the data to the cascode / sense amplifier 17.
[0021]
The cell array 16 includes an array of memory cell transistors, word lines, bit lines, and the like, and stores data in each memory cell transistor. At the time of data reading, data from a memory cell specified by the activation word line is read to a bit line. At the time of programming or erasing, by setting the word line and the bit line to appropriate potentials according to the respective operations, the operation of injecting or extracting the charge to the memory cell is executed.
[0022]
The cascode / sense amplifier 17 receives the current supplied from the cell array 16 in accordance with the position selection by the column decoder 15 and the row decoder 14, and determines whether the read data is 0 or 1 based on the sum of the leak current and the offset. Determine if there is any. The determination result is supplied to the input / output buffer 12 as read data. The verify operation accompanying the program operation (write operation) and the erase operation (erase operation) can be executed in the same manner as the read operation.
[0023]
The write / erase circuit 18 operates under the control of the control circuit 11, and generates a program voltage (step-up voltage for programming). By driving the row decoder 14 and the column decoder 15 using this program voltage, a data write operation to the cell array 16 is executed in accordance with the write data supplied from the input / output buffer 12 to the cascode / sense amplifier 17. The write / erase circuit 18 further generates an erase voltage to be applied to the word line and the bit line at the time of the erase operation, and executes the erase operation of the cell array 16 in sector units based on this voltage.
[0024]
In the nonvolatile semiconductor memory device 10 of FIG. 3, a booster circuit (booster) for boosting the potential of the word line selectively activated by the row decoder 14 at the time of data reading is not provided. Further, a reference cell circuit to be compared with read data at the time of reading is not provided.
[0025]
FIG. 4 is a diagram illustrating an example of the configuration of the cell array 16 and the column decoder 15.
[0026]
In FIG. 4, memory cell transistors 21 are arranged vertically and horizontally, and memory cell transistors 21 in one row in the horizontal direction are commonly connected to a corresponding one of word lines WL0 to WL1. The word line supplies a gate voltage to each memory cell transistor 21. The source terminal of each memory cell transistor 21 is connected to the ground potential via the transistor 25.
[0027]
When the word line is selectively activated, in the memory cell transistor 21 connected to the word line, the drain terminal connected to the bit lines BL (p) _0, BL (p) _1,... Electric current flows. This current amount is an amount corresponding to the data value of “0” or “1”. Even if the memory cell transistor 21 is connected to a word line that is not selectively activated, if this is an overerased cell, a leak current flows from the bit line to the ground.
[0028]
The bit lines BL (p) _0, BL (p) _1,... Are selectively connected to the cascode / sense amplifier 17 by a plurality of transistors 23 and 24 which are selectively turned on in accordance with a designated column address. You. Specifically, the current supplied from the cascode / sense amplifier 17 flows to the read cell via the selected bit line, so that the current signal DATACELL is supplied to the cascode / sense amplifier 17.
[0029]
FIG. 5 is a diagram showing an example of a configuration of a part of the cascode / sense amplifier 17. FIG. 5 shows a pre-sense amplifier portion of the cascode / sense amplifier 17.
[0030]
The pre-sense amplifier 30 is a circuit that converts a current flowing through a memory cell into a voltage, and includes PMOS transistors 31 and 32 and NMOS transistors 33 to 39. The signal PD is a signal that is LOW during the read operation. The signal ATD is HIGH in order to detect the sum of the leak current and the offset current immediately after the start of the read operation in response to the address change.
[0031]
Immediately after the address signal changes and the read operation starts, all the word lines in FIG. 4 are not selected and only the leak current flows. As a result, a current flows from the node N in FIG. 5 to the bit line in FIG. 4 as the current signal DATACELL. At this time, the signal ATD generated according to the change in the address is set to HIGH, and a predetermined amount of current flows from the node N to the ground potential via the transistors 38 and 39 in addition to the current signal DATACELL. The sum of both currents is converted from a current value to a voltage value by the circuit of FIG. 5 and output as a voltage signal SAIN. That is, a voltage corresponding to the current amount of “leak current + offset” is output as the voltage signal SAIN.
[0032]
After that, in FIG. 4, the word line is selectively activated, and a current (and a leak current) of the read cell flows. As a result, a current flows from the node N in FIG. 5 to the bit line in FIG. 4 as the current signal DATACELL. At this time, the signal ATD is LOW, and only the current signal DATACELL becomes a current flowing through the node N. This current is converted from a current value to a voltage value by the circuit of FIG. 5 and output as a voltage signal SAIN. That is, a voltage corresponding to the amount of “read cell current + leakage current” is output as the voltage signal SAIN.
[0033]
FIG. 6 is a diagram illustrating an example of a configuration of a part of the cascode / sense amplifier 17. FIG. 5 shows the sense amplifier portion of the cascode / sense amplifier 17. The sense amplifier portion compares the voltage corresponding to the amount of “leak current + offset current” with the voltage corresponding to the amount of “read cell current + leak current”, and determines “0” or “1”. Of data is determined.
[0034]
The sense amplifier 40 of FIG. 6 includes PMOS transistors 41 to 46, NMOS transistors 47 to 56, and a capacitor 57.
[0035]
Immediately after the read operation, a voltage signal SAIN corresponding to the amount of “leak current + offset current” is supplied from the pre-sense amplifier 30. At this time, since the signal ATD is HIGH, the voltage of the voltage signal SAIN is stored in the capacitor 57 via the transistor 47. Thereafter, when the voltage signal SAIN corresponding to the current amount of “read cell current + leakage current” is supplied from the pre-sense amplifier 30, the signal ATD is LOW and the signal ATDEQ is HIGH. Accordingly, the voltage of the voltage signal SAIN is supplied to the gate terminal of the transistor 52 via the transistor 48. At this time, a voltage corresponding to the amount of “leak current + offset current” stored in the capacitor 57 is supplied to the gate terminal of the transistor 51.
[0036]
The PMOS transistors 41 and 42 and the NMOS transistors 51 and 52 constitute a differential amplifier, and have a function of detecting and amplifying a difference between the gate terminal voltage of the transistor 51 and the gate terminal voltage of the transistor 52. The transistors 49 and 50 are provided for resetting, and when the signal RST becomes HIGH, the electric charge accumulated in the capacitor 57 is discharged.
[0037]
The comparison result detected by the differential amplifier is output as the data signal SODATA via the inverter formed by the PMOS transistor 45 and the NMOS transistor 53. This data signal SODATA is output to the outside of the nonvolatile semiconductor memory device 10 via the input / output buffer 12 of FIG.
[0038]
As described above, a voltage corresponding to the sum of the leak current and the offset current is generated in the pre-sense amplifier 30, and this voltage is held in the capacitor 57 of the sense amplifier 40. Is generated, and the voltage is compared with the voltage held in the capacitor 57 to perform data determination. That is, data determination based on a comparison between “read cell current + leak current” and “leak current + offset current” becomes possible.
[0039]
At this time, since the two currents to be compared both include the leak current, the leak current is canceled regardless of the magnitude of the leak current, and the data can be reliably determined. Further, since a reference cell is not required for reading and generating a reference potential, the circuit scale can be reduced and cost can be reduced. Further, since there is no need to boost the potential of the selected word line at the time of reading, a boosting circuit dedicated to the read word is not required, and the circuit size can be reduced and cost can be reduced.
[0040]
FIG. 7 is a timing chart for explaining a data read operation according to the present invention.
[0041]
First, by setting the signal RST to HIGH, the transistors 49 and 50 in FIG. 6 are made conductive, and the gate terminal of the transistor 51 and the gate terminal of the transistor 52, which are the voltage holding terminals of the capacitor 57, are reset by grounding. Thereafter, the signal RST is returned to LOW, and the bit line is selected during a period in which the signal ATD is HIGH. At this time, the word line has not been selectively activated. In this state, a leak current flows from the selected bit line via the overerased cell, and a voltage corresponding to “leak current + offset current” is held in the capacitor 57. After that, the signal ATD is returned to LOW, the signal ATDEQ is set to HIGH, and the word line is selectively activated to flow the current of the read memory cell to the selected bit line. As a result, a voltage corresponding to “read cell current + leakage current” is obtained. By comparing this voltage with the holding voltage of the capacitor 57, effective read data is obtained as the determination data SODATA. The timings of the signal RST, signal ATD, signal ATDEQ, word line activation, bit line selection, and the like are controlled by the control circuit 11 of the nonvolatile semiconductor memory device 10 shown in FIG.
[0042]
In the above-mentioned reading method, first, the signals ATD and ATDEQ are both set to HIGH to hold the reference data on both the reference side and the data side, and then the signals ATD and ATDEQ are set to LOW and HIGH respectively to select the word line. There is no need to precharge the level on the data side, and high-speed reading can be performed. The capacitor 57 in FIG. 6 can be realized with a small chip area by using a transistor capacitor or the like.
[0043]
As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.
【The invention's effect】
In the nonvolatile semiconductor memory device according to the present invention, since the two values to be compared both include the leak current, the leak current is canceled regardless of the magnitude of the leak current, and the data can be reliably determined. Further, since a reference cell is not required for reading and generating a reference potential, the circuit scale can be reduced and cost can be reduced. Further, since there is no need to boost the potential of the selected word line at the time of reading, there is no need for a boosting circuit dedicated to the read word, and the circuit scale can be reduced and cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a relationship between a read cell current and a reference cell current.
FIG. 2 is a diagram for explaining a read operation according to the present invention.
FIG. 3 is a diagram showing an example of a configuration of a nonvolatile semiconductor memory device according to the present invention.
FIG. 4 is a diagram showing an example of a configuration of a cell array and a column decoder.
FIG. 5 is a diagram showing an example of a partial configuration of a cascode / sense amplifier.
FIG. 6 is a diagram showing an example of a partial configuration of a cascode / sense amplifier.
FIG. 7 is a timing chart for explaining a data read operation according to the present invention;
[Explanation of symbols]
11 Control Circuit 12 Input / Output Buffer 13 Address Buffer 14 Row Decoder 15 Column Decoder 16 Cell Array 17 Cascode / Sense Amplifier 18 Write / Erase Circuit 19 Command Register

Claims (10)

A plurality of non-volatile memory cells;
A bit line to which the plurality of memory cells are connected;
A plurality of word lines connected to the plurality of memory cells;
Detecting a first current flowing through the bit line in a state where none of the plurality of word lines are activated, and a second current flowing through the bit line in a state where one of the plurality of word lines is selectively activated; And a sense amplifier circuit for detecting data based on the magnitude relationship between the sum of the first current value and the predetermined offset value and the second current value. apparatus. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a row decoder for selectively activating said word line at a voltage equal to or smaller than a power supply voltage supplied from outside. The sense amplifier circuit includes:
A pre-sense amplifier that detects a sum of the first current and a predetermined current and converts the sum into a first voltage, and detects the second current and converts the same into a second voltage;
2. The nonvolatile semiconductor memory device according to claim 1, further comprising a voltage comparison circuit for comparing said first voltage and said second voltage. The voltage comparison circuit is
A capacitor for holding the first voltage;
2. The nonvolatile semiconductor memory device according to claim 1, further comprising a comparator which receives the voltage held by said capacitor and said second voltage. The pre-sense amplifier detects the sum of the first current and the predetermined current at a first timing, converts the sum into the first voltage, and detects the second current at a second timing. Converting the voltage to the second voltage, the voltage comparison circuit holding the first voltage in the capacitor at the first timing, the voltage held by the capacitor at the second timing, and the second voltage 5. The non-volatile semiconductor memory device according to claim 4, wherein the comparison is made with: 6. The nonvolatile semiconductor memory device according to claim 5, wherein said voltage comparison circuit supplies said first voltage to both of two input terminals of said comparator at said first timing. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said comparator is a differential amplifier. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising an erasing circuit for erasing a predetermined group of said plurality of memory cells. 9. The non-volatile semiconductor memory device according to claim 8, wherein said plurality of memory cells include over-erased cells which flow current in a state where none of said plurality of word lines are activated. A first current, which is the sum of a leak current flowing through the bit line at a first timing and a predetermined current, is detected. A non-volatile semiconductor memory device, comprising: a sense amplifier circuit that detects a certain second current and determines data based on a magnitude relationship between the first current value and the second current value.

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